KR100850092B1 - Spice model extraction for cmos devices - Google Patents

Abstract

The present invention relates to a measurement pattern design method that can be applied to a process of 130 nm and below, and to a SPICE modeling method that enables circuit simulation of electrical characteristics considered important in a nanometer-scale CMOS device. In other words, the present invention provides accurate analysis of device characteristic changes due to leakage current, STI stress effect, and the SPICE modeling technique, which are not previously considered in the case of CMOS devices having a line width of 130 nm or less. According to the requirements, we propose a method of designing the measuring device structure to model these phenomena, and then apply the BSIM4 model to the measured values of the device obtained from the proposed structure and apply the gate tunneling current and gate induced drain leakage. Accurate modeling of current, STI stress effects, etc.

Modeling, BSIM, CMOS, SPICE

Description

SPICE modeling method for CMOS devices {SPICE MODEL EXTRACTION FOR CMOS DEVICES}

1 is a measurement pattern layout of a narrow width device according to an embodiment of the present invention;

2 is a test pattern layout diagram of a gate poly according to an embodiment of the present invention;

3 is a diagram illustrating a general parameter extraction procedure of a BSIM4 model;

4 is an exemplary binning matrix of a BSIM4 model according to an embodiment of the present invention;

5 is an exemplary view comparing Id-Vds and Id-Vgs characteristics and simulation values of 10um / 0.13um and 0.15um / 0.13um devices according to an exemplary embodiment of the present invention.

6 is an exemplary diagram illustrating a gate tunneling leakage current component of a general NMOS device;

7 is a view illustrating a comparison between modeling results using a gate tunneling leakage current parameter of a BSIM4 model and measured values of 10 um / 0.13 um NMOS and PMOS devices according to an embodiment of the present invention;

8 is an exemplary view of modeling a 10um / 0.13um NMOS and a PMOS with a GIDL parameter according to an embodiment of the present invention;

9 is a graph showing Id-Vgs and Id-Vds graphs according to the length between poly and active SAs of the 10um / 0.13um NMOS and PMOS devices of the present invention.

10 is an exemplary graph illustrating Vth and Idsat trends according to the length between poly and active of 10um / 0.13um NMOS and PMOS transistors of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit simulator, and in particular, to a measurement pattern design method that can be applied to a process of 130 nm and below, and electrical characteristics considered important in nanometer-scale Complementary Metal-Oxide-Semiconductor devices. The present invention relates to a simulation program with integrated circuit emphasis (SPICE) model that enables circuit simulation.

Typically, in fabricating an electronic circuit, a simulation is performed before fabricating the actual electronic circuit. This simulation minimizes the trial and error that can occur during the actual circuit fabrication. SPICE is one of the simulation programs and simulates a semiconductor integrated circuit using model data, device parameter data and design data. .

Meanwhile, in recent years, the digital and analog functions, which are represented as System On Chips, are mixed to limit the memory capacity of single chip, increasing SRAM, etc. In order to develop chips that increase speed, reduce power consumption, and suppress heat generation, CMOS process technology has been actively refined due to the high integration to be installed in the market, the operation speed beyond GHz, and the appearance of mobile products such as mobile phones. ought.

In addition, the development cost is reduced in response to the high cost of the reticle manufacturing process due to the advancement of the process and the large diameter of the wafer, and the new product is made early as the product life cycle is shortened. In order to enter the market, mask revision should be minimized during product development, and the highly accurate SPICE model is one means of implementing this.

Therefore, in addition to the IV characteristics in the transistor operating region, electrical characteristics such as leakage current and shallow trench isolation (STI) effects that were previously overlooked should be reflected in the model. It is required to have a closer form.

Accordingly, an object of the present invention is to provide a measurement pattern design method that can be applied to a process of 130 nm and below, and a SPICE modeling method that enables circuit simulation of electrical characteristics considered important in a nanometer-scale CMOS device. have.

The present invention for achieving the above object is a SPICE modeling method of a CMOS device, (a) manufacturing the CMOS device, (b) measuring data on the various electrical characteristics of the manufactured CMOS device and (c) setting a set of SPICE model parameters using the measured data, (d) extracting a gate tunneling leakage current and a GIDL parameter of the BSIM4 model, and (e) the SPICE model parameter values And measuring the characteristics of the CMOS device using the gate tunneling leakage current and a GIDL parameter.

Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

In order to reduce the area occupied by the TEG, the number of transistors used for the SPICE model is more than 20. In general, a part of the transistor terminals is commonly bundled. However, in the case of the conventional SPICE model as described above, there is a problem in that the current flowing through each transistor terminal cannot be measured for each transistor. Accordingly, in the test pattern proposed in the present invention, transistor terminals are disposed in pads to measure gate leakage current and gate induced drain leakage (GIDL).

In addition, in order to protect the gate oxide film from being destroyed by plasma or ESD during the semiconductor unit process, it is common to attach a protection diode, but in the present invention, such a protection diode is removed by removing the protection diode. When measuring the current, the forward operation of the diode (diode) to avoid excessive value is measured. However, in this case, since abnormal leakage current due to the destruction of the gate oxide may occur during the measurement operation for modeling, it is necessary to increase the number of measurement samples and process the missing data to prevent the characteristics of the broken transistor from being reflected in the model. desirable.

As described above, the layout design of the device should be made in accordance with the purpose of modeling, and also minimize the possibility of deformation of the measurement pattern that may occur during the semiconductor unit process, or be careful not to cause the deformation of the pattern in the region acting as a transistor. shall. As an example, the following two cases are presented in the present invention.

1 illustrates a measurement pattern layout of a narrow width device according to an exemplary embodiment of the present invention. In the design of a measurement pattern for a SPICE model of a CMOS transistor, FIG. When the width of the source / drain region in which the contact for forming the electrode is located is small, the “H” or “c” shape layout is performed as shown in FIG. 1. In this case, even though the edge where the source / drain region where the transistor region and electrode contact are placed is vertically laid out, the semiconductor gate width is formed in a rounded “U” shape in the silicon after the semiconductor process. It can be larger or smaller.

This can cause errors in the model for transistor electrical characteristics items that are affected by the gate width. In order to improve this, if the corner is placed only on one side in the form of "c" as shown in (b) of FIG. 1, the above-described effect occurs only on one side, thereby reducing the possibility of error. This effect of the etching process also in the pattern formation of the gate poly, the gate length in silicon at both ends of the gate poly may be thinner or thicker than the layout.

FIG. 2 is a diagram illustrating a test pattern layout of a gate poly according to an exemplary embodiment of the present invention. If the distance from the active edge of the poly end denoted by AA in FIG. It can also occur at the gate poly inside the active region, which can cause the electrical characteristics of the transistors to appear unrealistic. Accordingly, the present invention prevents this by defining AA about three times larger than the minimum line width of the gate poly.

In addition, it is common to prevent the deformation of the pattern and to reproduce it in the silicon according to the pattern during the layout design by optimizing the OPC rules in the semiconductor process, but since the pattern design for the modeling is usually performed at the same time as the TEG design, The pattern design method proposed in the present invention can provide better pattern reliability with optimization of OPC rules.

On the other hand, the refinement of the process and the introduction of new process means, such as STI, show the electrical characteristics of new devices that have not been seen before, and the SPICE model for circuit design is also being developed to reflect this. The BSIM4 model is widely adopted in the semiconductor field to model device characteristics of 65nm technology at 0.18um. This model includes drain induced threshold voltage shift (DITS) due to a pocket implant, reduction of output resistance in long channel devices, and body bias of reverse short channel effect (RSCE). Bias dependence was improved to improve the IV characteristic model of the device, as well as layout dependence of device leakage current, current STI effect, well proximity effect such as gate leakage current, gate induced drain leakage (GIDL), etc. In addition, RF-related characteristics of MOS devices can be newly modeled. In particular, the modeling of leakage current improves the accuracy of circuit simulation when designing low power consumption products, and improves the accuracy of simulation by STI effect modeling to predict IV characteristic change according to active area.

3 illustrates a general parameter procedure applied when using the BSIM4 model. In the present invention, a method and a result of modeling the BSIM4 model using the BSIM4 model applied to the 0.13 um process are presented.

A binning model that splits the entire range of transistor gate sizes supported by a particular CMOS process by length and width, models each parameter set in each bin, and then binds them together, although the size of the transistor Since the dependence of the parameter on an empirical method is weak, the physical meaning of the parameter value is weak, but the modeling accuracy of each interval is global, modeling the full range of transistor available sizes with one parameter set. There is an advantage over the model. In addition, even if a process has size dependencies that cannot be supported by a particular model, its modeling follows an empirical procedure, allowing more flexibility than global models.

FIG. 4 is a diagram illustrating how the intervals of the BSIM4 binning model obtained as a result of the present invention are divided, and a portion close to the minimum value of the gate length and width is finely divided so that the reverse according to the gate length and width is performed. The short short channel effect and the narrow width effect are well reflected. 5 is a diagram comparing the measurement and simulation values of the Id-Vds and Id-Vgs characteristics of the 10um / 0.13um and 0.15um / 0.13um devices, and shows that the maximum error is less than 3%.

FIG. 6 illustrates a path of leakage current passing through the gate oxide film and flowing into the source / drain region. As shown in FIG. 6, the leakage current passing through the gate oxide film and reaching the source / drain region depends on the path. It can be divided into five. The current components Igs and Igd, which flow directly from the double gate to the diffusion region of the source or drain, are proportional to the transistor channel width, and the current components Igcs, Igcd, and bulk that flow across the channel from the gate to the diffusion region of the source or drain. Igb, which flows directly into the bulk, is proportional to the amount of current in the gate area. Therefore, in the present invention, since the 10um / 10um transistor shows the largest leakage current, it is advantageous to use the transistor of this size first.

7 is a view comparing the results of modeling using the gate tunneling leakage current parameter of the BSIM4 model according to the present invention with the measured values of 10um / 0.13um NMOS and PMOS devices. We can see that we have successfully modeled variations in voltage.

At this time, the GIDL current has a strong dependency on the drain-gate applied voltage and a weak body bias. The depletion region is strongly generated in the region overlapping with the drain under the gate poly due to the high electric field across the gate oxide, and the generated electron and hole flows between the gate and the drain by band to band tunning. Known. 8 shows the results of modeling 10um / 0.13um NMOS and PMOS with GIDL parameters.

On the other hand, physical stress caused by shallow trench isolation (STI) decreases mobility and increases threshold voltage in the case of NMOS, leading to a decrease in drain current. This reduction in electrical characteristics is a function of the length of the active region in the same direction as the current direction of the transistor, making short channel devices particularly sensitive. PMOS devices tend to be opposite to NMOS.

FIG. 9 is a graph comparing Id-Vgs and Id-Vds curves with measured and simulated values when the distance (SA) from one gate active to one active of the transistor is changed from 0.67um to 13.3um according to an exemplary embodiment of the present invention. As the SA is changed, the mobility and the drain current decrease with increasing NMOS and increasing PMOS. A graph showing this trend according to the SA change is shown in FIG. 10.

As described above, in the present invention, the SPICE modeling technique that can be applied to the process of 130 nm or less is designed by using the BSIM4 model. The fabrication process used was a 130nm process of fab2, which designed a transistor layout to minimize errors in the size dependence of transistor electrical characteristics due to the pattern deformation of silicon, and improved the pad layout method to easily measure leakage current. The gate tunneling leakage current and GIDL parameters of the BSIM4 model were extracted and the STI effect was used to accurately model the phenomenon of transistor characteristics changing according to the size of the active region.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

As described above, the present invention provides accurate analysis of device characteristic changes due to factors for leakage current and STI stress effect, which have not been previously considered in the case of a CMOS device having a line width of 130 nm or less, and accordingly According to the requirements of the SPICE modeling technique, we propose the method of designing the measuring device structure to model these phenomena.The BSIM4 model is applied to the measured values of the device obtained from the proposed structure, and the gate tunneling current, GIDL ( Gate Induced drain leakage The advantage of accurately modeling the current, STI stress (stress effect), etc. is an advantage.

Claims (3)

SPICE modeling method of a CMOS device, (a) manufacturing the CMOS device, (b) measuring various electrical property data of the manufactured CMOS device; (c) setting a set of SPICE model parameters using the measured data; (d) extracting the gate tunneling leakage current and GIDL parameters of the BSIM4 model; (e) measuring characteristics of the CMOS device using the SPICE model parameter value, the gate tunneling leakage current, and a GIDL parameter SPICE modeling method of the CMOS device comprising a. The method of claim 1, In the step (c), the parameters of the SPICE model, SPICE modeling method of the CMOS device, characterized in that modeled to analyze the gate leakage current and the STI stress effect of the CMOS device. The method of claim 1, The CMOS device is a SPICE modeling method of the CMOS device, characterized in that the CMOS device is 130nm or less.

Images