KR100843615B1 - Efficient dual frame buffer control device and the same method - Google Patents

Abstract

The present invention relates to a dual frame buffer control device and a method thereof. According to a preferred embodiment of the present invention, there is provided an apparatus comprising: a first buffer and a second buffer, in which previous frame data is optionally recorded; A write buffer controller for generating a buffer status check signal when frame data is input; A read buffer controller that reads the previous frame data recorded in either the first buffer or the second buffer; And a frame controller which, when the buffer status check signal is input, calculates a remaining read time of the previous frame data to be read out and compares the estimated frame time to determine whether the frame data can be written and a buffer to be stored. Control devices may be provided. Therefore, according to the present invention, it is possible to display the latest image data (ie, frame data) generated from the image sensor without discarding it.

Dual Buffer, Control, Frame Data

Description

Effective dual frame buffer control device and the same method

1 is a diagram illustrating a frame transfer process through a conventional single frame buffer.

Figure 2 is a block diagram of a dual frame buffer control device according to an embodiment of the present invention.

3 is an internal block diagram of a frame controller according to an embodiment of the present invention.

4 is a flowchart illustrating a method of writing frame data output from an image sensor to a buffer at predetermined time intervals according to an exemplary embodiment of the present invention.

5 is a diagram illustrating synchronization according to frame data output, frame data storage of a first controller, and frame data reading of a second controller at predetermined time intervals of an image sensor according to an exemplary embodiment of the present invention.

FIG. 6 illustrates frame data written and / or read into a buffer according to FIG. 5; FIG.

<Explanation of symbols for the main parts of the drawings>

310: check time indicating unit

315: RRT calculator

320: FWT register

325: comparison unit

330: recording buffer selection unit

The present invention relates to a dual frame buffer control device and a method thereof, and more particularly, to a dual frame buffer control device and a method capable of displaying a frame image recently output from the sensor.

1 is a diagram illustrating a frame data transfer process through a conventional single buffer. Referring to FIG. 1, a process of transferring frame data through a single buffer is briefly described. In general, there is a difference in a speed at which frame data is generated by an image sensor and a speed in reading frame data stored in a buffer. Thus, referring to 110 of FIG. 1, after the frame data is output from the image sensor, after a predetermined delay time, the write buffer controller writes the first frame data in the first buffer. After writing of the write buffer controller is completed, the read buffer controller accesses the first buffer and starts reading the first frame data.

In response to a preset synchronization time at 120, the image sensor outputs the second frame data, and after a predetermined delay time, the write buffer controller checks the state of the first buffer for writing the second frame data. However, as shown in Fig. 1 , since the frame data read time is slow, the write buffer controller cannot access the first buffer. As a result, the write buffer controller cannot discard the second frame data in the first buffer and discards it.

As described above, when a single buffer is provided, a problem arises in that a large amount of frame data cannot be written to the buffer due to the difference between the read time and the write time from the buffer data.

Accordingly, an object of the present invention for solving the above problems is an effective dual frame buffer control device capable of displaying the latest image data (ie, frame data) generated from an image sensor without using a dual frame buffer and its To provide a way.

It is another object of the present invention to provide an effective dual frame buffer control apparatus and method for providing image data in more real time to a user by minimizing dropping.

Other objects of the present invention will be easily understood through the description of the following examples.

In order to achieve the above object, according to an aspect of the present invention, there is provided a dual frame buffer control device capable of storing the latest frame data input from an imaging sensor such as an image sensor.

According to a preferred embodiment of the present invention, there is provided an apparatus comprising: a first buffer and a second buffer, in which previous frame data is optionally recorded; A write buffer controller for generating a buffer status check signal when frame data is input; A read buffer controller that reads the previous frame data recorded in either the first buffer or the second buffer; And a frame controller which, when the buffer status check signal is input, calculates a remaining read time of the previous frame data to be read out and compares the estimated frame time to determine whether the frame data can be written and a buffer to be stored. Control devices may be provided.

The frame controller may further include: a check time indicating unit for instructing calculation of a remaining read time of the frame data when the buffer status check signal is input; An RRT calculator configured to calculate a remaining frame read time of the previous frame data being read by the second controller according to the read time calculation instruction signal; An FWT register storing a recording time of the frame data; A comparator for generating a recordable indication signal by comparing the calculated remaining frame read time with the write time; And a write buffer selector configured to select a recordable buffer from the first buffer or the second buffer according to the recordable instruction signal and to transmit a write instruction signal to the write buffer controller.

The RRT calculator may calculate the remaining frame read time using the total size of the previous frame data and the size of the read data.

The comparator may generate the recordable indication signal and transmit the generated recordable indication signal to the write buffer selector when the calculated remaining frame read time is greater than the write time.

The comparison unit generates a discard instruction signal and transmits the discard instruction signal to the write buffer selector when the write time is greater than the calculated remaining frame read time, wherein the write buffer selector transmits the frame to the write buffer controller when the discard instruction signal is input. The discarding of data can be indicated.

The first buffer or the second buffer may each include a status register.

The write buffer controller and the read buffer controller update the status register of the buffer being accessed to the first state, and when the access is terminated, update to the second state, except that the buffer in which the status register is the first state is accessed except the controller being accessed. This is impossible, and the buffer may be either the first buffer or the second buffer.

According to another aspect of the present invention, there is provided a method of controlling a dual frame buffer such that the dual frame control device can record the latest frame data output through the image sensor.

According to a preferred embodiment of the present invention, a method of controlling a dual frame buffer so that the dual frame control device can record the latest frame data output through the image sensor, the frame data input from the recording buffer controller through the image sensor Receiving a buffer status check signal correspondingly; Calculating a remaining read time of previous frame data being read by a read buffer controller corresponding to the buffer status check signal; Comparing the remaining read time with a preset recording expected time; Selecting a buffer to record the frame data when the remaining read time is greater than the estimated recording time; And writing, by the write buffer controller, the frame data to the selected buffer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Numbers (eg, first, second, etc.) used in the description of the present specification are merely identification symbols for sequentially distinguishing identical or similar entities.

2 is a block diagram of an image pickup device according to an exemplary embodiment of the present invention, and FIG. 3 is an internal block diagram of a frame controller according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an imaging device according to an exemplary embodiment of the present invention includes an image sensor 210, an image signal processor 215, a dual buffer controller 200, a controller, and a display 250. do.

The image sensor 210 is an image pickup device in which an optical image corresponding to an external image (that is, a subject) is formed. The image sensor 210 converts a light signal of the optical image into an analog signal, which is an electrical signal, and is included in the image sensor 210. The digital signal is converted into a digital signal through an image signal processor 215 and output to the image signal processor 215.

That is, the image sensor 210 may photograph the subject at a predetermined time interval and output image data to the image signal processor 215 at each time interval. Hereinafter, image data output from the image sensor 210 to the image signal processor 215 will be referred to as Bayer image data.

In addition, the image sensor 210 may be implemented as a charge coupled device (CCD: hereinafter referred to as "CCD") or a complementary metal oxide semiconductor (CMOS) hereinafter referred to as "CMOS". Can be.

The image signal processor 215 converts the Bayer image data input from the image sensor 210 to correspond to a predetermined format (eg, YUV format, RGB format, etc.). For example, the image signal processor 215 may perform preprocessing such as enlargement, reduction, rotation, error correction, gamma correction, white correction, etc. of the Bayer image data. It is also possible to decode the image data.

Hereinafter, the image data output from the image signal processing unit 215 will be referred to as "frame data".

As shown in FIG. 2, the dual frame control apparatus 200 according to the present invention includes a write buffer controller 220, a first buffer 225, a second buffer 230, a read buffer controller 240, and a frame buffer. It is configured to include a controller 235.

The write buffer controller 220 selects either the first buffer 225 or the first buffer 225 according to the control of the frame buffer controller 235, and outputs the predetermined time interval from the image signal processor 215. The function of recording the frame data is performed.

In the present specification, the "buffer status check signal" means that the write buffer controller 220 controls the frame buffer controller to indicate when the frame buffer controller 235 should check the states of the first buffer 225 and the second buffer 230. It is defined as a control signal output to 235.

In addition, when frame data is input from the image signal processor 215, the write buffer controller 220 may generate a state check control signal and transmit the state check control signal to the frame buffer controller 235.

The first buffer 225 or the second buffer 230 is a storage area in which frame data is recorded by the write buffer controller 220. In addition, the first buffer 225 and the second buffer 230 indicate whether each buffer is accessed by an arbitrary controller (for example, the write buffer controller 220 or the read buffer controller 240). It may also include a status register (not shown) that may indicate. Here, the status register is updated to the first state (for example, high) by the accessed controller (for example, the write buffer controller 220 or the read buffer controller 240), and then access is terminated. The controller may update the status register of the accessed buffer to a second state (for example, low) to enable access by another controller.

The read buffer controller 240 reads the frame data recorded in either the first buffer 225 or the second buffer 230 under the control of the frame buffer controller 235, and transfers the frame data to the controller 245. To perform. In addition, the read buffer controller 240 includes an interface unit (not shown) that can be connected to an external display device (for example, an LCD, etc.) to be combined with the display device through the corresponding interface unit to provide frame data to the display device. You can also pass it. In the present specification, the dual frame buffer control apparatus 200 includes a control unit 245 and will be described with an emphasis on transferring frame data to the display unit 250.

Here, if the read buffer controller 240 alternately selects the first buffer 225 or the second buffer 230 (that is, reads the frame data recorded in the first buffer 225 at the time t-1), At time t, the frame data recorded in the second buffer 230 may be read out, that is, the frame data recorded in the buffer is read out by alternately selecting the first buffer 225 and the second buffer 230. I can ship it.

The frame buffer controller 235 checks the state of the first buffer 225 or the second buffer 230 to record or discard the frame data input from the image signal processor 215 to the write buffer controller 220. Determining the function.

Referring to FIG. 3, the frame buffer controller 235 includes a check time indicator 310, an RRT calculator 315, an FWT register 320, a comparator 325, a write buffer selector 330, and a read buffer selector. It comprises a unit 335.)

When the state check control signal is input from the write buffer controller 220, the check time indicating unit 310 instructs the control signal (hereinafter, referred to as "RRT") to calculate the RRT (remain read time). Control signal ") to the RRT calculator 315. The " control signal &quot;

When the RRT calculation control signal is input from the check time indicating unit 310, the RRT calculator 315 may access a buffer accessed by the read buffer controller 240 (for example, the first buffer 225 or the second buffer 230). The remaining frame data reading time is calculated and transmitted to the comparison unit 325.

For example, the RRT calculating unit 315 reads the remaining data using the total size of the frame data and the size of the data read from the check point indicating unit 310 to the time point at which the RRT calculation indicating signal is input. Can be calculated.

The FWT register 320 stores the estimated time of writing frame data to be written to either the first buffer 225 or the second buffer 230 by the write buffer controller 220. Here, the estimated write time stored in the FWT register 320 may vary depending on the size of the frame data. The estimated write time is calculated by the processor (not shown) at the time when the frame data is written to either the first buffer 225 or the second buffer 230 by the write buffer controller 220, and then the FWT register. And stored at 320.

For example, the estimated recording time is calculated by the processor (not shown) according to the user's selection of the image size through preset menu information through the display unit 250 to take a picture, and thus the FWT register 320. Can be stored in. Therefore, only when the user performs an operation of changing the image size, the estimated recording time recorded in the FWT register 320 is calculated corresponding to the image size selected by the user and then stored in the FWT register 320 by the processor. Can be.

When the frame data read time calculated from the RRT calculator 315 is input, the comparator 325 approaches the FWT register 320 to read the estimated recording time and compare the frame data read time with the corresponding frame data read time. The comparator 325 compares the frame data read time and the estimated recording time to determine whether the frame data inputted to the write buffer controller 220 can be recorded, and then generates a control signal when the record data can be written to the write buffer selector ( 330).

The write buffer selector 330 selects a recordable buffer among the first buffer 225 or the second buffer 230 according to the control signal input from the comparator 325. The write buffer selector 330 generates a signal including the selected buffer information (hereinafter, referred to as a "buffer select signal") and transmits the signal to the write buffer controller 220. Accordingly, the write buffer controller 220 may write a frame data input from the image signal processor 215 corresponding to the buffer selection signal input through the write buffer selector 330 (eg, the first buffer). 225 or the second buffer 230.

The read buffer selector 335 temporarily records the most recent buffer information that the read buffer controller 240 has accessed to read frame data stored in the buffer. The read buffer selector 335 generates a read buffer select signal to select another buffer so that the read buffer controller 240 can read the next frame data subsequent to the frame data read recently, and then the read buffer controller 335. And transmit to 240.

For example, assume that the read buffer controller 240 approaches the second buffer 230 to read the third frame data at time t-1. Then, the read buffer selector 335 may read the first buffer (240) so that the read buffer controller 240 approaches the first buffer 225 at time t to read the frame data closest to the third frame data. 225) The read buffer selection signal including the selection information may be generated and transmitted to the read buffer controller 240.

Referring again to FIG. 2, the display 250 is a means for displaying frame data input from the second controller 240 through the image signal processor 215 under the control of the controller 245. For example, the display unit 135 may be a liquid crystal display (LCD).

The controller 245 may be configured as internal components of the dual frame control apparatus 200 (eg, the image sensor 210, the image signal processor 215, and the write buffer controller 220) according to an exemplary embodiment of the present invention. , The first buffer 225, the second buffer 230, the frame buffer controller 235, the read buffer controller 240, and the display unit 250).

4 is a flowchart illustrating a method of writing frame data output from an image sensor to a buffer at predetermined time intervals according to an exemplary embodiment of the present invention. Hereinafter, an operation process after the arbitrary frame data is output from the image sensor 210 in correspondence with a preset synchronization signal will be described.

In operation 410, the write buffer controller 220 receives arbitrary frame data from the image sensor 210. Hereinafter, in order to distinguish it from frame data previously output from the image sensor 210, it will be referred to as "T frame data" for convenience. In addition, it will be described on the assumption that the first buffer 225 and the second buffer 230 store T-1 frame data and T-2 frame data, which are output in time earlier than the T frame data. In addition, it will be described on the assumption that the read buffer controller 240 reads the T-2 frame data by accessing the first buffer 225.

In step 415, the write buffer controller 220 sends a signal indicating a check whether or not the T frame data may be stored (hereinafter, referred to as a "buffer status check signal") to the check point indicating unit (see below) of the frame buffer controller 235. 310). As a result, the check time indicating unit 310 may know that the write buffer controller 220 receives the T frame data from the image sensor 210 at the present time.

Accordingly, in operation 420, the check time indicator 310 may output a signal indicating the calculation of the remaining read time (ie, RRT) of the frame data currently being read by the read buffer controller 240. To pass. In addition, the check time indicating unit 310 may transmit a signal (hereinafter, referred to as a "comparison indicating signal") instructing the comparison unit 325 to compare the RRT and the FWT.

For example, the check time indicator 310 may calculate an RRT and calculate the calculated RRT to determine whether to record or discard the frame data in either the first buffer 225 or the second buffer 230. A comparison of the FWTs can be indicated.

Here, in the present specification, the check time indicating unit 310 transmits a signal instructing the RRT calculation to the RRT calculating unit 315 corresponding to the buffer state check signal input from the write buffer controller 220, and calculates the calculated RRT and FWT. Although the description focuses on transmitting a signal indicative of the comparison of R, the RRT calculated from the RRT calculating unit 315 is input according to an implementation method, and it is natural that the FWT may be read out and compared to the RRT and the FWT. .

In operation 425, the RRT calculator 315 calculates the remaining time of the frame data being read by the read buffer controller 240 in accordance with the RRT calculation instruction signal input from the check time indication unit 310, and compares the comparison unit 325. To pass).

For example, the RRT calculator 315 may calculate the RRT using the total size of the frame data stored in the accessed buffer and the size of the read frame data.

In operation 430, the comparator 325 reads and compares the input RRT and the pre-stored FWT from the FWT register 320 from the RRT calculator 315.

If the RRT is larger than the FWT, in step 435, the comparator 325 transmits a signal indicating the recording of the T frame data to the write buffer selector 330. RRT and FWT will be described in more detail below with reference to the associated drawings.

For example, if the RRT is larger than the FWT, it means that a buffer that is not accessed by the read buffer controller 240 can be accessed through the write buffer controller. Also, since the frame data input to the current write buffer controller 220 is a more recent image than the frame data stored in another buffer (that is, a buffer not accessed by the read buffer controller 240), the frame buffer controller 235 is T. Transfers a signal instructing the recording of frame data.

In operation 440, the write buffer selector 330 selects a recordable buffer from the first buffer 225 or the second buffer 230 by referring to the status register of each buffer and transmits the writeable buffer to the write buffer controller 220.

For example, the write buffer selector 330 may access the buffer's status register to know the status of the buffer. That is, the buffer that is being accessed by the read buffer controller 240 (for example, the first buffer 225 or the second buffer 230) has a status register set by the read buffer controller 240 in the first state (for example, For example, high). Similarly, the buffer being accessed by the write buffer controller 220 may be updated by the write buffer controller 220 with the status register to the first state. Of course, the buffer in which the status register is updated to the first state by the write buffer controller 220 and the read buffer controller 240 is stored in the corresponding controller (for example, the write buffer controller 220 or the read buffer controller 240). When the access is terminated, the status register may be updated to a second state (eg, low) by the controller.

Of course, in more detail, when the buffer is implemented in connection with a chip selector, the write buffer selector 330 may enable, disable or disable the chip selector of the write buffer controller 220. The recordable buffer may be selected and transferred to the write buffer controller 220 using the control signal and the control signal of the read buffer controller 240. An operation process of the chip selector (not shown) is obvious to those skilled in the art, and thus a separate description thereof will be omitted.

For example, when the first buffer 225 is in the first state, the write buffer selector 330 may select the second buffer 230 and transmit a write command to the write buffer controller 220.

In operation 445, the write buffer controller 220 transmits the T frame data from the image sensor 210 to the buffer selection signal input from the recording buffer selector 330 in step 410 corresponding to the data recording signal. For example, the second buffer 230 may be written.

However, if the RRT is smaller than the FWT, the comparator 325 transmits a write disable signal to the write buffer controller 220 through the write buffer selector 330 in step 450. Accordingly, the write buffer controller 220 may discard the T frame data input from the image sensor 210 without writing to either the first buffer 225 or the second buffer 230.

5 is a diagram illustrating synchronization according to frame data output, frame data storage of a first controller, and frame data reading of a second controller at predetermined time intervals of an image sensor according to an exemplary embodiment of the present invention. FIG. 6 is a diagram illustrating frame data written and / or read into a buffer according to FIG. 5.

Hereinafter, for convenience of description, image data output from the image sensor 210 at predetermined time intervals (for example, a predetermined synchronization time) will be collectively described as frame data. In addition, frame data output first in time order will be referred to as first frame data, and frame data thereafter as second frame data.

Referring to FIG. 5, 510 is a synchronous time at which the image sensor 210 outputs frame data at predetermined time intervals, and 520 is a frame buffer output from the image sensor 210. An example of time for storing in either the first buffer 225 or the second buffer 230 is shown. In addition, 530 illustrates the time when the read buffer controller 240 accesses either the first buffer 225 or the second buffer 230 to read recorded frame data.

As shown in 510, 520, and 530 of FIG. 5, a synchronization time for recording frame data and a synchronization time for reading frame data are generally set differently. In addition, since the time for recording the frame data requires a short time compared to reading the frame data, as shown in FIG. 5, the synchronization time according to the frame data recording is relatively higher than the synchronization time due to the frame data reading. It is assumed that it is designed to be short.

When the image sensor 210 outputs the first frame data as shown in 511, the write buffer controller 220 writes the first frame data to the first buffer 225 at a predetermined time interval. Since it takes a while to transfer the first frame data from the image sensor 210 to the write buffer controller 220, as shown in 511 and 521, after the first frame data is output from the image sensor 210. A predetermined time delay occurs to be written to the first buffer 225 by the write buffer controller 220.

As shown in 511 and 521, the write buffer controller 220 receives multiple frame data from the image sensor 210 at the same time and does not output them simultaneously, but when the first frame data is input from the image sensor 210, The first frame data may be recorded in the first buffer 225. In FIG. 6, the first frame data is recorded in the first buffer 225.

The read buffer controller 240 may start reading the first frame data after the writing of the first frame data in the first buffer 225 is completed by the write buffer controller 220 as shown in 431.

At 512, when the image sensor 210 outputs the second frame data, the write buffer controller 220 writes the second frame data to the second buffer 230 after a predetermined time delay, as shown at 522. do. Since the read buffer controller 240 approaches the first buffer 225 and reads the first frame data, the write buffer controller 220 may write the second frame data to the second buffer 230. . Referring to 520 of FIG. 5, first frame data is recorded in the first buffer 225, and second frame data is recorded in the second buffer 230.

If the image sensor 210 outputs the third frame data at 513, after a predetermined time delay, the write buffer controller 220 outputs a control signal corresponding to whether the third frame data can be written from the frame buffer controller 235. The third frame data is written to the first buffer 225 under the control of the frame buffer controller 235.

In more detail, referring to 513 and 523 of FIG. 5, after the read buffer controller 240 finishes reading the first frame data, the read buffer controller 240 approaches the second buffer 230 to start reading the second frame data. As a result, the first buffer 225 is idle at the present time. Therefore, the frame buffer controller 235 may transmit a signal instructing the writing of the third frame data to the first buffer 225 to the write buffer controller 220. As a result, the write buffer controller 220 may write the third frame data to the first buffer 225.

When the read of the first frame data is completed, the read buffer controller 240 approaches the second buffer 230 to read the second frame data.

In operation 514, when the image sensor 210 outputs the fourth frame data corresponding to the preset synchronization signal, the write buffer controller 220 may provide a control signal corresponding to whether the fourth frame data may be written after a predetermined delay time. It receives from the frame buffer controller 235.

Referring to 550, the image sensor 210 outputs fourth frame data corresponding to a preset synchronization signal. The fourth frame data is input to the write buffer controller 220 after the predetermined delay time. In addition, the recording buffer controller 220 receives the fourth frame data from the image sensor 210 and reads the data based on a time point 524 in which the recording buffer controller 220 writes the fourth frame data to either the first buffer 225 or the second buffer 230. The time remaining until the buffer controller 240 completes reading of the second frame data (ie, RRT) is relatively longer than the time required for the write buffer controller 220 to write the fourth frame data to the buffer (ie, FWT). (Of course, here, the time required to write the fourth frame data into the buffer (ie, FWT) and the time remaining until completion of reading out the second frame data (ie, RRT) may be the same).

Accordingly, in such a case, the frame buffer controller 235 transmits a control signal instructing the writing of the fourth frame data to the write buffer controller 220. As a result, the write buffer controller 220 approaches the first buffer 225 and records the fourth frame data. Here, the write buffer controller 220 cannot access the second buffer 230 because the read buffer controller 240 is connected to the second buffer 230.

The state of the buffer after writing of the fourth frame data by the write buffer controller 220 is illustrated in 640 of FIG. 6.

In addition, as shown at 550, the recording of the fourth frame data is first completed by the write buffer controller 220, and then the reading of the second frame data is completed by the read buffer controller 240. Accordingly, when the read buffer controller 240 approaches the first buffer 225 by the write buffer controller 220 to read the next frame data, the read buffer controller 240 approaches the first buffer 225 to read the fourth frame data. Start reading.

Referring to block 560 of FIG. 5, the image sensor 210 outputs fifth frame data corresponding to a preset synchronization signal (or synchronization time). After a predetermined delay time, the write buffer controller 220 receives the fifth frame data. The write buffer controller 220 approaches the second buffer 230 to record the fifth frame data. The state of the buffer after the writing of the fifth frame data by the write buffer controller 220 is completed is illustrated at 650 of FIG. 6.

Referring to 570 of FIG. 5, the image sensor 210 outputs sixth frame data in response to a preset synchronization signal. As described above, after the predetermined delay time, the write buffer controller 220 receives the sixth frame data. Here, the remaining read time of the fifth frame data being read by the read buffer controller 240 is recorded at the time 526 when the write buffer controller 220 receives the sixth frame data via the image sensor 210. Since it is larger than the expected time, the write buffer controller 220 approaches the first buffer 225 and records the sixth frame data. The state of the buffer after the writing of the sixth frame data by the write buffer controller 220 is completed is illustrated in 660 of FIG. 6.

Referring to 580 of FIG. 5, the image sensor 210 outputs seventh frame data in response to a preset synchronization signal. After a predetermined delay time, the write buffer controller 220 receives the seventh frame data. Here, the frame buffer controller 235 calculates and compares the fifth frame data read completion time of the read buffer controller 240 and the seventh frame data write completion time of the write buffer controller 220. As shown in 580, the frame buffer controller may be completed since the point at which the read buffer controller 240 completes the fifth frame data read is completed relatively earlier than the point at which the write buffer controller 220 has finished writing the seventh frame data. 235 transmits a control signal indicating that the seventh frame data is not written to the write buffer controller 220 (that is, a control signal indicating discarding). Therefore, when reading of the fifth frame data is completed, the read buffer controller 240 approaches the first buffer 225 and starts reading the sixth frame data. The state of the corresponding buffer is illustrated at 670 of FIG. 6.

Referring to 590 of FIG. 5, the image sensor 210 outputs eighth frame data in response to a preset synchronization signal. After a predetermined delay time, the write buffer controller 220 receives the eighth frame data and writes it to the second buffer 230. The state of the buffer after the writing of the eighth frame data by the write buffer controller 220 is completed is illustrated in 680 of FIG. 6.

As described above, the present invention provides an effective dual frame buffer control apparatus and a method thereof, which can display the latest image data without discarding it.

In addition, the present invention has an effect that can provide (display) the image data near the real-time to minimize the phenomenon in the real-time processing surface.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (8)

Optionally a first buffer and a second buffer in which previous frame data is recorded; A write buffer controller for generating a buffer status check signal when frame data is input; A read buffer controller that reads the previous frame data recorded in either the first buffer or the second buffer; And When the buffer status check signal is input, the remaining read time of the previous frame data to be read is calculated and compared with the estimated recording time to select a buffer to record the frame data when the remaining read time is larger than the estimated recording time. Including a frame controller, And the write buffer controller writes the frame data to the selected buffer. The method of claim 1, The frame controller A check time indicating unit for indicating calculation of remaining read time of the frame data when the buffer state check signal is input; An RRT calculator configured to calculate a remaining frame read time of the previous frame data being read by the second controller according to the read time calculation instruction signal; An FWT register storing a recording time of the frame data; A comparator for generating a recordable indication signal by comparing the calculated remaining frame read time with the write time; And And a write buffer selector configured to select a recordable buffer among the first buffer and the second buffer according to the recordable instruction signal and to transmit a write instruction signal to the write buffer controller. . The method of claim 2, And the RRT calculator calculates the remaining frame read time using the total size of the previous frame data and the size of the read data. The method of claim 2, And the comparing unit generates the recordable indication signal and transmits the writeable indication signal to the recording buffer selection unit when the calculated remaining frame read time is greater than the recording time. The method of claim 4, wherein The comparison unit generates a discard instruction signal when the write time is greater than the calculated remaining frame read time and transfers the discard instruction signal to the write buffer selector. And the write buffer selector instructs the write buffer controller to discard the frame data when the discard instruction signal is input. The method of claim 1, And the first buffer or the second buffer includes a status register, respectively. The method of claim 6, The write buffer controller and the read buffer controller update the status register of the buffer being accessed to the first state, and update to the second state when the access ends. The buffer in which the status register is in the first state is not accessible except the controller being accessed. And the buffer is one of the first buffer and the second buffer. In the method of controlling the dual frame buffer so that the dual frame control device can record the latest frame data output through the image sensor, Receiving a buffer status check signal corresponding to the frame data input from the write buffer controller through the image sensor; Calculating a remaining read time of previous frame data being read by a read buffer controller corresponding to the buffer status check signal; Comparing the remaining read time with a preset recording expected time; Selecting a buffer to record the frame data when the remaining read time is greater than the estimated recording time; And And the write buffer controller writes the frame data to the selected buffer.

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