KR100848554B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display for reducing the difference in brightness of the screen caused by the delay of the gate signal as the distance from the gate line input gate is input, the width toward the farther from the starting point gate signal input M × n defined by the gate line GL in the mth row, the data line DL in the nth column, and the gate line GL and the data line DL in which the thickness is increased, and arranged in a matrix form. Pixels and a thin film transistor formed at the intersection of the gate line GL and the data line DL.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY}

1 is a plan view showing a conventional liquid crystal display device.

2 is a diagram showing a gate signal delay caused by a gate line resistance in a conventional liquid crystal display device.

FIG. 3 is a diagram illustrating a difference in brightness of a screen due to a gate signal delay shown in FIG. 2.

4 is a plan view showing a storage on-gate liquid crystal display device according to the present invention.

5 is a diagram illustrating a relative time relationship between a gate voltage supplied to a gate electrode, a signal voltage applied to a source electrode of a thin film transistor, and a pixel voltage.

*** Explanation of symbols for main parts of drawing ***

12: gate line 14: data line

12a: gate electrode 14a: source electrode

14b: drain electrode 15: semiconductor layer

18: contact hole 20: thin film transistor

21: gate pad 22: data pad

41: signal voltage 42: pixel voltage                 

43: gate voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display for preventing a gate signal delay generated in a gate line due to a resistance of a gate line.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In fact, as shown in FIG. 1, the liquid crystal display includes a liquid crystal panel 2 having gate lines GL1 through GLm and data lines DL1 through DLn intersected with each other. Therefore, the liquid crystal panel has a plurality of gate lines GL1 to GLm, data lines DL1 to DLn, and liquid crystal cells provided in regions where the lines cross each other.
The liquid crystal panel includes pixel electrodes for applying an electric field to each of the liquid crystal cells and a reference electrode, that is, a common electrode. Here, the pixel electrode is formed for each liquid crystal cell on the lower substrate, while the common electrode is integrally formed on the entire surface of the upper substrate. Each of the pixel electrodes is connected to any one of the data lines DL1 to DLn via source and drain terminals of a thin film transistor (hereinafter, referred to as TFT). The gate terminal of each of the TFTs is connected to one of the gate lines 12 GL1 to GLm for causing the pixel voltage signal to be applied to the pixel electrodes for one line. In addition, the liquid crystal display of FIG. 1 includes a gate driver 4 connected to gate lines GL1 to GLm, a data driver 6 connected to data lines DL1 to DLn, and a common electrode. The common voltage generator 8 is provided. The gate driver 4 sequentially supplies scanning signals, that is, gate signals to the gate lines GL1 to GLm, to sequentially drive pixels on the liquid crystal panel 2 by one line. The data driver 6 supplies a data voltage signal to each of the data lines 14 DL1 to DLn whenever the gate signal is supplied to any one of the gate lines GL1 to GLm. The common voltage generator 8 supplies a common voltage signal to the common electrode. Such a liquid crystal display device displays an image by adjusting light transmittance by an electric field applied between a pixel electrode and a common electrode according to a data voltage signal for each liquid crystal cell.

In the liquid crystal panel, when the gate signal is turned off and the voltage applied to the gate terminal of the thin film transistor drops, the data voltage (common electrode voltage reference) supplied to the data line 14 (DL to DLn) and the liquid crystal cell are charged. The feed-through voltage (ΔVp) corresponding to the difference voltage with the liquid crystal cell voltage is generated.
The feed-through voltage ΔVp is generated by the parasitic capacitance Cgs existing in the structure of the thin film transistor between the gate terminal of the TFT and the liquid crystal cell electrode. The liquid crystal is caused by signal delay due to the resistance of the gate line and the data line. Even when the data voltages having the same magnitude are supplied to the cells, the magnitude of the feed-through voltage ΔVp generated varies depending on the positions of the liquid crystal cells. In detail, the pixels on the liquid crystal panel have the equivalent circuit as shown in FIG. 2. In FIG. 2, a pixel includes a TFT connected between a gate line GL, a data line DL, and a common electrode CL, and a liquid crystal cell Clc connected between a source terminal of the TFT and the common electrode CL. Will be. The liquid crystal cell Clc has a difference between a data voltage on the data line DL and a reference voltage on the common electrode CL during a period from T0 to Toff where the TFT is turned on by the gate signal on the gate line GL. It will charge the voltage. However, the gate signal applied to the gate terminal of the TFT causes a gate signal delay due to the resistance of the gate line GL. That is, as shown in the drawing, when the pixel is close to the start point of the gate line GL, there is almost no delay of the gate signal, whereas when the pixel is far from the start point of the gate line GL, the gate signal is transmitted. Since the length of the line becomes longer, the influence of the wiring resistance of the gate line is increased, which increases the delay of the gate signal. In addition, the delay of the signal may be caused by factors such as intrinsic capacitance of the gate line and parasitic capacitance of the gate terminal of the thin film transistor.
As described above, if the delay amount of the gate signal increases as the position of the pixels increases from the start point of the gate line GL due to the resistance of the gate line 12, the position of the pixels is from the start point of the gate line GL. As the distance increases, the feed through voltage ΔVp increases as the position of the pixel moves away from the start point of the gate line GL. In other words, the feed-through voltage ΔVp becomes larger as the delay time of the gate signal becomes longer.

As such, the feed-through voltage ΔVp is the light transmittance of the liquid crystal cells due to the feed-through voltage ΔVp that varies in size depending on the position of the liquid crystal cells because the wiring resistance of the gate line GL depends on the position of the liquid crystal cells. As shown in FIG. 3, a difference in brightness of the screen occurs between pixels near the start point of the gate line GL and pixels far from the start point of the gate line GL.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to increase the width of the gate line 12 as the distance from the start point of the gate line 12 into which the gate signal is input increases the width of the gate line ( 12) to reduce the wiring resistance and to increase the area of the storage electrode overlapping the gate line to form the storage capacitor, thereby providing an improved liquid crystal display device.

Other objects and features of the present invention will be described in detail in the configuration and claims of the following invention.

The liquid crystal display device of the present invention for achieving the above object is to isolate the gate line of the m-th row, the data line of the nth column formed to intersect the gate line of the m-th row, the insulation of the gate line and the data line A gate insulating film and m x n pixels defined by the gate line and the data line and arranged in a matrix form, wherein the gate line is configured such that the line width increases as the gate signal is moved away from a portion to which a gate signal is applied. .
In addition, the pixel has a thin film transistor, the thin film transistor includes a panel-like semiconductor layer, a gate electrode drawn out of the gate line, a source electrode drawn out of the data line, and a drain electrode connected to the pixel electrode formed in the pixel. The source electrode and the drain electrode are opposed to each other so as to overlap the semiconductor layer with a predetermined portion, and the gate voltage is charged while the gate signal is applied to the gate electrode of the thin film transistor. The electronic device further includes a storage capacitor that discharges the charged voltage while the data voltage is supplied to the pixel electrode during the gate line driving, thereby preventing the voltage variation of the pixel electrode.

The storage capacitor is formed by a gate line having a wider width and a region overlapping a pixel electrode formed in the pixel and a passivation layer between the gate capacitor and the gate capacitor.

The width of the storage electrode is formed in proportion to the width of the gate line.

Hereinafter, the liquid crystal display of the present invention as described above will be described in detail with reference to the accompanying drawings.

4 illustrates a storage on gate liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in the figure, the gate line 12 of the m-th row and the data line 14 of the n-th column are formed to be thicker as the distance from the start point at which the gate signal is input on the glass substrate 11 increases. It is orthogonal and consists of the pixel defined by the said gate line 12 and the data line 14, and the pixel electrode 17 formed in the said pixel. In addition, the pixel electrode 17 overlapping the gate line 12, that is, the storage electrode formed to extend to the gate line 12 and the pixel electrode 17 may overlap each other to form a storage capacitor Cst. As the width of 12 increases, the capacity of the storage capacitor Cst also increases.

Although not shown, a gate insulating film is interposed between the gate line 12 and the data line 14 for the purpose of electrical insulation therebetween.

A gate pad 21 is formed at one end side of the gate line 12, and a data pad 22 is formed at one end side of the data line 14.

The gate pad 21 supplies a gate signal supplied from a gate driver integrated circuit (not shown) to the gate lines 12, and the data pad 22 supplies image information supplied from a data driver integrated circuit (not shown). Is supplied to the data line 14.

Near the intersection of the gate line 12 and the data line 14, a thin film transistor 20 for independently controlling the driving of each pixel is formed, where the thin film transistor 20 is a part of the gate line 12. A gate electrode 12a, a gate insulating film (not shown) covering the gate electrode 12a, a semiconductor layer 15 formed in the form of a pattern on the gate insulating film, and a predetermined interval on the semiconductor layer 15 Source / drain electrodes 14a and 14b spaced apart from each other. The drain electrode 14b is electrically connected to the pixel electrode 17 through a contact hole 18.

In addition, the gate line 12 is formed such that its line width increases as the gate signal from the gate pad 21 moves away from the start point input to the gate line 12, and the gate line 12 moves away from the start point through which the gate signal is input. Reduce the resistance increase of 12.

In addition, the width of the gate line 12 is increased to the opposite side where the gate electrode 12a of the thin film transistor 20 is formed.

In the related art, as described with reference to FIGS. 2 to 3, in a liquid crystal display device having a constant width of the gate line, as the length of the gate line becomes longer, the distance from the start point at which the gate signal is input due to an increase in resistance of the gate line As a result, the feed-through voltage ΔVp increases due to an increase in the gate signal delay, causing a difference in brightness of the screen.

Therefore, in order to reduce the appearance of the brightness differently according to the position of the pixel due to the gate signal delay, the present invention forms the width of the gate line closer to the gate pad from the starting point to which the gate signal is applied. It is reduced.

In addition, as the line width of the gate line 12 increases as the distance from the gate pad 21 increases, the protective layer between the gate line 12 and the pixel electrode 17 is formed by increasing the area overlapping with the storage electrode. There is an advantage that the capacity of the storage capacitor (Cst) generated in between can be increased toward the end of the gate line 12.

Accordingly, the present invention increases the capacitance of the storage capacitor Cst with a decrease in the gate signal delay that increases as the distance from the start point of the gate line from which the gate signal is input from the gate pad increases, thereby increasing the feed-through voltage ΔVp. The problem of increasing away from the pad can be solved.

Hereinafter, the reduction in the brightness difference by increasing the capacity of the storage capacitor Cst as the distance from the start point of the gate signal of the present invention will be described in detail.

FIG. 5 shows a relative time relationship between the gate voltage 43 supplied to the gate electrode of the thin film transistor via the gate line, the signal voltage 41 and the pixel voltage 42 applied to the source electrode of the thin film transistor.

As shown in the figure, when the gate voltage 43 of the thin film transistor is turned on by the gate signal of the selected gate line, the signal voltage 41 is supplied to the pixel electrode via the thin film transistor. On the other hand, when the gate voltage 43 is changed from the high state to the low state, the parasitic capacitance Cgs generated in the region overlapping between the gate / source electrode 14a due to the structure of the thin film transistor, The pixel voltage 42 changes due to the parasitic capacitance Cgd generated in the region overlapping between the gate / drain electrodes 14b. In this case, the change ΔVp of the pixel voltage is referred to as a feed through voltage and may be represented by Equation 1 below.

ΔVp = Cgd / (Cgs + Cgd + Cst + Clc) ΔVg

)(

)

는 게이트 전압이다.Here, Clc is a liquid crystal capacitance generated between the pixel electrode and the common electrode with the liquid crystal layer interposed therebetween,

Is the gate voltage.

The feed-through voltage ΔVp increases as the distance from the start point at which the gate signal is input due to the wiring resistance of the gate line 12 increases, and as the distance from the gate pad decreases, the brightness of the screen decreases. The gate line is formed by increasing the line width of the gate line as the distance from the start point of the gate line from which the gate signal is input from the pad increases the capacitance of the storage capacitor Cst generated by the gate insulating film between the gate line and the storage electrode. It is possible to prevent the feed-through voltage DELTA Vp from increasing as it moves toward the starting point of.

As shown in FIG. 4, since the storage capacitor Cst is formed by the overlapping region of the gate line and the storage electrode with the gate insulating layer interposed therebetween, when the width of the gate line is increased, the overlapping region of the storage capacitor Cst is increased. The capacity of the storage capacitor Cst may be increased.

As described above, in the liquid crystal display of the present invention, the width of the gate line becomes thicker as it moves away from the start point of the gate line from which the gate signal is input from the gate pad, thereby reducing the resistance of the gate line and increasing the capacitance of the storage capacitor Cst. By preventing the feed-through voltage ΔVp from increasing toward the end of the gate line, the brightness difference according to the position of the pixel may be reduced.

Claims (7)

A gate line of the mth row; A data line of an nth column formed to intersect the gate line of the mth row; A gate insulating film formed between the gate line and the data line; And Including m × n pixels defined by the gate line and the data line and arranged in a matrix form, The gate line is configured to increase the line width as the distance from the gate signal is applied, and to increase the area of the storage electrode overlapping the gate line with the gate insulating layer therebetween. device. The liquid crystal display of claim 1, wherein the gate line is connected to a gate pad for inputting a gate signal to the gate line at one end of the gate line to receive the gate signal from a gate driver integrated circuit. The liquid crystal display device of claim 1, wherein the one end of the data line is connected to a data pad for inputting a data signal to the data line to receive a data signal from a data driver integrated circuit. The pixel of claim 1, wherein the pixel has a thin film transistor, the thin film transistor includes a semiconductor layer, a gate electrode electrically connected to the gate line, a source electrode electrically connected to the data line, and a pixel formed in the pixel. And a drain electrode connected to the electrode, wherein the source electrode and the drain electrode are provided to face each other with respect to the gate electrode. 5. The liquid crystal display device according to claim 1 or 4, wherein the gate line increases in width on the opposite side to which the gate electrode is formed. The liquid crystal display of claim 1, wherein a storage capacitor is formed by a storage electrode formed by overlapping the gate line with a gate insulating layer therebetween. 7. The liquid crystal display of claim 6, wherein the width of the storage electrode increases in proportion to the width of the gate line.

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