KR100847839B1 - Capacitor of Semiconductor Device and Manufacturing Method Thereof - Google Patents

Abstract

The present invention comprises the steps of forming a barrier layer on the upper surface of the semiconductor substrate to form a metal film having a predetermined thickness; After forming a photoresist pattern in the form of a line by patterning the upper surface of the metal film, an etching process using the photoresist pattern as an etching mask is performed to etch the metal film in the form of a line to form a line having a predetermined height and width. Forming a first metal film pattern and a second metal film pattern; Removing the line type photoresist pattern and depositing a first dielectric layer on the semiconductor substrate including the first metal layer pattern and the second metal layer pattern to a predetermined thickness; After planarizing the first metal layer pattern and the second metal layer pattern, forming a first electrode metal layer and a second electrode metal layer contacting the first metal layer pattern and the second metal layer pattern, respectively. A method for forming a capacitor of a semiconductor device.

Capacitors, MIM

Description

Capacitor of Semiconductor Device and Method of Forming It {Capacitor of Semiconductor Device and Manufacturing Method Thereof}

1A to 1D are cross-sectional views illustrating a method of forming a MIM capacitor of a semiconductor device according to the prior art;

2A to 2E are cross-sectional views illustrating a method of forming a MIM capacitor of a semiconductor device according to the present invention.

**** Drawing Description Code ***

200: semiconductor substrate 202: barrier layer

204a: first metal film pattern 204b: second metal film pattern

208a, 208b, and 208c: first dielectric film 210a: first electrode metal layer

210b: second electrode metal layer

The present invention relates to a capacitor of a semiconductor device and a method of forming the same, and more particularly, to a capacitor of a semiconductor device and a method of forming the same that can reduce the process of forming a MIM capacitor of the semiconductor device.

1A to 1D are cross-sectional views illustrating a method of forming a MIM capacitor of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, in a state in which a predetermined base layer 10 is formed on the semiconductor substrate 1, the first metal film 11 and the dielectric film 12 on the base layer 10. And a second metal film 13 are formed in this order.

Next, as shown in FIG. 1B, the first photoresist layer pattern 14 is formed on the second metal layer 13 by a known photolithography process, and then the first photoresist layer pattern 14 is etched. The capacitor upper electrode 13a is formed by etching the second metal film 13 and the dielectric film 12 using a mask.

Next, in a state in which the first photoresist pattern is removed, as shown in FIG. 1C, a second photoresist pattern 15 for forming a capacitor lower electrode is formed on the resultant again through a photolithography process, and then, The exposed first metal film portion is etched to form the capacitor lower electrode 11a, thereby completing the MIM capacitor. Unexplained reference numeral 11b denotes a circuit wiring in the logic region.

Thereafter, as shown in FIG. 1D, in a state in which the interlayer insulating film 16 is formed on the resultant, predetermined portions of the interlayer insulating film 16 are selectively etched to circuit the capacitor lower and upper electrodes 11a and 13a. Contact holes exposing the wiring 11b, respectively, are formed, and then a conductive film is embedded in each of the contact holes, so that the plug 17 contacts the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. To form. Then, a metal film is deposited on the interlayer insulating film 16, and then patterned, and the metal electrode is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a by the plug 17, respectively. Form the field 18.

However, in the semiconductor device of the prior art, there are many MIM capacitor forming processes of the semiconductor device, and thus the yield of the semiconductor device is lowered.

The present invention has been proposed to solve the problems of the prior art as described above, and an object of the present invention is to provide a method of forming a MIM capacitor of a semiconductor device to reduce the process of forming a MIM capacitor of the semiconductor device.

Features of the present invention for achieving the above object is the step of forming a barrier layer on the upper surface of the semiconductor substrate to form a metal film having a predetermined thickness; After forming a photoresist pattern in the form of a line by patterning the upper surface of the metal film, an etching process using the photoresist pattern as an etching mask is performed to etch the metal film in the form of a line to form a line having a predetermined height and width. Forming a first metal film pattern and a second metal film pattern; Removing the line type photoresist pattern and depositing a first dielectric layer on the semiconductor substrate including the first metal layer pattern and the second metal layer pattern to a predetermined thickness; Forming a first electrode metal layer and a second electrode metal layer contacting the first metal layer pattern and the second metal layer pattern, respectively, after planarizing the first metal layer pattern and the second metal layer pattern A method for forming a capacitor of a semiconductor device.

And depositing the first dielectric layer and selectively etching the first dielectric layer between the first metal layer pattern and the second metal layer pattern and then filling the second dielectric layer to form the second dielectric layer. do.

In the present invention, the first dielectric film is deposited as an inter metal dielectric (IMD) film or a pre metal dielectric (PMD) film.

In the present invention, the second dielectric layer is formed of TiO.₂ Membrane, HfO₂ Membrane, ZrO₂, SrTiO₃ Membrane, ((Bi, (e)₄Ti₃O₁₂One of the films is filled.

The method may further include planarizing the first metal layer pattern and the second metal layer pattern after forming a second dielectric layer between the first metal layer pattern and the second metal layer pattern. .

In still another aspect of the present invention, there is provided a semiconductor device comprising: a first metal film pattern and a second metal film pattern in a line shape having a predetermined height and width on an upper surface of a barrier layer on a semiconductor substrate; A first dielectric layer formed on the semiconductor substrate including the first metal layer pattern and the second metal layer pattern; The present invention relates to a capacitor of a semiconductor device including a first electrode metal layer and a second electrode metal layer contacting the first metal film pattern and the second metal film pattern, respectively.

The method may further include a second dielectric layer formed between the first metal layer pattern and the second metal layer pattern.

In the present invention, the first metal film pattern and the second metal film pattern are formed in a line shape having a height greater than a width.

In the present invention, the barrier layer is characterized in that formed of a SiN layer or SiO ₂ layer.

In the present invention, the first dielectric film is formed of an intermetal dielectric (IMD) film or a pre metal dielectric (PMD) film.

In the present invention, the second dielectric film is formed of one of a TiO ₂ film, an HfO ₂ film, a ZrO ₂ , an SrTiO ₃ film, and a ((Bi, (e) ₄ Ti ₃ O ₁₂ ) film.

Hereinafter, a method of forming a MIM capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of forming a MIM capacitor of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, a barrier layer 202, for example, an SiN layer or an SiO ₂ layer, is formed on the upper surface of the semiconductor substrate 200 and a predetermined thickness is formed on the upper surface of the barrier layer 202. After forming the metal film 204 having a pattern, a photoresist pattern 206 having a line shape is formed through patterning.

As shown in FIG. 2B, the metal layer 204 is etched to the barrier layer 202 in the form of a line by performing an etching process using the photoresist pattern 206 having a line shape as a mask to have a predetermined width and height. After forming the first metal film pattern and the second metal film pattern in a line shape, as shown in FIG. 2C, an ashing and cleaning process is performed to remove the photoresist pattern 206.

Here, after forming a bent photoresist pattern selectively through patterning, an etching process using the bent photoresist pattern as an etching mask is performed to form a bent first metal film pattern and a second having a predetermined width and height. A metal film pattern can also be formed.

By forming the first metal film pattern 204a and the second metal film pattern 204b in the form of lines (or bends) as described above, the first metal pattern 204a and the second metal pattern 204b are in contact with the dielectric film. The effective area is increased to maximize the capacitance of the capacitor.

Here, the first metal film pattern and the second metal film pattern may be formed in a line shape having a height greater than the width, and the MIM capacitor in the first metal film pattern and the second metal film pattern having a line shape having a height greater than the width. Formation of the semiconductor device can be miniaturized.

The first metal film pattern and the second metal film pattern may be formed to have the same width and height.

Thereafter, an intermetal dielectric (IMD) film or a pre metal dielectric (PMD) film 208 having a predetermined thickness over the semiconductor substrate 200 including the first metal film pattern 204a and the second metal film pattern 204b. After the first dielectric film 208 is stacked, the first metal film pattern 204a and the second metal film pattern 204b in the form of a line (or a curved shape) having a predetermined height and width as shown in FIG. 2D. ) Is planarized through an etch back or chemical mechanical polishing (CMP) process to form a metal insulator-metal (MIM) capacitor.

In addition, after the dielectric film is selectively etched between the first metal film pattern 204a in the form of lines (or bends) and the second metal film pattern 204b in the form of lines (or bends), for increasing the capacitance. For example, a material having a high dielectric constant, for example, TiO ₂ , HfO ₂ , ZrO ₂ , SrTiO ₃ , and the second dielectric film 208b of ((Bi, (e) ₄ Ti ₃ O ₁₂ )) may be replaced with the first metal film pattern 204a. It may be formed by filling between the second metal film patterns 204b.

Subsequently, as illustrated in FIG. 2E, the first electrode metal layer 210b and the second electrode metal layer 210b are formed to contact the first metal film pattern 204a and the second metal film pattern 204b in a line shape, respectively. do.

As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above-described embodiments, and those skilled in the art to which the present invention pertains, various modifications and Modifications are possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

As described above, after forming the metal layer pattern on the semiconductor substrate according to the present invention, by forming an insulating film on the semiconductor substrate including the metal layer pattern to form a MIM capacitor, the process yield can be improved by simplifying the MIM capacitor process It works.

In another exemplary embodiment of the present invention, a semiconductor device may be reduced by forming a MIM capacitor with a first metal film pattern and a second metal film pattern having a height greater than a width in the semiconductor device.

Claims (11)

Forming a barrier layer on an upper surface of the semiconductor substrate and then forming a metal film having a predetermined thickness; After forming a photoresist pattern in the form of a line by patterning the upper surface of the metal film, an etching process using the photoresist pattern as an etching mask is performed to etch the metal film in the form of a line to form a line having a predetermined height and width. Forming a first metal film pattern and a second metal film pattern; Removing the line type photoresist pattern and depositing a first dielectric layer on the semiconductor substrate including the first metal layer pattern and the second metal layer pattern to a predetermined thickness; After depositing the first dielectric layer, selectively etching the first dielectric layer between the first metal layer pattern and the second metal layer pattern and filling the second dielectric layer; And Forming a first electrode metal layer and a second electrode metal layer contacting the first metal film pattern and the second metal film pattern, respectively, after planarizing the first metal film pattern and the second metal film pattern A method of forming a capacitor of a semiconductor device, characterized in that. delete The method of claim 1, The first dielectric film, A method of forming a capacitor of a semiconductor device, characterized in that it is deposited by an intermetal dielectric (IMD) film or a pre metal dielectric (PMD) film. The method of claim 1, The second dielectric layer is, A method of forming a capacitor of a semiconductor device, wherein one of a TiO ₂ film, an HfO ₂ film, a ZrO ₂ , an SrTiO ₃ film, and a ((Bi, (e) ₄ Ti ₃ O ₁₂ ) film is filled. The method of claim 1, And forming a second dielectric film between the first metal film pattern and the second metal film pattern, and then planarizing the first metal film pattern and the second metal film pattern. How to form a capacitor. A first metal film pattern and a second metal film pattern in a line shape having a predetermined height and width on an upper surface of the barrier layer on the semiconductor substrate; A first dielectric layer formed on the semiconductor substrate including the first metal layer pattern and the second metal layer pattern; A second dielectric layer formed between the first metal layer pattern and the second metal layer pattern; And And a first electrode metal layer and a second electrode metal layer contacting the first metal film pattern and the second metal film pattern, respectively. delete The method of claim 6, The first metal film pattern and the second metal film pattern, A capacitor of a semiconductor device, characterized in that formed in the form of a line larger than the width. The method of claim 6, The barrier layer, A capacitor of a semiconductor device, characterized in that formed of a SiN layer or a SiO ₂ layer. The method of claim 6, The first dielectric film, A capacitor of a semiconductor device, characterized in that it is formed of an inter metal dielectric (IMD) film or a pre metal dielectric (PMD) film. The method of claim 6, The second dielectric layer is, A capacitor of a semiconductor device, characterized in that formed of one of a TiO ₂ film, an HfO ₂ film, a ZrO ₂ , an SrTiO ₃ film, and a ((Bi, (e) ₄ Ti ₃ O ₁₂ ) film.

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