KR100845808B1 - Clock mismatch correction circuit and DL circuit including the same - Google Patents

Abstract

The clock mismatch correction circuit of the present invention detects the phase difference between the fed-out output rising clock and the output polling clock and accordingly outputs the internal rising clock and the internal falling clock by delaying one of the input rising clock and the input falling clock for a predetermined time. A mismatch correction unit; And a clock transmitter configured to receive an internal rising clock and an internal falling clock and output an output rising clock and an output falling clock.

Description

Clock Mismatch Correction Circuit And DLL Circuit Including The Same}

1 is a block diagram of a clock mismatch correction circuit according to the present invention;

2 is a timing diagram of the clock mismatch correction circuit shown in FIG. 1;

3 is a timing diagram of a clock mismatch correction circuit shown in FIG. 1;

4 is a timing diagram of a clock mismatch correction circuit shown in FIG. 1;

5 is a block diagram of a DL circuit including the clock mismatch correction circuit shown in FIG. 1;

6 is a block diagram illustrating another embodiment of the clock mismatch correction circuit shown in FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: mismatch correction unit 20: clock transmission unit

30: DL clock generator 40: output driver

50: phase splitting unit 60: mismatch correction unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a clock mismatch correction circuit and a DL circuit using the same.

In general, the DL circuit is used to match the phase of the clock applied from the outside of the semiconductor integrated circuit and the clock used therein.

A typical semiconductor integrated circuit design is designed to control the operation of the duty cycle correction circuit at the input buffer stage by placing an analog duty cycle corrector (DCC) in front of the DL circuit. The problem with such a circuit is that if the external signal is distorted, it will correct it, but it will be difficult to cope with mismatches that may occur in the internal circuit. In addition, there is a disadvantage that the response speed is slow when the external supply power (Power) changes. In semiconductor integrated circuits, such internal mismatches may occur, or if the duty cycle correction circuit responds slowly, read fail may cause serious failures. Therefore, if the power of the system is unstable or the process (Process) is severe, the design response is required to operate stably.

For example, the DC circuit is enabled with an external power of 1.8V, so that the locking state is maintained after the duty cycle correction circuit is operated. At this time, if the external power rises to 2.0V, the duty cycle correction circuit starts operation to meet the duty again. In this case, if a read command is applied from the outside, the duty is output to the DL output as it is, and the output data DQ and data strobe signal DQS are turned off, resulting in read fail. In other words, there is a need for a correction circuit that does not cause a lead fail even when the duty cycle correction circuit is completely corrected.

Disclosure of Invention The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a clock mismatch correction circuit for correcting mismatch between DL clocks by actively coping with power or process variation, and a DL circuit including the same.

The clock mismatch correction circuit of the present invention for achieving the above-described technical problem detects the phase difference between the fed-back output rising clock and the output polling clock and delays one of the input rising clock and the input polling clock accordingly accordingly. A mismatch correction unit for outputting a rising clock and an internal polling clock; And a clock transmitter configured to receive the internal rising clock and the internal falling clock and output an output rising clock and an output falling clock.

The DL circuit including the clock mismatch correction circuit of the present invention includes a DL clock generator configured to receive an external clock and generate a DL clock; A phase splitter for splitting a phase of the DL clock to generate an input polling clock and an input rising clock; A mismatch correction unit for detecting a phase difference between the feedback output rising clock and the output polling clock and delaying one of the input rising clock and the input polling clock for a predetermined time to output an internal rising clock and an internal falling clock; A clock transmitter configured to receive the internal rising clock and the internal falling clock and output the output rising clock and the output falling clock; And an output driver configured to output data in synchronization with the output polling clock and the output rising clock.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram of a clock mismatch correction circuit in accordance with the present invention.

As shown, the clock mismatch correction circuit according to the present invention includes a mismatch correction unit 10, a clock transmission unit 20, and a phase splitting unit 50.

The mismatch correction unit 10 detects a phase difference between the fed-back output rising clock RCLK and the output falling clock FCLK and selects one of the input rising clock IPRCLK and the input falling clock IPFCLK accordingly. It outputs an internal rising clock (IRCLK) and an internal polling clock (IFCLK) with a time delay.

The clock transmitter 20 receives the internal rising clock IRCLK and the internal falling clock IFCLK and outputs the output rising clock RCLK and the output falling clock FCLK. The clock transmitter 20 may be implemented by a general driver circuit.

The mismatch correction unit 10 includes a delay unit 11, a phase detection unit 12, and a delay selection unit 13.

The delay unit 11 delays the output polling clock FCLK for a predetermined time. The delay unit 11 may be composed of first to Nth delay units 11-1 to 11-N (N is a natural number), and one of the nth delay units 11-n (n is A natural number equal to or greater than 1 and equal to or less than N) It can be configured as n times the delay amount of the first delay unit 11-1. The delay unit 11 may be configured such that the amount of delay increases from the first delay unit 11-1 to the Nth delay unit 11-N.

The phase detection unit 12 compares the phase of the output rising clock FCLK with the output of the delay unit 11 and outputs phase detection signals Pcontrol_1 to Pcontrol_N. The phase detection unit 12 is composed of first to Nth phase detection units 12-1 to 12 -N, and one of the nth phase detection units 12-n is the nth delay unit 11. The n-th phase detection signal Pcontrol_N is output by comparing the output of -n) and the phase difference of the output rising clock RCLK.

The delay selection unit 13 varies the amount of delay of the input polling clock IPFCLK according to the phase detection signals Pcontrol_1 to Pcontrol_N. The delay selection unit 13 is composed of first to Nth delay selection units 13-1 to 13-N, and one of the nth delay selection units 13-n includes the nth phase detection signal ( According to Pcontrol_N, the input signal of the nth delay selecting unit 13-n is delayed or immediately output.

The delay selection unit 13 may be configured such that the first to Nth delay selection units 13-1 to 13-N have the same delay amount, and the first to Nth delay selection units 13-1. 13-N) to be connected in sequence. That is, the delay selection unit 13 outputs the output of the first delay selection unit 13-1 dly_CLK1 to the second delay selection unit 13-2, and outputs the second delay selection unit ( Although not shown, the output dly_CLK2 of 12-1) is configured to be an input of the third delay selection unit 13-3. Thus, the output of the Nth delay selection unit 13-N is equal to the internal polling clock IFCLK.

As illustrated in FIG. 1, the n-th delay selecting unit 13-n may be configured as a MOS transistor receiving the n-th phase detection signal Pcontrol_n from a gate and having a source and a drain connected thereto. In this case, all of the delay amounts of the first to Nth delay selection units 13-1 to 13-N can be configured to be the same, and the delay amount of the nth delay selection unit 13-n is equal to It can be comprised so that it may become equal to the delay amount of one delay unit 11-1.

The clock mismatch correction circuit according to the present invention may further include a phase splitting unit 50 that receives a DL clock and outputs the input rising clock IPRCLK and the input polling clock IPFCLK that are inverted in phase with each other. It may further be provided.

The phase splitting unit 50 may include an inverter that receives the DL clock DLL_CLK and inverts it to output the input rising clock IPRCLK; And a passgate configured to receive the DL clock DLL_CLK and output the input polling clock IPFCLK. A passgate PG1 is used to synchronize the input polling clock IPFCLK with the same timing as the input rising clock IPRCLK. The clock mismatch correction circuit according to the present invention has been described, for example, by correcting a mismatch of a DL clock by applying the DL clock DLL_CLK as an input clock, and may be applied to a general clock mismatch correction circuit. have.

The clock mismatch correction circuit may further include an output driver configured to output data in synchronization with the output rising clock RCLK and the output falling clock FCLK.

Referring to the configuration of the mismatch correction unit 10 shown in Figure 1 in more detail as follows.

The first delay unit 11-1 delays the output polling clock FCLK by a first delay time delay_1. The first delay unit 11-1 may be implemented with a general delay circuit. The n th delay unit 11-n, which is one of the second to N th delay units 11-2 to 11 -N, delays the output polling clock FCLK to the n th delay time delay_n. . The nth delay unit 11-n further delays a predetermined time more than the n-1 delay unit 11-n-1. (N is a natural number of 2 or more). The n-th delay unit 11-n has a longer delay time than the n-th delay unit 11-n-1. For example, the delay time of the nth delay unit 11-n may be implemented at n times the delay time of the first delay unit 11-1. The second to Nth delay units 11-2 to 11 -N may be implemented as general delay circuits.

The first phase detection unit 12-1 compares the phase of the output rising clock RCLK and the output of the first delay unit 11-1 to output a first phase detection signal Pcontrol_1. The n-th phase detection unit 12-n outputs an n-th phase detection signal Pcontrol_n by comparing the phase of the output rising clock RCLK and the output of the n-th delay unit 11-n. Alternatively, as shown in FIG. 1, the n-th phase detection unit 12-n compares the phase of the output rising clock RCLK with a signal inverting the output of the n-th delay unit 11-n. (N is more than 1 and natural number less than or equal to N). The first to Nth phase detection units 12-1 to 12 -N may be implemented by general phase detector circuits.

The first delay selecting unit 13-1 delays the input polling clock IPFCLK by the predetermined time according to the first phase detection signal Pcontrol_1 to output the first delay clock dly_CLK_1.

The first delay selecting unit 13-1 delays the input polling clock IPFCLK by the predetermined time as the first phase detection signal Pcontrol_1 is enabled, and the first phase detection signal Pcontrol_1. As is disabled, the output signal is output to the first delayed clock dly_CLK_1 without delaying the input polling clock IPFCLK.

The n-th delay selecting unit 13-n delays the n−1 th delay clock dly_CLK_n−1 by the predetermined time in response to the n th phase detection signal Pcontrol_n, so that the n th delay clock dly_CLK_n )

The nth delay selecting unit 13-n delays the n−1 th delay clock dly_CLK_n−1 by the predetermined time as the nth phase detection signal Pcontrol_n is enabled, and the nth phase As the detection signal Pcontrol_n is disabled, the detection signal Pcontrol_n is output to the nth delay clock dly_CLK_n without delaying the n-1th delay clock dly_CLK_n-1.

The delay times of the first to Nth delay selection units 13-1 to 13 -N may be configured to be the same. The delay time of the first to Nth delay selection units 13-1 to 13 -N is equal to the delay time of the first delay unit 13-1, and the nth delay unit 13 The delay time of -n) may be configured to be n times the delay time of the first delay unit 13-1. The delay time of the nth delay selecting unit 13-n may be equal to the delay time of the nth delay unit 11-n. The nth delay selection unit 13-n may be implemented as a capacitor as shown in FIG. 2. As the nth phase detection signal Pcontrol_n is enabled, the capacitor is driven to have a predetermined delay time characteristic. As the n th phase detection signal Pcontrol_n is disabled, the capacitor shows only the junction capacitance, so that the n−1 th delay clock dly_CLK_n−1 is converted into the n th delay clock dly_CLK_n. Will output without delay.

The number of n is related to the precision of the present invention. The present invention has a large number of n and delay times of each of the first to Nth delay units 11-1 to 11 -N or each of the first to Nth delay selection units 13-1 to 13 -N. The smaller the difference between them, the more accurate the mismatch can be corrected.

Hereinafter, the operation of the clock mismatch circuit shown in FIG. 1 will be described with reference to the timing diagrams of FIGS. 2 to 4.

FIG. 2 is a timing diagram of the clock mismatch correction circuit shown in FIG. 1.

The phase difference between the output polling clock FCLK and the output rising clock RCLK is 180 degrees, and there is no mismatch. In this case, the first to Nth delay units 11-1 to 11 -N output signals in which the output polling clock FCLK is delayed for a predetermined time. The first to Nth phase detection units 12-1 to 12 -N invert the signal delayed by the output polling clock FCLK in the first to Nth delay units 11-1 to 11 -N. The phase of the signal and the output rising clock RCLK are compared. Since the delayed signal of the output polling clock FCLK is a delayed signal compared to the output rising clock RCLK, the first to Nth phase detection signals Pcontrol_1 to Pcontrol_N are disabled. Accordingly, the mismatch correction unit 10 receives the first to Nth phase detection signals Pcontrol_1 to Pcontrol_N and outputs the internal polling clock IPFCLK without delaying the input polling clock IPFCLK. do. Since there is no mismatch between the output polling clock FCLK and the output rising clock RCLK, since no further correction is required, the output polling clock IFCLK is output directly without delaying the input polling clock IPFCLK. .

3 is a timing diagram of the clock mismatch correction circuit shown in FIG. 1.

The output polling clock FCLK is out of phase with the output rising clock RCLK. The first phase detection signal Pcontrol, which compares a phase of the output falling clock FCLK with the first delay time delay and the output rising clock RCLK, is enabled, and the other second to Nth The phase detection signals Pcontrol_2 to Pcontrol_N are disabled. Accordingly, when the first phase detection signal Pcontrol_1 is input, the first delay selection unit 13-1 delays the input polling clock IPFCLK for a predetermined time and other second to nth delay selection units. 13-2 to 13-n output the received signals without delay. Therefore, the internal polling clock IPFCLK is a signal delayed by the delay in the first delay selection unit 13-1. That is, according to the present invention, since the mismatched degree of the phase of the output rising clock RCLK and the output polling clock FCLK is a delay amount of the first delay unit 11-1, the input polling clock IPFCLK ) Is delayed by the delay amount of the first delay unit 11-1 (or equal to the delay amount of the first delay selection unit 13-1) to thereby output the clock rising clock RCLK and the output polling clock. The mismatch of (FCLK) is corrected.

4 is a timing diagram of the clock mismatch correction circuit shown in FIG. 1.

The phase difference between the output polling clock FCLK and the output rising clock RCLK is greater than that shown in FIG. 3. The first phase detection signal Pcontrol_1 and the second phase detection signal Pcontrol_2 are enabled, and the other third phase detection signals Pcontrol_3 to N-th phase detection signal Pcontrol_N are disabled. Therefore, the internal polling clock IPFCLK is a signal delayed by the delay in the first delay selection unit 13-1 and the second delay selection unit 13-2.

In the same principle as in FIG. 3, the present invention provides that the mismatched phases of the output rising clock RCLK and the output polling clock FCLK are equal to each other in the first delay unit 11-1 and the second delay unit ( 11-2), the input polling clock IPFCLK is selected as the delay amount of the second delay unit 11-2 (or the first delay selection unit 13-1 and the second delay selection). By delaying the unit 13-2 by the sum of the delay amounts, the mismatch between the output rising clock RCLK and the output polling clock FCLK is corrected.

Accordingly, the present invention corrects the delay of the phase in consideration of the mismatch between the output rising clock RCLK and the output polling clock FCLK at the final output stage. The output rising clock RCLK and the output polling clock FCLK at the final output stage are fed back by feeding back a mismatch between the output rising clock RCLK and the output falling clock FCLK due to the cause. The mismatch of can be corrected.

FIG. 5 is a block diagram of a DL circuit including the clock mismatch correction circuit of FIG. 1.

The DL circuit illustrated in FIG. 5 includes a DL clock generator 30, a phase splitter 50, a mismatch corrector 10, a clock transmitter 20, and an output driver 40.

The DL clock generator 30 receives an external clock EXT_CLK and generates a DL clock DLLCLK.

The DL clock generator 30 includes a buffer 31, a DL delay line 32, a compensation delay line 33, a phase detector 34, and a low pass filter 35.

The buffer 31 receives and buffers an external clock EXT_CLK, and the DL delay line 32 delays the output of the buffer 31 by a predetermined time. The phase detector 34 compares the phase of the output of the compensation delay line 33 with the output of the buffer 31. The low pass filter 35 receives the output of the phase detector 34 and feeds it back to the DL delay line 32.

The phase splitter 50 splits the phase of the DL clock to generate an input polling clock IPFCLK and an input rising clock IPRCLK. The input polling clock IPFCLK and the input rising clock IPRCLK are signals having a phase difference of 180 degrees.

The mismatch correction unit 10 and the clock transmission unit 20 are as shown in FIG. 1.

The output driver 40 outputs data in synchronization with the output polling clock FCLK and the output rising clock RCLK. The data may be, for example, data contained in a cell in a semiconductor integrated circuit.

FIG. 6 is a detailed circuit diagram illustrating another embodiment of the clock mismatch correction circuit shown in FIG. 1.

The clock mismatch correction circuit illustrated in FIG. 6 includes a phase splitting unit 50, a mismatch correcting unit 60, and a clock transmission unit 20.

The mismatch correction unit 60 includes a first delay unit 11-1, a first phase detection unit 12-1, and a delay selection unit 14.

The delay selection unit 14 includes an inverter for inverting the input rising clock IPRCLK; A plurality of inverters for delaying the input polling clock IPFCLK; And a selection unit 14-1 selectively outputting the input polling clock IPFCLK and outputs of the plurality of inverters.

The input rising / falling clocks IPRCLK and IPFCLK may be DL clocks, and when two general clocks are supplied in pairs, the input rising / falling clocks IPRCLK and IPFCLK may be applied to correct mismatches of phases of the two clocks. .

The present invention can be applied to a dual loop DLL circuit and can also be applied to design-for-manufacturing (DFM).

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The clock mismatch correction circuit and the DL circuit using the same according to the present invention have an effect of correcting a mismatch between DL clocks that can actively cope with a change in power or a process.

Claims (24)

A mismatch correction unit for detecting a phase difference between the feedback output rising clock and the output polling clock and delaying one of the input rising clock and the input polling clock for a predetermined time to output an internal rising clock and an internal falling clock; And And a clock transmitter configured to receive the internal rising clock and the internal falling clock and output an output rising clock and an output falling clock. The method of claim 1, The mismatch correction unit, A delay unit for delaying the output polling clock for a predetermined time; A phase detection unit for comparing a phase of the output rising clock and the output of the delay unit to output a phase detection signal; And And a delay selection unit for varying a degree of delay of the input polling clock according to the phase detection signal. The method of claim 2, The delay unit, Consisting of first to Nth delay units (N is a natural number), The nth delay unit, which is one of them (n is a natural number equal to or greater than 1 and equal to or less than N), is configured as n times the delay amount of the first delay unit. The method of claim 3, wherein The phase detection unit, The first to Nth phase detection units, One of the nth phase detection units, And a phase difference between the output of the nth delay unit and the output rising clock to output an nth phase detection signal. The method of claim 4, wherein The delay selection unit, Consisting of first to Nth delay selection units, One of them, the nth delay selection unit, And a unit delay selection line configured to vary the degree of delaying the input polling clock according to the plurality of phase detection signals. The method of claim 5, wherein And the first to Nth delay selection units have the same delay amount, and the first to Nth delay selection units are sequentially connected. The method of claim 6, The nth delay selection unit, And a MOS transistor configured to receive the nth phase detection signal at a gate and have a source and a drain connected thereto. The method of claim 5, wherein The delay selection unit, An inverter for inverting the input rising clock; A plurality of inverters for delaying the input polling clock; And And a selection unit for selectively outputting the input polling clock and the outputs of the plurality of inverters. The method of claim 5, wherein And the delay amounts of the first to Nth delay selection units are the same. The method of claim 9, And the delay amount of the nth delay selection unit is equal to the delay amount of the first delay unit. The method of claim 1, And a phase splitting unit configured to receive a DL clock and output the input rising clock and the input polling clock which are inverted in phase with each other. The method of claim 11, The phase splitting unit, An inverter configured to receive the DL clock and invert the output signal to output the input rising clock; And And a passgate configured to receive the DL clock and output the input polling clock. The method of claim 1, And an output driver configured to output data in synchronization with the output rising clock and the output falling clock. A DL clock generator configured to receive an external clock and generate a DL clock; A phase splitter for splitting a phase of the DL clock to generate an input polling clock and an input rising clock; A mismatch correction unit for detecting a phase difference between the feedback output rising clock and the output polling clock and delaying one of the input rising clock and the input polling clock for a predetermined time to output an internal rising clock and an internal falling clock; And A clock transmitter configured to receive the internal rising clock and the internal falling clock and output the output rising clock and the output falling clock; And And a output driver configured to output data in synchronization with the output polling clock and the output rising clock. The method of claim 14, The DL clock generator, A buffer which receives and buffers an external clock; A DL delay line for delaying the output of the buffer to generate a DL clock; A compensation delay unit delaying an output of the DL delay line; A phase detector for comparing a phase of an output of the compensation delay unit and an output of the buffer; And And a low pass filter receiving the output of the phase detector and feeding back the DL delay line. The method of claim 14, The mismatch correction unit, A delay unit for delaying the output polling clock for a predetermined time; A phase detection unit for comparing a phase of the output rising clock and the output of the delay unit to output a phase detection signal; And And a delay selection unit for varying a degree of delay of the input polling clock according to the phase detection signal. The method of claim 16, The delay unit, Consisting of first to Nth delay units (N is a natural number), One of the nth delay units (n is a natural number equal to or greater than 1 and equal to or less than N) is a DL circuit comprising n times the delay amount of the first delay unit. The method of claim 17, The phase detection unit, The first to Nth phase detection units, One of the nth phase detection units, And a phase difference between the output of the nth delay unit and the output rising clock to output an nth phase detection signal. The method of claim 18, The delay selection unit, Consisting of first to Nth delay selection units, One of them is the nth delay selection unit And a plurality of unit delay selection lines configured to vary the degree of delaying the input polling clock according to the plurality of phase detection signals. The method of claim 19, And the first to Nth delay selection units have the same delay amount, and the first to Nth delay selection units are sequentially connected. The method of claim 20, The nth delay selection unit, And a MOS transistor receiving the nth phase detection signal from a gate and having a source and a drain connected thereto. The method of claim 19, The delay selection unit, An inverter for inverting the input rising clock; A plurality of inverters for delaying the input polling clock; And And a selection unit for selectively outputting the input polling clock and the outputs of the plurality of inverters. The method of claim 19, The delay amount of the nth delay selection unit is equal to the delay amount of the first delay unit. The method of claim 14, The phase splitting unit, An inverter configured to receive the DL clock and invert the output signal to output the input rising clock; And And a pass gate configured to receive the DL clock and output the input polling clock.

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