KR100835973B1 - Array board for transverse electric field type liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to a configuration of a transverse electric field type liquid crystal display device array substrate and a manufacturing method thereof.

In summary, during the process of patterning the pixel electrode of the array substrate, residues of the source-drain metal layer extending from the data line occur along the lateral step of the common electrode close to the data line. Is removed during the process of patterning the protective film.

In this manner, it is possible to prevent the occurrence of leakage current due to the residue of the source-drain metal layer.

Description

An array substrate for in-plane switching mode LCD and the method for fabricating the same             

1 is a plan view schematically showing one pixel of a conventional array substrate for a transverse electric field type liquid crystal display device;

2A to 2C are cross-sectional views taken along the line II-II` and III-III` of FIG. 1 and shown in a conventional process sequence.

3 is a plan view schematically showing one pixel of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

4A through 4D are cross-sectional views taken along the line IV-`IV and V-V` of FIG. 3 and in accordance with the process sequence of the present invention.

<Description of the symbols for the main parts of the drawings>

100: substrate 112: gate wiring

114: gate electrode 117: common electrode

120: active layer 124: data wiring

126 source electrode 128 drain electrode                 

130: pixel electrode 134: etching hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to an array substrate for an in-plane switching mode liquid crystal display device for preventing leakage current occurring in a pixel region, and a method of manufacturing the same.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have attracted the most attention due to their excellent resolution and video performance.

Hereinafter, a conventional array substrate for a transverse electric field type liquid crystal display device and a manufacturing method thereof will be described with reference to the drawings.                         

1 is a plan view schematically illustrating a part of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the drawing, a conventional array substrate 10 for a transverse electric field type liquid crystal display device has a plurality of gate wirings 12 and storage wirings 16 arranged in one direction in parallel with a predetermined interval therebetween, and intersect with the two wirings. In particular, the data line 24 defining the pixel area P is formed from the gate line 12.

At the intersection of the gate wiring 12 and the data wiring 24, the gate electrode 14 which is a part of the gate wiring 12, the active layer 20 and the source electrode formed on the gate electrode 14 are formed. And a thin film transistor T including a drain electrode 28 and a drain electrode 28. The source electrode 26 is connected to the data line 24, and the gate electrode 14 is connected to the gate line 12. ).

The pixel electrode 30 connected to the drain electrode 28 and the common electrode 17 connected in parallel with the pixel electrode 30 and connected to the storage wiring 16 are disposed on the pixel area P. This is made up.

The pixel electrode 30 includes an extension part 30a extending from the drain electrode 28, a plurality of vertical parts 30b vertically extending from the extension part 30a and spaced apart from each other by a predetermined distance, and the storage wiring line. The upper portion of the 16 is composed of a horizontal portion (30c) for connecting the vertical portion (30b) into one.

The common electrode 17 extends vertically from the storage wiring 16 to the pixel region P, and is arranged with a plurality of vertical portions 17b intersecting with the vertical portions 30b of the pixel electrodes, respectively. It consists of the horizontal part 17a which connects the part 17b to one.

The vertical portion 17b of the common electrode 17 of the pixel area P is configured to be spaced apart from the data line 24 by a predetermined distance, and part of the common electrode 17 is adjacent to the data line 24.

In addition, a storage capacitor C is connected in parallel with the pixel region P, and the storage capacitor portion includes a portion of the storage wiring 16 that defines the pixel region P. The horizontal portion 30c of the pixel electrode positioned with the gate insulating layer (not shown) interposed on the first storage electrode is used as the second storage electrode.

In the above-described configuration, the data line 24, the pixel electrode 30, and the source and drain electrodes 26 and 28 are formed of the same metal layer, and these structures are formed on top of each other with the gate line and the common electrode interposed therebetween. Is configured on.

However, a residual film of the metal layer may remain on a side step of the common electrode due to a pattern defect during the process of patterning the metal layer.

Hereinafter, the process will be described with reference to FIGS. 2A to 2C.

2A to 2C are sectional views taken along the lines II-II 'and III-III' of FIG. 1 and shown in a conventional process sequence.

As shown in FIG. 2A, one selected from a group of conductive metals including aluminum (Al), an aluminum alloy such as aluminum neodymium (AlNd), and chromium (Cr) is deposited on the substrate 10 to form a gate electrode 14. A gate wiring (12 of FIG. 1), a storage wiring 16 spaced apart in parallel with the gate wiring by a predetermined distance, and a plurality of vertical parts 17b protruding vertically from the storage wiring 16; In addition, a common electrode (17 of FIG. 1) including a horizontal part (17a of FIG. 1) connecting the plurality of vertical parts 17b to one is formed.

Next, a gate insulating film 18 is formed of silicon nitride (SiN _x ) on the entire surface of the substrate 10 including the gate wiring and the storage wiring 16.

Next, amorphous silicon (a-Si: H) and amorphous silicon (n + a-Si: H) containing impurities are deposited and patterned on the gate insulating layer 18 to form an active layer 20 and an ohmic contact. Form layer 22.

As shown in FIG. 2B, one of the conductive metal groups as described above is deposited and patterned on the entire surface of the substrate 10 on which the active layer 20 and the ohmic contact layer 22 are formed. A data line 24 crossing the storage line 16 to define the pixel area P, a source electrode 26 protruding from the data line 24, and contacting the ohmic contact layer 22; A drain electrode 28 spaced at a predetermined interval, an extension portion (30a in FIG. 1) extending in one direction from the drain electrode 28 to the pixel region P, and a plurality of vertical portions extending vertically from the extension portion The pixel electrode 30 is formed of a horizontal portion 30c which connects the portion 30b and the plurality of vertical portions 30b to one.

In this case, during the patterning of the source and drain electrodes 26 and 28, the pixel electrode 30, and the data line 24, the metal layer may be formed on the stepped portion of the side surface of the common electrode vertical part 17b due to an etching failure. The remaining film 25 is generated.

As illustrated in FIG. 2C, a protective film 32 is formed by depositing silicon nitride (SiN _x ) on the entire surface of the substrate 10 on which the source and drain electrodes 26 and 28 are formed.

According to the above-described process, a conventional array substrate for a liquid crystal display device can be manufactured.

In the above-described process, during the process of forming the source and drain electrodes 26 and 28, the data line 24, and the pixel electrode 30, a metal residual film (a) along the lateral step of the common electrode 17b due to an etching failure. 25) may remain.

In particular, since the metal remaining film 25 left at the side step difference of the common electrode 17b adjacent to the data line 24 may start from the data line 24, a leakage current may be generated by the remaining film, resulting in malfunction of the substrate. May cause.

The present invention has been made for the purpose of solving the above-described problems, and forms an etching hole by etching the upper protective film corresponding to the side portion of the common electrode formed in close proximity to the data line.

In this way, the path of the leakage current can be blocked because the residual film of the lower part can be removed during the process of dry etching the etching hole.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object comprises: a gate wiring formed in one direction on a substrate, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line crossing the gate line and the storage line and defining the pixel area crossing the gate line; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A pixel electrode comprising an extension part extending from the drain electrode to the pixel area, a plurality of vertical parts extending vertically from the extension part, and a horizontal part connecting the plurality of vertical parts to one of the upper portions of the storage wiring; A common electrode extending vertically from the storage line and having a plurality of vertical parts arranged in parallel with the plurality of vertical parts of the pixel electrode, and a horizontal part connecting the plurality of vertical parts to one; And a protective layer covering the data line, the source electrode, the drain electrode, and the pixel electrode, and having an etching hole formed by etching a portion corresponding to the side portion of the vertical portion close to the data line among the plurality of vertical portions of the common electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, comprising: forming a gate wiring formed in one direction on a substrate and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Forming a common electrode including a plurality of vertical portions extending vertically from the storage line and a horizontal portion connecting the plurality of vertical portions into one; Forming a data line crossing the gate line and the storage line with a first insulating film interposed therebetween and intersecting the gate line and defining a pixel area; Forming a thin film transistor formed at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; An extension part extending from the drain electrode to the pixel region, a plurality of vertical parts extending vertically from the extension part and crossing and parallel to a plurality of vertical parts of the common electrode, and the plurality of vertical parts of the storage wiring line. Forming a pixel electrode having a horizontal portion connected to one from the top; A protective layer is formed to cover the data line, the source electrode, the drain electrode, and the pixel electrode, and an etching hole is formed in the passivation layer by etching a portion corresponding to the side portion of the vertical portion close to the data line among the plurality of vertical portions of the common electrode. It includes a step.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A feature of the present invention is to form a passivation layer on top of the array wiring configured in the transverse electric field mode, and to remove any metal remaining film under the etch by etching an arbitrary region corresponding to the side of the common electrode located close to the data wiring. will be.

3 is a plan view schematically illustrating a part of an array substrate for a transverse electric field type liquid crystal display device according to the present invention.

As illustrated, the array substrate 100 for a transverse electric field type liquid crystal display device according to the present invention includes a plurality of gate wirings 112 and storage wirings 116 formed in one direction in parallel with a predetermined interval therebetween, and the two wirings. In particular, the gate line 112 and the data line 124 define a pixel area P.                     

A thin film transistor T including a gate electrode 114, an active layer 120, a source electrode 126, and a drain electrode 128 is formed at an intersection point of the gate wiring 112 and the data wiring 124. The source electrode 126 is connected to the data line 124 and the gate electrode 114 is connected to the gate line 112.

The pixel electrode 130 connected to the drain electrode 128 and the common electrode 117 formed in parallel with the pixel electrode 130 and connected to the storage wiring 116 are disposed on the pixel area P. Configure The pixel electrode 130 may include an extension part 130a extending from the drain electrode 128, a plurality of vertical parts 130b vertically extending from the extension part 130a and spaced apart from each other by a predetermined distance, and the storage wiring line. It consists of a horizontal portion (130c) connecting the vertical portion (130b) as one at the top of the (116).

The common electrode 117 extends in the vertical direction from the storage line 116 and crosses the vertical portion 130b of the pixel electrode and the vertical portions 117b as one. It consists of a horizontal part 117a to connect.

In the above-described configuration, the metal remaining layer 125 may be formed along the side step of the common electrode due to an etching failure during the process of patterning the data line 124 and the source and drain electrodes 126 and 128.

As described above, in particular, the metal remaining film 125 left at the step of the common electrode 117b adjacent to the data line 124 may be connected to the data line 124, thereby causing a leakage current. .

Accordingly, in order to block the path of the leakage current, a portion of the passivation layer (not shown) formed on the substrate corresponding to an arbitrary portion of the side surface of the common electrode 117b adjacent to the data line 124 is etched. An etching hole 134 is formed.

During the dry etching process for forming the etching hole 134, the metal residual film 125 existing in the step of the common electrode 117b may be removed, thereby preventing the leakage current path.

Hereinafter, a manufacturing process of the transverse electric field array substrate according to the present invention will be described with reference to FIGS. 4A to 4D.

4A through 4D are cross-sectional views taken along the line IV-IV ′ and V-V ′ of FIG. 3, and according to the process sequence of the present invention.

Figure 4a is deposited on the substrate 100 selected from the group of conductive metals including aluminum (Al), aluminum alloys such as aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo), tungsten (W) And a gate wiring 112 including the gate electrode 114, a storage wiring 116 spaced apart in parallel with the gate wiring 112 by a predetermined interval, and vertically protruding from the storage wiring 116. A common electrode (17 in FIG. 3) including a plurality of vertical parts 117b and a horizontal part (117a in FIG. 3) connecting the plurality of vertical parts 117b to one is formed.

Next, an inorganic insulating material group including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) is formed on the front surface of the substrate 100 including the gate wiring 112 and the storage wiring 116. The gate insulating film 118 is formed with one.

Next, amorphous silicon (a-Si: H) and amorphous silicon (n + a-Si: H) containing impurities are deposited on the gate insulating layer 118 and patterned to form the active layer 120 and ohmic. The contact layer 122 is formed.

As shown in FIG. 4B, one of the conductive metal groups as described above is deposited and patterned on the entire surface of the substrate 100 on which the active layer 120 and the ohmic contact layer 122 are formed, thereby forming the gate wiring ( A data line 124 defining a pixel area P intersecting with 112 and the storage line 116 of FIG. 3, and a source protruding from the data line 124 and contacting the ohmic contact layer 122. The electrode 126 and the drain electrode 128 spaced apart from each other, an extension portion 130a of FIG. 3 extending from the drain electrode 128 to the pixel region P, and vertically extending from the extension portion. A pixel electrode including a plurality of vertical portions 130b and a horizontal portion 130c connecting the plurality of vertical portions 130b to one is formed.

In the above-described process, the ohmic contact layer 122 exposed between the two electrodes is etched using the source electrode 126 and the drain electrode 128 as a mask to expose the active layer 120.

At this time, during the process of patterning the source and drain electrodes 126 and 128, the pixel electrode 130, and the data line 124, the metal residual film 125 is formed in the stepped portion of the side surface of the common electrode 117b due to an etching failure. May occur.

FIG. 4C illustrates one selected from the group of organic insulating materials including benzocyclobutene and acryl-based resin on the front surface of the substrate 100 on which the data line 124 and the like are formed, or silicon oxide ( A protective film 132 is formed by coating or depositing one selected from the group of inorganic insulating materials including SiO ₂ ) and silicon nitride (SiN _X ).

Next, as shown in FIG. 4D, the protective layer 132 is patterned to etch an arbitrary region corresponding to the side step difference of the common electrode 117b adjacent to the data line 124 to etch the hole 134. To form.

In the process of forming the etching hole 134, the metal remaining film of the lower portion is removed.

Therefore, the leakage current path by the metal residual film 125 may be blocked.

Accordingly, the array substrate for a transverse electric field type liquid crystal display device according to the present invention further has an etching hole for blocking a leakage current path by the metal residual film, thereby preventing an operation failure of the substrate due to the metal residual film.

Claims (4)

A gate wiring formed in one direction on the substrate and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line crossing the gate line and the storage line and defining the pixel area crossing the gate line; A thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A pixel electrode comprising an extension part extending from the drain electrode to the pixel area, a plurality of vertical parts extending vertically from the extension part, and a horizontal part connecting the plurality of vertical parts to one of the upper portions of the storage wiring; A common electrode extending vertically from the storage line and having a plurality of vertical parts arranged in parallel with the plurality of vertical parts of the pixel electrode, and a horizontal part connecting the plurality of vertical parts to one; A passivation layer covering the data line, the source electrode, the drain electrode, and the pixel electrode, and an etching hole formed by etching a portion corresponding to the side portion of the vertical portion close to the data line among the plurality of vertical portions of the common electrode. Array substrate for a transverse electric field type liquid crystal display device comprising a. Forming a gate wiring formed in one direction on the substrate and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Forming a common electrode including a plurality of vertical portions extending vertically from the storage line and a horizontal portion connecting the plurality of vertical portions into one; Forming a data line crossing the gate line and the storage line with a first insulating film interposed therebetween and intersecting the gate line and defining a pixel area; Forming a thin film transistor configured at an intersection point of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; An extension part extending from the drain electrode to the pixel region, a plurality of vertical parts extending vertically from the extension part and crossing and parallel to a plurality of vertical parts of the common electrode, and the plurality of vertical parts of the storage wiring line. Forming a pixel electrode having a horizontal portion connected to one from the top; A protective layer is formed to cover the data line, the source electrode, the drain electrode, and the pixel electrode, and an etching hole is formed in the passivation layer by etching a portion corresponding to the side portion of the vertical portion close to the data line among the plurality of vertical portions of the common electrode. Steps to Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising a. The method of claim 2, The gate wiring, the storage wiring, and the common electrode may be formed of one selected from the group of conductive metals including aluminum (Al), aluminum alloy, tungsten (W), molybdenum (Mo), and chromium (Cr). Array substrate manufacturing method. The method of claim 2, And the first insulating layer is one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ).

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