KR100834933B1 - A method and apparatus for cancellation of offsets in comparators - Google Patents

Abstract

A method and an apparatus for canceling offsets in comparators are provided to cancel offsets of the comparators of various types, by applying stress condition of generating hot carriers. Two input ports of a comparator are precharged with an equal voltage. Offset code of the comparator is determined from the code of an output voltage by enabling the comparator under the that voltages of the two input ports are equal. Stress condition of generating hot carrier in at least one transistor constituting the comparator. The step is implemented by increasing an operation voltage of the comparator. The comparator includes at least one cross-coupled PMOS transistor(35,36) and at least one cross-coupled NMOS transistor(33,34).

Description

A method and apparatus for cancellation of offsets in comparators

1 illustrates a comparator circuit.

Figure 2 shows the output voltage for an ideal comparator.

3A shows the output form of the comparator with a negative offset, and FIG. 3B shows the output form of the comparator with a positive offset.

4 is a circuit diagram of a latch type comparator.

5 is a diagram showing that the offset voltages of the three comparators gradually converge to zero as the offset voltages of three comparators having different offsets are repeatedly performed by repeatedly performing the above three steps of the method according to the present invention. .

Figure 6 shows an embodiment of the apparatus for reducing the offset of the comparator according to the present invention, showing a latch type comparator by way of example.

Fig. 7 shows another type of circuit embodying the scheme iii) in the third step S3 of the present invention, i.e., lowering the gate voltage of the PMOS 35 to increase the current of the PMOS 35 to increase the generation of hot carriers. It is a block diagram.

FIG. 8 is an improved circuit of FIG. 6 and is a circuit diagram to compensate for the drawback of excessive current consumption in the transistor 36 corresponding to the transistor 35 applying stress in FIG. 6.

9 is a comparator circuit controlled by a clock commonly used in an input receiver or the like as another example of a comparator to which the present invention is applied.

10 and 11 are examples of circuit diagrams in which the present invention is applied to the comparator shown in FIG.

The present invention relates to a method and apparatus for reducing offset in a comparator.

Comparators are used for sense amplifiers in memory devices such as DRAMs. The comparator compares the two input voltages and outputs a digital level output voltage according to the difference between the two input voltages.

Figure 1 shows the comparator circuit, and Figure 2 shows the output voltage for an ideal comparator.

As shown in Figure 2, an ideal comparator, comparing the two input voltage values of V _{IN +} and V _IN- V _{IN +} V-is smaller than _IN- V _{OUT +} - V _OUT- value and outputs the digital level of the negative On the contrary, if V _{IN +} is greater than V _IN- , the V _{OUT +} -V _OUT- value outputs a positive digital level. An ideal comparator, as shown in Figure 2, the moment V _{IN +} becomes equal to V _IN- , that is, when V _{IN +} -V _IN- becomes zero, the V _{OUT +} -V _OUT- values are also positive at the same time at the negative digital level output. The digital level output value changes.

However, there is a real comparator called an offset. This is mainly due to various factors in the process such as material problems, pattern size, non-uniformity of doping concentration, and it is known that it is practically impossible to eliminate the offset of the comparator.

The sign of the offset of the comparator has a negative offset and a positive offset. 3A shows the output form of the comparator with a negative offset, and FIG. 3B shows the output form of the comparator with a positive offset.

In the comparator with a negative offset, as shown in Fig. 3A, the value of V _{OUT +} -V _OUT- still has a negative digital level output even when V _{IN +} -V _IN- is zero, and V _{IN +} -V _IN- is Only by V _OS will the V _{OUT +} -V _OUT- values still be converted from the negative digital level output to the positive digital level output.

In contrast, in a comparator with a positive offset, as shown in Figure 3b, the V _{OUT +} -V _OUT- value already has a positive digital level output before V _{IN +} -V _IN- becomes zero, and V _{IN +} is V. _In situations where V _OS is smaller than _IN- , ie, V _{IN +} -V _IN- is -V _OS , V _{OUT +} -V _OUT- has already been converted from a negative digital level output to a positive digital level output. Therefore, if V _{IN +} -V _IN- is zero, the value of V _{OUT +} -V _OUT- has a positive digital level output value.

Figures 3a and V _OS value indicating the degree that the comparator is erroneously determine the difference between the two input voltages in Figure 3b is referred to as an offset voltage.

The offset voltage of the comparator will affect the sense amplifier in which the comparator is used. Sense amplifiers are important components in memory devices such as DRAMs that output minute electrical signals to the digital level. The offset voltage of the comparator has a significant impact on the performance of memory devices such as sense amplifiers and DRAMs containing sense amplifiers.

The present invention provides a method and apparatus for reducing the offset voltage of a comparator.

Hereinafter, a method and apparatus for reducing an offset of a comparator according to the present invention will be described in detail with reference to the drawings.

First, the present invention will be described with reference to a latch type comparator. Of course, the technical idea of the present invention is equally applicable to other types of comparators. Here, the description will be made by taking a latch type comparator as an example for convenience.

4 is a circuit diagram of a latch type comparator. The latch type comparator includes two CMOS inverters as shown in FIG. 4, wherein the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. It has a structure Thus, in Fig. 4, the 31 and 32 nodes are both input terminals of the comparator and at the same time output terminals. This structure is called a cross-coupled inverter structure. The latch type comparator shown in FIG. 4 amplifies and outputs a small input difference through positive feedback.

Prior to describing the present invention, a method of operating the latch type comparator shown in FIG. 4 will be described. In particular, the case where the latch type comparator as shown in FIG.

The comparator of FIG. 4 is disabled because the voltages of the 37 and 38 nodes of FIG. 4 are in a high-Z state or at an intermediate voltage. In this state, the two input voltages (V _{IN +} and V _IN- ) to be compared are connected to the 31 and 32 nodes, respectively, so that the 31 and 32 nodes have the values of the two input voltages (V _{IN +} and V _IN- ) to be compared, respectively. do. When the voltages of the 37 and 38 nodes of FIG. 4 become V _dd and V _ss , the comparator of FIG. 4 is enabled. 4, when the comparator is enabled, the voltage of a node having any voltage higher than 31 and 32 nodes is increased to V _dd , and the voltage of a node having any voltage lower than 31 and 32 nodes is V _ss . The voltage at node 31 and the node at node 32 become the output voltages of the comparator (V _{OUT +} , V _OUT- ).

That is, while the comparator of FIG. 4 is disabled, 31 nodes and 32 nodes are input terminals that receive an input voltage value. However, when the comparator of FIG. 4 is enabled, the 31 and 32 nodes become output terminals having an output voltage value. will be.

An ideal comparator with no offset voltage would have an output voltage value of positive or negative digital level based on the case where the voltage difference between 31 and 32 nodes in the disabled state is zero, but the actual voltage with the offset voltage is present. This is not the case with comparators.

For example, if there is a negative offset voltage (V _OS ) in the comparator of FIG. 4, the difference is greater than the offset voltage (V _OS ) even when an input voltage of 31 nodes is greater than an input voltage of 32 nodes in the comparator of FIG. 4. If it is small, the output value of the 31 node has the output voltage value of the negative digital level, and the output value of the 32 node has the output of the positive digital level, even though the input voltage of the 31 node is larger than the input voltage of the 32 node. An error with a voltage value will occur.

Similarly, if there is a positive offset voltage (V _OS ) in the comparator of FIG. 4, the difference is greater than the offset voltage (V _OS ) even when the input voltage of the 31 node is smaller than the input voltage of the 32 node in the comparator of FIG. 4. If it is small, the output value of the 31 node has the output voltage value of positive digital level, and the output value of the 32 node has the output value of negative digital level, even though the input voltage of the 31 node is smaller than the input voltage of the 32 node. An error with a voltage value will occur.

The present invention proposes the following method to solve this problem.

First, the two input terminals V _{IN +} and V _IN− (31 nodes and 32 nodes in FIG. 4) of the comparator are precharged to the same voltage (step S1). The comparator is then enabled to measure the output voltage of the comparator (step S2). Since the voltages of the two input terminals are the same, the sign of the output voltage value of the comparator measured at this time becomes the sign of the offset voltage of the comparator. As shown in Figs. 3A and 3B, it can be seen that the sign of the output value when the voltages of the two input terminals are the same is the sign of the offset voltage.

Next, a bias for generating stress is applied to any one of the transistors constituting the comparator (step S3). Specifically, in the step S3, the electrons or holes having a fast moving speed are generated by a strong drain electric field, that is, a hot carrier. The hot carriers are trapped in the gate oxide region in the silicon channel region of the MOS structure, thereby varying the threshold voltage of the MOS transistor. In the case of the NMOS transistor, the threshold voltage is increased by the hot carriers, thereby reducing the current. In the case of the PMOS transistor, the absolute value of the threshold voltage is decreased by the hot carriers, thereby increasing the current.

Since the generation of hot carriers is closely related to the size of the drain electric field, a large drain voltage may be applied to generate a large amount of hot carriers. Since hot carriers also have a substantially proportional relationship with the amount of drain current, the amount of hot carriers is increased by increasing the drain current.

On the other hand, when hot carriers are generated due to stress, the characteristics of the transistors deviate from their initial values after fabrication. Therefore, they are generally considered to have undesirable effects in integrated circuits, which is considered to be one of device degradation. have. However, the present invention aims to achieve the object of the present invention to offset the offset of the comparator by generating hot carriers in any one or more of the transistors constituting the comparator.

For example, in a comparator such as FIG. 4, assume that the offset voltage V _OS is a negative value. Since the sign of the offset voltage is a negative value, in step S2, the voltage at 31 nodes (ie, V _{OUT +} ) becomes V _ss , and the voltage at 32 nodes (ie, V _{OUT −} ) becomes V _dd . In this state, the drain voltage corresponding to V _dd -V _ss is applied to the PMOS 35 and the NMOS 34.

In the present invention, in order to generate hot carriers by the strong drain voltage, a voltage V _pp that is greater than V _{dd which} is a typical driving voltage of the comparator is applied to the 37 node. In this case, a stronger drain voltage corresponding to V _pp -V _ss is applied to the PMOS 35 and the NMOS 34.

As such, when a strong drain voltage is applied to the PMOS 35 and the NMOS 34, hot carriers are generated. When hot carriers are generated in the PMOS 35, the absolute value of the threshold voltage of the PMOS 35 is lowered and the drain current is increased. This increases the 31 node voltage V _{OUT +} to move the offset voltage in the positive direction. As a result, the negative offset voltage is canceled out.

On the other hand, when hot carriers are generated in the NMOS 34 due to the strong drain voltage applied to the NMOS 34, the threshold voltage of the NMOS 34 increases, thereby reducing the current driving capability of the NMOS 34, thereby reducing the 32-node voltage. Since there is a possibility to raise (V _OUT- ), the result is to move the negative offset voltage further in the negative direction.

In order to solve this problem, the present invention _applies a forward voltage to the n-well voltage (V _NW ) of the PMOS 35 to lower the absolute value of the threshold voltage of the PMOS by the forward body effect of the PMOS transistor, thereby flowing the current flowing through the PMOS 35. Is selectively increased relative to the NMOS 34. In this case, the current in the PMOS 35 increases so that the PMOS 35 has better conditions for generating hot carriers than the NMOS 34, which creates more hot carriers, resulting in a negative offset voltage across the comparator. It will work in the direction to cancel in the direction. Here, the term 'forward' refers to a state in which a forward bias is applied to the pn junction formed between the body terminal and the source terminal of the transistor. That is, it means a bias condition in which the body or source node voltage of the p-type semiconductor is higher than the source or body voltage of the n-type semiconductor.

Another way to increase the current in the PMOS 35 is by the PMOS 35 lowering the gate voltage. Lowering the gate voltage of the PMOS 35 increases the current in the PMOS 35, which, in the same way as above, causes the PMOS 35 to have better conditions for hot carrier generation than the NMOS 34, creating more hot carriers. As a result, the comparator as a whole operates in a way to cancel the negative offset voltage in the positive direction.

In the comparator as shown in FIG. 4, when the offset voltage V _OS is a positive value, since the sign of the offset voltage is a positive value, in step S2, the voltage at the 31 node (that is, V _{OUT +} ) becomes V _dd . , The voltage at 32 nodes (that is, V _OUT- ) is V _ss . In this state, the PMOS (36) and NMOS (33) V _dd - will take the drain voltage corresponding to V _ss.

For Applying a voltage of V _pp than the V _dd conventional drive voltage of the comparator 37 nodes, PMOS (36) and NMOS (33) to generate hot carriers by strong drain voltage in the present invention V _pp - V The stronger drain voltage corresponding to _ss is applied.

The occurrence of hot carriers in the PMOS 36 lowers the absolute value of the threshold voltage of the PMOS 36 and increases the drain current, which increases the 32 node voltage V _OUT- to move the offset voltage in the negative direction. This results in the cancellation of the positive offset voltage.

On the other hand, when hot carriers are generated in the NMOS 33 due to the strong drain voltage applied to the NMOS 33, the threshold voltage of the NMOS 33 increases, thereby reducing the current driving capability of the NMOS 33, thereby reducing the 32-node voltage. There is a probability of raising (V _OUT- ), which results in moving the positive offset voltage further in the positive direction.

In order to solve this problem, the present invention _applies a forward voltage to the n-well voltage (V _NW ) of the PMOS 36 to lower the absolute threshold voltage of the PMOS 36 due to the forward body effect of the PMOS transistor. The current flowing in is selectively increased compared to the NMOS 33. In this case, the current in the PMOS 36 increases, causing the PMOS 36 to have better conditions for hot carrier generation than the NMOS 33, creating more hot carriers, resulting in a negative offset voltage across the comparator. It will work in the direction to cancel in the direction.

Another way to increase the current of PMOS 36 is to lower the gate voltage of PMOS 36. Lowering the gate voltage of the PMOS 36 increases the current in the PMOS 36, which, in the same manner as above, causes the PMOS 36 to have better conditions for hot carrier generation than the NMOS 33, creating more hot carriers. As a result, the comparator as a whole operates in a way to cancel the positive offset voltage in the negative direction.

In summary, according to the method of the present invention, the negative offset voltage cancels in the positive direction, and the positive offset voltage cancels in the negative direction.

On the other hand, in step S3 of the present invention, in particular, the transistor applying a stress condition for generating hot carrier is a single gate structure. This is different from offset elimination using double gates or floating gates. Since a double gate or floating gate is not applied to a DRAM to which the present invention can be applied, it is technically significant that a transistor which applies a stress condition that generates a hot carrier in the present invention has a single gate structure.

Three steps in the method according to the invention, namely precharging the input voltages V _{IN +} and V _IN− of the two input terminals of the comparator (31 nodes and 32 nodes in FIG. 4) to the same voltage Step (step S1), then enable the comparator to measure the output voltage of the comparator (step S2) and apply a stress-inducing bias to any of the transistors constituting the comparator to generate a hot carrier By canceling the offset voltage (step S3) as a basic component, the step 3 is repeated so that the offset voltage converges to zero.

5 is a diagram showing that the offset voltages of the three comparators gradually converge to zero as the offset voltages of three comparators having different offsets are repeatedly performed by repeatedly performing the above three steps of the method according to the present invention. . In FIG. 5, the unit section of the horizontal axis represents three steps of the method according to the present invention as one package.

As can be seen from FIG. 5, it can be seen that the method according to the present invention can be easily applied to a bit line sense amplifier of a device having several comparators, for example, a DRAM. Finding stress conditions that apply equally to multiple comparators (eg, stress application time) is not an easy task. However, as the method according to the invention is repeated several times with a relaxed stress condition, the offset of all comparators in the device with several comparators adaptively converges to zero with negative feedback operation.

In the above description, the method of biasing the PMOS to increase the current of the PMOS transistor has been described, but a corresponding method may be applied to the NMOS transistor. For example, applying a hot carrier stress to the NMOS 33 instead of the PMOS 35 in a comparator with a negative offset voltage is another way to offset the comparator's offset, and a strong voltage is applied to the NMOS 33 for this purpose. After step S2, it is necessary to reverse the two output terminal voltages V _{OUT +} and V _OUT− of the comparator before executing step S3.

In the following, an apparatus for implementing the method according to the present invention is described.

Figure 6 shows an embodiment of the apparatus for reducing the offset of the comparator according to the present invention, showing a latch type comparator by way of example.

In contrast to FIGS. 4 and 6, which show a general latch type comparator, means 61 and 62 for precharging the same voltage to two input terminals, 31 and 32 nodes, and 31 and 32 nodes are connected. It can be seen that the switch 60 is provided.

In the first step S1 of the present invention, an operation of precharging the input voltages V _{IN +} and V _IN− of the two input terminals 31 and 32 of the comparator to the same voltage is performed. It is preferable that the voltages of the two input terminals are precharged and adjusted at the same time, but in some cases, only the process of adjusting the voltages of the two input terminals to be the same may be performed. In the case where only the adjustment process is performed, the switch 60 connecting the two input terminals 31 nodes and 32 nodes performs this. Further, depending on the situation in which the comparator is used, when a fixed voltage is input to one of the two input terminals, no means for precharging the voltage of the corresponding input terminal is required.

In summary, in the apparatus according to the present invention, in order to perform the first step S1, at least one switch for equally adjusting the input voltages of the two input terminals of the comparator must be provided.

The present inventors note that in the device shown in Fig. 6, the transistors 60, 61, and 62 may be configured with transistors already provided for operations such as bit line sensing in the conventional DRAM. That is, there is a big advantage that the present invention can be implemented by using a transistor already provided in the existing device.

In the second step (S2) of the present invention, the output voltage of the comparator is measured by enabling the comparator in the state where the voltages of the two input terminals of the comparator are equally adjusted, so a separate device is required in addition to the existing comparator. Not.

The third step (S3) of the present invention is to generate a hot carrier by applying a stress-biasing bias to any one of the transistors constituting the comparator, in order to generate the hot carrier effectively, i) a typical driving voltage to the comparator A larger voltage is applied to node 37, ii) applying a forward voltage to the n-well voltage of the PMOS and / or iii) lowering the gate voltage of the PMOS.

The apparatus according to the invention shown in FIG. 6 for scheme i) is provided with means (not shown) for applying a voltage having a controlled value to 37 nodes. The voltage input to node 37 by this means is either a high-Z state with the comparator disabled, a V _dd which is the typical drive voltage of the comparator, or is typically applied to generate hot carriers in the PMOS 35. V _pp is a voltage larger than the driving voltage V _dd .

In the apparatus according to the invention shown in FIG. 6 for scheme ii), means for forwardly inputting and controlling the voltage V _NW of the n-well comprising the body terminals of the PMOS 35, 36 (not shown) Is provided.

Means for scheme iii), i.e., a means for lowering the gate voltage of PMOS 35 to significantly increase the current in PMOS 35 to increase hot carrier generation, can be implemented in various forms.

In the apparatus according to the embodiment shown in Fig. 6, in the third step S3 of the present invention, the method iii) is performed using a switch 60 connecting two output terminals, 31 nodes and 32 nodes. When a current flows between the 31 and 32 nodes by the switch 60, it lowers the voltage of the 32 node, which is the gate voltage of the PMOS 35, and therefore, the gate voltage of the PMOS 35 is eventually lowered. This increases the current of the PMOS 35. In the hot carrier generation in step S3 of the present invention, the switch 60 connecting 31 nodes and 32 nodes is turned on with the comparator enabled.

Again, in FIG. 6, since the transistors 60, 61, and 62 may be configured with transistors already provided for operation such as bit line sensing in the conventional DRAM, if the present invention is implemented in the same manner as in FIG. There is a great advantage in that the present invention can be implemented by using a transistor already provided in the existing device.

Fig. 7 shows another type of circuit embodying the scheme iii) in the third step S3 of the present invention, i.e., lowering the gate voltage of the PMOS 35 to increase the current of the PMOS 35 to increase the generation of hot carriers. It is a block diagram.

FIG. 7 includes switches 71 and 72 connecting two output terminals 31 and 32 to node 88 in the third step S3 of the present invention. These switches 71 and 72 also lower the voltage at the two output terminals 31 and 32 to lower the gate voltage of the PMOS 35 to increase the current of the PMOS 35 to increase the generation of hot carriers.

FIG. 8 is an improved circuit of FIG. 6 and is a circuit diagram to compensate for the drawback of excessive current consumption in the transistor 36 corresponding to the transistor 35 applying stress in FIG. 6.

In the state where hot carriers are generated in the PMOS 35, the switch 60 is turned on to lower the gate voltage of the PMOS 35 while raising the gate voltage of the PMOSs 81 and 82 provided in FIG. 81 and 82 serve as the source resistance of the PMOS 35 and 36. This source resistance does not significantly reduce the current of the PMOS 35 that is intended to generate hot carriers, while the current of the corresponding PMOS 36 that is not intended to generate hot carriers is drastically reduced so that the current in the PMOS 36 is reduced. The disadvantage of excessive consumption is compensated for.

In the above detailed description of the present invention, the present invention has been described in detail with reference to the latch type comparator shown in FIG. The idea of the present invention is not limited to the latch type comparator, but also applies to other comparators in the form of cross-coupled transistors.

In the form of a cross-coupled transistor, there are two transistors in which the output node of the first transistor is connected to the input node of the second transistor, and the output node of the second transistor is also connected to the input node of the first transistor. Refers to.

The comparator to which the present invention is applied preferably comprises at least one cross-coupled PMOS transistor and at least one cross-coupled NMOS transistor. Lol

9 is a comparator circuit controlled by a clock commonly used in an input receiver or the like as another example of a comparator to which the present invention is applied. In comparison with the comparator shown in Fig. 4, the comparator shown in Fig. 9 is separated from the input terminals V _{IN +} and V _IN- and the output terminals V _{OUT +} and V _OUT- . In addition, the output terminal is precharged when the clock signal is low due to the phase of the clock signal CLK, and the comparator is enabled or disabled by the clock signal.

10 and 11 are examples of circuit diagrams in which the present invention is applied to the comparator shown in FIG. 10 and 11 are circuit diagrams corresponding to FIGS. 6 and 7, respectively, which are circuit diagrams to which the present invention is applied to the comparator shown in FIG.

10 and 11, the present invention will be described. The first step S1 of the present invention is a comparator input and output precharge step. The two input voltages V _{IN +} and V _IN− are precharged to the reference voltage and adjusted equally by the switches shown in Fig. 10 next to the input terminals (Fig. 10: 223, 224, Fig. 11: 243, 244). In addition, the two output voltages (V _{OUT +} and V _OUT- ) are _charged as preparation steps for comparator operation. These two operations can occur sequentially or simultaneously in any order. Both of these operations make sense that the clock signal is performed low.

In order to perform the second step S2 of the present invention, the comparator is operated while the clock signal becomes high, so that the comparator gives a differential amplified output.

In the third step S3 of the present invention, as a step of applying a hot carrier stress, V _H is applied to V _pp , which is a higher voltage at a normal operating voltage, thereby increasing the drain voltage of the PMOSs 211 and 212, and The n-well voltages V _NW of 211 and 212 are applied in the forward direction, and the gate voltages of the PMOSs 211 and 212 are lowered to increase the generation of hot carriers in the PMOSs 211 and 212, thereby reducing the offset of the comparator. Will be reduced.

As shown in the examples of Figs. 9 to 11, it can be seen that the present invention can be applied to various types of comparators.

As described above, according to the present invention, by applying a stress condition for generating hot carriers, offsets of various types of comparators can be reduced. According to the present invention, by repeatedly performing the basic operation according to the present invention for offset reduction in a device equipped with a plurality of comparators having different offset values, the effects of the offsets of the plurality of comparators converge to 0, respectively. When the present invention is applied to a sense amplifier reading a bit line of a DRAM, there is an advantage that can be implemented by controlling only an input voltage using transistors already provided without adding a transistor.

Claims (24)

Precharging the two input terminals of the comparator to the same voltage (S1); Enabling the comparator in the state where the voltages of the two input terminals of the comparator are the same by determining the offset sign of the comparator from the sign of the output voltage (S2); And And (S3) subjecting any one or more of the transistors of the comparator to a stress condition generating hot carriers. The method of claim 1, The step (S3) is implemented by increasing the drive voltage of the comparator. The method of claim 2, The step (S3) further comprises the step of applying a forward bias to the n-well voltage of the transistor constituting the comparator. The method of claim 2, The step (S3) further comprises the step of increasing the current of the transistor to generate a hot carrier, reducing the offset of the comparator. The method of claim 4, wherein In the step S3, the process of increasing the current of the transistor to generate hot carriers is implemented by lowering the gate voltage of the PMOS when the transistor to generate hot carriers is a PMOS. How to reduce the offset of the comparator. The method according to any one of claims 1 to 5, And in step S3, the transistor subjecting the stress condition to generate hot carriers is a single gate structure. The method according to any one of claims 1 to 5, And repeating the steps (S1), step (S2) and step (S3). The method according to any one of claims 1 to 5, And said comparator comprises at least one component circuit in the form of a cross-coupled transistor. The method according to any one of claims 1 to 5, And the comparator is in the form of a latch. The method according to any one of claims 1 to 5, And the comparator is included in a sense amplifier for sensing the bit line voltage of the DRAM. The method of claim 8, And wherein the comparator comprises at least one cross-coupled PMOS transistor and at least one cross-coupled NMOS transistor. Means M1 for precharging the two input terminals of the comparator to the same voltage; And By means of enabling the comparator in the state where the voltages of the two input terminals of the comparator are the same and determining the offset sign of the comparator from the sign of the output voltage, hot carrier is applied to any one or more of the transistors constituting the comparator. And a means (M2) for applying a stress condition to generate the device. The method of claim 12, And said means (M2) comprises means for increasing the drive voltage of the comparator. The method of claim 13, Said means (M2) further comprising means for applying forward bias to the n-well voltage of the transistors making up the comparator. The method of claim 13, And said means (M2) further comprises means for increasing the current of a transistor to generate hot carriers. The method of claim 15, In the means M2, the means for increasing the current of the transistor to generate hot carriers is a means for lowering the gate voltage of the PMOS when the transistor to generate hot carriers is a PMOS. Device for reducing offset. The method of claim 16, And said means for lowering the gate voltage of the PMOS is a switch means for connecting two output terminals of the comparator. The method of claim 16, And said means for lowering the gate voltage of the PMOS is a switch means for connecting the two output terminals of the comparator to the lower potential (V _SS ) of the comparator's driving voltage, respectively. The method of claim 15, Apparatus for reducing the offset of a comparator, characterized in that it further comprises means for reducing the current of a transistor other than the transistor to generate hot carriers. The method according to any one of claims 12 to 19, And said means (M2), wherein the transistor subjected to the stress condition generating hot carriers is a single gate structure. The method according to any one of claims 12 to 19, And said comparator comprises at least one component circuit in the form of a cross-coupled transistor. The method according to any one of claims 12 to 19, And the comparator is in the form of a latch. The method according to any one of claims 12 to 19, And the comparator is included in a sense amplifier for sensing the bit line voltage of the DRAM. The method of claim 22, And said comparator comprises at least one cross-coupled PMOS transistor and at least one cross-coupled NMOS transistor.

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