KR100817077B1 - Method of fabricating cmos image sensor - Google Patents

Abstract

A method for fabricating a CMOS image sensor is provided to remove a step between a pixel array region and a peripheral circuit region by completing the interconnection structure of the pixel array region and performing a cavity formation process for forming a light transmission part and a planarization process before the interconnection structure of the peripheral circuit region is completed. A substrate(100) includes a pixel array region and a peripheral circuit region. A photodiode(120) and at least one transistor(130) are formed on the substrate in the pixel array region. At least two transistors(140) are formed on the peripheral circuit region. An insulation layer(200) is formed on the pixel array region and the peripheral circuit region, covering at least one of the first and second transistors. At least one of a first interconnection layer(300a,300b) electrically connected to the transistors and a first interlayer dielectric(410) for insulating the first interconnection layer are formed in the pixel array region and the peripheral circuit region. The first interlayer dielectric formed on the photodiode is etched to confine a cavity on the photodiode. A light transmission material is formed on the first interlayer dielectric to fill the cavity. The light transmission material layer is planarized until the surface of the first interlayer dielectric is exposed so that a light transmission part(500) is formed. At least one of second interconnection layer and at least one of second interlayer dielectric(420) for insulating the second interconnection layer are formed on the first interlayer dielectric in the peripheral circuit region.

Description

Method of manufacturing CMOS image sensor {Method of fabricating CMOS image sensor}

1 is a cross-sectional view schematically showing a pixel array region and a peripheral circuit region of a general CMOS image sensor.

2A to 2E are sectional views showing the cavity forming process of the CMOS image sensor shown in FIG.

3A to 3F are cross-sectional views illustrating a manufacturing method of a CMOS image sensor according to an exemplary embodiment of the present invention in a process sequence.

Explanation of symbols on the main parts of the drawings

100: substrate 110: device isolation film

120: photodiode 130, 140: transistors

200: insulating film 300a, 300b: wiring layer

410, 420, and 430: interlayer insulating film 500: light transmitting portion

600: color filter

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor including a multilayer wiring.

Recently, digital cameras are being widely commercialized as they replace conventional film cameras and are combined with other digital products such as cameras or mobile phones, and the demand for miniaturization and light weight is increasing at the same time. As a solid-state imaging device for implementing a digital camera, a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor is used.

CMOS image sensor among solid-state imaging devices can use high-definition semiconductor process to achieve high image quality, and integrate low voltage, low power consumption, and peripheral circuits that perform various functions on a single chip. Therefore, there is an advantage in miniaturization and light weight. Because of these advantages, CMOS image sensors are widely used in electro-optical products such as digital cameras.

In general, a CMOS image sensor includes a pixel array region consisting of a plurality of unit pixels and a peripheral circuit region for driving the pixel array. The unit pixel includes a photodiode region, which is a light receiving unit, and one or more transistor regions connected to the photodiode. In the transistor region, a transfer transistor for transporting charges generated by the photodiode to the floating diffusion region, a reset transistor for periodically resetting the charge stored in the floating diffusion region, and a source follower buffer amplification function, Drive transistors for buffering signals according to charged charges and select transistors serving as switches for selecting the unit pixels may be disposed.

1 is a cross-sectional view schematically showing a pixel array region and a peripheral circuit region of a general CMOS image sensor.

Referring to FIG. 1, a CMOS image sensor includes a semiconductor substrate 10 having a pixel array region and a peripheral circuit region. In the semiconductor substrate 10, an element isolation film 11 defining an active region is formed. A PN junction diode may be formed in the photodiode region of the semiconductor substrate, and a plurality of transistors for processing a current signal generated from the PN junction diode may be formed in the transistor region. In the peripheral circuit region, a plurality of transistors may be formed as driving elements for driving the pixel array. An insulating film for insulating them is formed on the photodiode and these transistors, and at least one wiring layer electrically connected to the transistor and an interlayer insulating film for insulating the wiring layer may be formed on the insulating film.

In general, in a CMOS image sensor, in order to increase light sensitivity, a portion of an insulating film formed on a photodiode region and an interlayer insulating film are removed to define a cavity, and a light transmitting portion made of a light transmitting material having a single refractive index in the cavity is defined. Form. If the insulating film and the interlayer insulating film having different refractive indices are not removed on the photodiode region, the light irradiated to the photodiode region is reflected or absorbed along the incident path so that only a portion of the irradiated light reaches the photodiode. . In this case, since the photosensitivity can be reduced, a conventional CMOS image sensor includes a cavity on the photodiode region.

2A to 2E are sectional views showing the cavity forming process of the CMOS image sensor shown in FIG.

Referring to FIG. 2A, as described above, the photodiode 12 and the transistors 13 and 14 are formed on the semiconductor substrate 10 including the pixel array region and the peripheral circuit region, and the photodiode 12 is formed. The insulating film 10 is formed on the transistors 13 and 14. Subsequently, the wiring process and the interlayer insulating film forming process are repeated to insulate the one or more wiring layers 31, 32, and 33 and the wiring layers 31, 32, and 33 on the semiconductor substrate 10. 43) to complete the wiring structure.

Referring to FIG. 2B, in order to form a cavity (C of FIG. 2C) to be described later, an unnecessary interlayer insulating layer 43 existing on the pixel array region, for example, an interlayer insulating layer deposited together during the wiring process of the peripheral circuit region. (43) can be removed. As shown, when the number of the wiring layers 30a and 30b in the peripheral circuit region and the pixel array region are different, a step S may occur between the peripheral circuit region and the upper surface of the pixel array region.

Referring to FIG. 2C, as is well known in the art, a predetermined mask pattern is formed by a photolithography process and a dry etching process by plasma is performed to form interlayer insulating films 41 and 42 on the photodiode region. A cavity C penetrating the through is formed.

Referring to FIG. 2D, the light transmitting material layer 50L ₁ is coated on the interlayer insulating layers 42 and 43 to fill the cavity C by a spin coating process.

Referring to FIG. 2E, an etch back process by plasma etching is performed until the surface of the interlayer insulating layer 42 is exposed to perform a planarization process on the light transmitting material layer 50L ₁ in the cavity C. The transmission part 50 is formed. Because of the step S caused by the interlayer insulating film 43 in the peripheral circuit region, the coated light transmissive material layer 50L ₁ may vary in thickness depending on the location. For example, in the region where the step S is present, the thickness t of the light transmitting material layer 50L1 may have a larger thickness h than other positions. For this reason, a part R of the light transmitting material layer may remain on the region where the step S exists after the etch back process.

Referring to FIG. 2F, an etch back process may be performed to prevent the light transmitting material layer from remaining on the interlayer insulating layer 42. At this time, the light transmitting portion 50 'in the cavity 50 is excessively etched, so that the surface of the light transmitting portion 50' in the cavity C may have a concave shape. Such a concave shape is undesirable because it leads to a bending phenomenon of the subsequent color filter 60.

Referring to FIG. 2G, the light transmitting material layer 50L ₂ is further coated by a small thickness to prevent the concave surface shape from being caused by the etchback process described above. As such, when the light transmitting portion 50 'is completed, the color filter 60 is formed on the surface of the light transmitting portion 50'.

As described above, the conventional process of forming the light transmitting portion 50 'and the color filter 60 in the cavity C includes a planarization process and a process of recoating the light transmitting material layer by a small thickness. They have a problem that reproducibility is not secured in actual application. For this reason, in the CMOS image sensor produced, variations in light sensitivity and color reproducibility occur for each product, and thus, quality control is difficult.

Accordingly, the technical problem to be achieved by the present invention is to provide a planarization process having excellent process reproducibility, in order to form a light transmitting part in the cavity, and thus, to provide a CMOS image sensor having a uniform quality. It is to provide a manufacturing method.

According to one or more exemplary embodiments, a method of manufacturing a CMOS image sensor includes preparing a substrate having a pixel array region and a peripheral circuit region. A photodiode and one substrate on the substrate of the pixel array region are provided. One or more first transistors are formed, and one or more second transistors are formed on the peripheral circuit region. Then, an insulating film is formed on the pixel array region and / or the peripheral circuit region to cover a transistor which is any one or a combination of the photodiode, the first transistor, and the second transistor. Forming at least one first wiring layer electrically connected to the transistors and a first interlayer insulating layer insulating the first wiring layer in the pixel array region and the peripheral circuit region.

Thereafter, the first interlayer insulating layer formed on the photodiode is etched to define a cavity on the photodiode and to form a light transmitting material layer filling the cavity on the first interlayer insulating layer. In some embodiments of the present disclosure, when defining the cavity, a portion of the insulating layer may be further etched to increase light transmittance.

Next, the light transmitting material layer is planarized to form a light transmitting part until the surface of the first interlayer insulating film is exposed. After the planarization of the light transmitting part is completed as described above, one or more second interlayer insulating films are formed on the first interlayer insulating film of the peripheral circuit region to insulate the one or more second wiring layers and the second wiring layers.

In example embodiments, the method may further include exposing an upper surface of the light transmitting part by removing the second interlayer insulating layer deposited on the pixel array region while forming the second wiring layer and the second insulating layer. Can be. To this end, the step of forming a color filter on the exposed upper surface of the light transmitting portion is further performed.

In some embodiments of the present disclosure, the second interlayer insulating layer may be formed of a material having an etch selectivity with respect to the light transmitting material layer in order to protect the upper surface of the light transmitting portion from the etching process of the second interlayer insulating layer. . In another embodiment of the present invention, an etch stop layer may be formed between the first interlayer insulating film and the second interlayer insulating film.

In an embodiment of the present invention, the light transmitting material layer may be silicon oxide or silicon nitride. These light transmissive material layers can be planarized by a chemical mechanical polishing process or an etch back process by plasma.

According to the exemplary embodiment of the present invention, before the wiring structure of the peripheral circuit region is completed, a planarization process for forming the light transmitting portion is performed so that there is no step between the pixel array region and the peripheral circuit region, thereby having a uniform upper surface. It is possible to provide the light transmitting portion. Accordingly, it is possible to provide a color filter defined with a precise size and shape on the upper surface of the light transmitting portion, thereby providing a CMOS image sensor having a uniform quality.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer interposed therebetween. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

3A to 3F are cross-sectional views illustrating a manufacturing method of a CMOS image sensor according to an exemplary embodiment of the present invention in a process sequence.

Referring to FIG. 3A, a semiconductor substrate having a pixel array region and a peripheral circuit region is prepared. A device isolation film 110 defining these regions is formed by a shallow trench insulating film (STI) forming process or the like.

The pixel array region includes a plurality of unit pixels including a photodiode region in which the photodiode 120, which is a light receiving unit, and a transistor region in which the first transistors 130, such as a transfer transistor, a reset transistor, a drive transistor, and a select transistor, are formed. It is an area to be arranged. The peripheral circuit region is a region where peripheral circuits such as the second transistor 140 for driving the transistors of the pixel array region are disposed. In some embodiments of the present invention, the first transistor 130 and the second transistor 140 may be simultaneously formed by the same process.

Thereafter, an insulating film 200 covering the photodiode 120 and the first transistor 130 is formed on the pixel array region or the peripheral circuit region. An insulating layer 200 covering the second transistor 140 in the peripheral circuit region is also formed. In some embodiments of the present invention, the insulating film 200 forms a single insulating film to cover all of the photodiode 120, the first transistors 130, and the second transistors 140 in the pixel array region and the peripheral circuit region. Can be deposited by a process.

The first wiring layers 300a and 300b connected to the transistors 130 and 140 by via plugs or the like penetrating through the insulating film 200 and / or the first interlayer insulating films 410 and 420. The process of forming the first interlayer insulating films 410 and 420 that insulate the first wiring layers 300a and 300b is repeated at least once to complete the wiring structure of the pixel array region. As used herein, the first wiring layer 300a is disposed in the pixel array region and includes a wiring layer including all the wirings 310 and 320 up to the top wiring layer 320 for completing the wiring structure of the pixel array region. Refers to. In some embodiments of the present invention, when the first wiring layer 300a is formed, the wiring layers 300b and 310 of the wiring layers 300b electrically connected to the transistor 140 and the interlayer insulating films 410 and 420 simultaneously on the peripheral circuit region. Can be formed.

Referring to FIG. 3B, the first interlayer insulating layers 410 and 420 formed on the photodiode 120 in the pixel array region are etched to define the cavity C on the photodiode 120. Cavity C may be formed by a plasma dry etching process as is well known in the art. In the etching process for forming the cavity C, a portion of the insulating film 200 may be further etched to further increase the light transmittance incident on the photodiode.

Referring to FIG. 3C, a light transmitting material layer is coated on the first interlayer insulating layer 420 to fill the cavity C. Referring to FIG. Thereafter, the light transmitting material layer may be planarized to form the light transmitting part 500 until the upper surface of the first interlayer insulating layer 420 is exposed. The light transmitting material layer may be planarized by a chemical mechanical polishing process or an etch back process by plasma.

In some embodiments of the present invention, the light transmitting material layer may be silicon oxide or silicon nitride, and may be formed by chemical vapor deposition. In another embodiment of the present invention, the light transmitting material layer may be made of an organic polymer compound. For example, the light transmitting material layer may be made of a fluorine-based polymer having a ring structure called Cytop ™ (Asahi Glass Company), or a polymer of a polymethyl methacrylate (PMMA) series.

Referring to FIG. 3D, after forming the light transmitting unit 500 as described above, at least one second wiring layer 330 and the second wiring layer 330 are insulated on the first interlayer insulating layer 420 of the peripheral circuit region. The second interlayer insulating film 430 may be formed. The connection pad 340 may be formed by forming an opening in the second interlayer insulating layer 430 to expose a portion of the surface of the second wiring layer 330.

Although not shown, in some embodiments of the present invention, the etch stop layer is further formed on the surfaces of the light transmitting part 500 and the first interlayer insulating layer 420 before the second interlayer insulating layer 430 is formed, thereby forming a subsequent pixel. The surface of the light transmitting part 500 may be protected in the process of removing the second insulating layer 430 on the array region. In another embodiment of the present invention, a material having an etch selectivity with the light transmitting material layer may be used as the second interlayer insulating film 430. For example, when the light transmitting material layer is silicon nitride, the second interlayer insulating film 430 may use a silicon oxide film. The reverse is also possible.

Referring to FIG. 3E, after the wiring structure 300b of the peripheral circuit region is completed, the second interlayer insulating layer 430 formed on the pixel array region in order to prevent an unnecessary increase of an optical path for light incident on the photodiode. ) May be removed to expose the top surface of the light transmitting part 500. The second interlayer insulating layer 430 may be protected by plasma dry etching up to the above-described etch stop layer.

Referring to FIG. 3F, a color filter 600 may be formed on the upper surface of the exposed light transmitting part 500. According to the exemplary embodiment of the present invention, before the wiring structure 300b of the peripheral circuit region is completed, a planarization process for forming the light transmitting part 500 is performed, so that there is no step between the pixel array region and the peripheral circuit region. It is possible to provide the light transmitting portion 500 having a uniform top surface. Since the color filter 600 is formed on the light transmitting part 500 having the uniform upper surface, the color filter 600 may be provided that is limited to the exact size and shape instead of the color filter 600 having the concave shape.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and alterations are possible within the scope without departing from the technical spirit of the present invention, which are common in the art. It will be apparent to those who have knowledge.

In the method for manufacturing a CMOS image sensor of the present invention, before the wiring structure of the peripheral circuit region is completed, the cavity formation process for forming the light transmitting portion 500 and the planarization of the light transmitting material layer are completed before the wiring structure of the pixel array region is completed. The process is performed to eliminate the step between the pixel array region and the peripheral circuit region. As a result, the light transmitting unit 500 provided by the planarization process may have a uniform upper surface, and in this case, a chemical mechanical polishing process having excellent process reproducibility may be applied, thereby providing a CMOS image sensor having a uniform quality. can do.

Claims (9)

Providing a substrate having a pixel array region and a peripheral circuit region; Forming a photodiode and at least one first transistor on a substrate in the pixel array region; Forming at least one second transistor on the peripheral circuit area; Forming an insulating film on at least one of the photodiode, the first transistor, and the second transistor on the pixel array region and the peripheral circuit region; Forming at least one first wiring layer electrically connected to the transistors and a first interlayer insulating film in the pixel array region and the peripheral circuit region to insulate the first wiring layer; Etching the first interlayer insulating film formed on the photodiode to define a cavity on the photodiode; Forming a light transmissive material layer filling the cavity on the first interlayer insulating film; Forming a light transmitting part by planarizing the light transmitting material layer until the surface of the first interlayer insulating film is exposed; And Forming at least one second wiring layer and at least one second interlayer insulating film on the first interlayer insulating film in the peripheral circuit area to insulate the at least one second wiring layer and the second wiring layer. The method of claim 1, Defining the cavity, further etching a portion of the insulating film to define a cavity on the photodiode; The method of claim 1, And forming a color filter on the upper surface of the light transmitting portion. The method of claim 3, wherein prior to forming the color filter, Forming a second wiring layer and the second insulating layer to remove the second interlayer insulating film deposited on the pixel array region to expose the upper surface of the light transmitting portion. . The method of claim 1, And the second interlayer insulating layer is made of a material having an etch selectivity with the light transmitting material layer. The method of claim 1, And the light transmitting material layer is silicon oxide or silicon nitride. The method of claim 1, And forming an etch stop layer between the first interlayer insulating film and the second interlayer insulating film. The method of claim 1, And the light transmitting material layer is planarized by a chemical mechanical polishing process. The method of claim 1, And the light transmitting material layer is planarized by an etch back process by plasma.

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