KR100806907B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention discloses a liquid crystal display and a driving method thereof for maximizing the filling rate during line inversion driving. According to the present invention, the timing controller outputs RGB input data, a first timing signal having a variable pulse period according to the inverted polarity per frame, and a second timing signal having a variable pulse period according to the inverted polarity per frame, When loading the RGB input data, different loading processing time for writing each data line according to the first timing signal, converting the loaded RGB input data and outputting them to the data line of the liquid crystal panel, the gate driver is the second timing According to the signal, a plurality of gate signals for controlling the switching element of the liquid crystal panel on / off are output to the gate line of the liquid crystal panel. As a result, when displaying an image by using the n-line inversion driving method, the pulse width of the first data signal in the same polarity section is extended than the pulse width in the normal driving, and the pulse width of the remaining data signals in the normal driving It is possible to maximize the charging rate of the pixel electrode by reducing the pulse width and adjusting the pulse width so that the gate signal does not overlap only when the data signal of the first polarity is changed to the data signal of the second polarity.

LCD, fill factor, pixel, pixel, line inversion, polarity inversion, pulse width

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a diagram for describing a deterioration in image quality of a liquid crystal display using the line inversion driving method.

2 is a view for explaining a difference in filling rate in the conventional line inversion driving method.

3 is a diagram for describing a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a view for explaining a filling rate in the line inversion driving method according to the present invention.

5 is a waveform diagram illustrating a control signal of a gate driver for driving a conventional liquid crystal display.

6 is a waveform diagram illustrating a control signal of a gate driver for driving a liquid crystal display according to a first embodiment of the present invention.

7 is a waveform diagram illustrating a control signal of a gate driver for driving a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating a generation position of a TP signal in FIG. 7.

9 is a waveform diagram for explaining a general n-line inversion, and in particular, four-line inversion driving will be described as an example.

10 is a waveform diagram illustrating an output signal of a gate driver for driving a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 11 is a waveform diagram illustrating an example of the implementation of FIG. 10.

FIG. 12 is a waveform diagram illustrating another example of the implementation of FIG. 10.

FIG. 13 is a waveform diagram illustrating an output signal of a gate driver for driving a liquid crystal display according to a fourth exemplary embodiment of the present invention.

14 is a waveform diagram illustrating an example of the implementation of FIG. 13.

<Description of the symbols for the main parts of the drawings>

100: timing controller 200: data driver

300; Gate Driver 400: Liquid Crystal Panel

STV: Vertical Sync Start Signal CPV: Gate Select Signal

OE: output enable signals G1, G2, ..., Gn: gate signals

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of compensating for deterioration of image quality in a liquid crystal display device having an n-line inversion driving method.

In general, a liquid crystal display (hereinafter referred to as LCD) is a display that obtains a desired image signal by applying an intensity-controlled electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, thereby controlling the amount of light transmitted through the substrate. Device. The LCD includes a plurality of scan lines for transmitting a gate selection signal and data lines intersecting the scan lines and for transmitting image data, and formed in an area surrounded by the scan lines and the data lines, respectively. It includes a plurality of pixels in the form of a matrix connected through a data line and a switching element.

The method of applying image data to each pixel in such an LCD is as follows.

First, when the gate on / off signal is sequentially applied to the gate lines, the switching elements connected to the scan line are sequentially turned on and off, and at the same time, an image signal to be applied to the pixel row corresponding to the scan line, more specifically, Supplies the gray voltage to the data lines, respectively. Then, the image signal supplied to the data line is applied to each pixel through the turned on switching element. In this case, the gate signal is sequentially applied to all the scan lines for one frame period to apply the pixel signal to all the pixel rows, thereby displaying an image of one frame.

On the other hand, the liquid crystal material has a problem in that it deteriorates when an electric field in the same direction is continuously applied. That is, when the polarity of the applied voltage of one pixel receives the positive signal voltage, it is necessary to receive the negative signal voltage in a certain frame. As a result, the polarity of the applied voltage of the specific pixel should be made to repeat the positive and negative polarities.

For this reason, a dot inversion method (DIM) for inverting polarity with a pixel unit is used in a liquid crystal display to invert an LCD.

By the way, when the display of the halftone screen such as the end of the window in the liquid crystal display device using the dot inversion driving method, there is a problem that the screen shake phenomenon occurs severely. In addition, the dot inversion driving method has a problem in that a power consumption problem is large because a data line must be driven with a large amplitude.

In order to solve this problem, a line inversion method (LIM) for inverting polarity in a line unit is used in a liquid crystal display.

However, the line inversion driving method causes a deterioration in image quality as shown in FIG. 1 when the displayed screen is the same gray level.

FIG. 1 is a diagram for describing a deterioration in image quality of a liquid crystal display using a line inversion driving method. In particular, a two-line inversion driving method is taken as an example.

As shown in Fig. 1, even if the same gray is displayed in the line inversion, the reason why different image quality is displayed according to adjacent rows (or lines) is a phenomenon due to a difference in charging time.

That is, in the two-line inversion, since the polarity is changed at intervals of two lines, when the entire screen displays the same gray pattern, the charging characteristic of the data line is as shown in FIG. 2.

2 is a view for explaining the difference in the filling rate in the conventional line inversion driving method, in particular, taking 2-line inversion as an example.

As shown in Fig. 2, positive (+) polarity data voltages are applied to the (4n-2) th line and the (4n-1) th line, respectively, and negative to the nth line and the (4n + 1) th line. A negative data voltage is applied respectively.

However, a difference in charging characteristics occurs in a line having the same polarity as the previous line, and a line having a different polarity from the previous line takes a long time to charge the data line, thereby writing data other than desired data. Therefore, there is a problem that a poor image quality of the horizontal line occurs as shown in FIG.

Accordingly, an object of the present invention is to provide a liquid crystal display device for maximizing a filling rate in a liquid crystal display device having an n-line inversion driving method.

Another object of the present invention is to provide a method of driving the above liquid crystal display.

According to an aspect of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and an area surrounded by the gate lines and the data lines. A liquid crystal display device comprising: a plurality of pixels formed in a matrix and arranged in a matrix form having switching elements connected to the gate line and the data line, respectively;

A timing controller configured to output RGB input data input from an external graphic controller, a first timing signal having a variable pulse period according to the inverted polarity of each frame, and a second timing signal having a variable pulse period according to the inverted polarity of each frame;                     

A data driver for differently loading a time for writing each data line according to the first timing signal when the RGB input data is loaded, and converting the loaded RGB input data to output the data line; And

And a gate driver configured to output a plurality of gate signals for operating on / off of the switching element according to the second timing signal.

In addition, a method of driving a liquid crystal display according to another aspect of the present invention includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and the gate lines and data. A driving method of a liquid crystal display device including a plurality of pixels formed in a region surrounded by a line and arranged in a matrix form having switching elements connected to the gate line and the data line, respectively.

(a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof;

(b) outputting a TP signal having a controlled generation position within an N-line inversion period based on the DE signal;

(c) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line;

(d) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the data enable signal; And

(e) based on the CPV, adjacent to a first gate signal having a wider pulse width than that in normal driving and a gate signal applied to a previous gate line so as to be within a generation range of the first data signal in a data period of the same polarity; Supplying the remaining gate signal to the gate line.

Here, the step (e),

The method may further include outputting an OE signal having a generation period of an N line inversion period to supply the remaining gate signal adjacent to the gate signal applied to the previous gate line to the gate line.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, the gate lines and A driving method of a liquid crystal display device comprising a plurality of pixels formed in a region surrounded by a data line and arranged in a matrix form each having a switching element connected to the gate line and the data line.

(a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof;

periodically adjusting the distance of the inactive section of the DE signal periodically;

(c) outputting a TP signal having a regulated generation position within an N-line inversion period based on the adjusted DE signal;

(d) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line;

(e) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the DE signal; And

(f) based on the CPV, adjacent to the first gate signal having a wider pulse width than that in normal driving and the gate signal applied to the previous gate line so as to be within the generation range of the first data signal in the data period of the same polarity; Supplying the remaining gate signal to the gate line.

Here, the step (b) is,

It is preferable to periodically adjust the distance of the inactive section of the DE signal by using a predetermined line memory.

In addition, the above step (f),

The method may further include outputting an OE signal having a generation period of an N line inversion period to supply the remaining gate signal adjacent to the gate signal applied to the previous gate line to the gate line.

According to yet another aspect of the present invention, there is provided a method of driving a liquid crystal display device, including a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and the gate lines. And a plurality of pixels formed in a region surrounded by a data line and arranged in a matrix form having switching elements connected to the gate line and the data line, respectively.                     

(a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof;

(c) outputting a TP signal having an adjusted generation position within an N-line inversion period based on the DE signal;

(d) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line;

(e) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the DE signal; And

(f) On the basis of the CPV, the first gate signal having a wider pulse width than that in the normal driving and the gate signal applied to the previous gate line so as to be within the generation range of the first data signal in the data period of the same polarity; Supplying the remaining gate signal to the gate line.

Here, step (f) described above,

The method may further include outputting a (N-1) type OE signal having different generation periods to supply the remaining gate signal overlapping with the gate signal applied to the previous gate line to the gate line.

According to the liquid crystal display and the driving method thereof, when displaying an image by using the n-line inversion driving method, the pulse width of the first data signal in the same polarity section is extended than the pulse width in the normal driving, and the remaining data signals The pulse width of is smaller than the pulse width at the time of normal driving, and maximizes the charging rate of the pixel electrode by adjusting the pulse width so that the gate signal does not overlap only when the data signal of the first polarity is changed to the data signal of the second polarity. can do.

In addition, according to the liquid crystal display and the driving method thereof, when displaying an image by using the n-line inversion driving method, the pulse width of the first data signal of the same polarity section is extended to the pulse width during the normal driving, and the rest The pulse width of the data signal is smaller than the pulse width in normal driving, generates the first gate signal within the first data signal generation period, and generates the remaining gate signals to overlap the gate signal applied to the previous gate line. Only when the polarity data signal is changed to the data signal of the second polarity, the pulse width may be adjusted so that the gate signal does not overlap, thereby maximizing the charging rate of the pixel electrode.

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

3 is a diagram for describing a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller 100, a data driver 200, a gate driver 300, and a liquid crystal panel 400.

The timing controller 100 includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and RGB image data R [0: N] and G [applied from an external graphic controller (not shown). 0: N], G [0: N]), a data enable signal DE, and the like, based on a vertical sync signal Vsync and a horizontal sync signal Hsync for controlling the display of the RGB data. One timing signal is generated, and the RGB image data R [0: N], G [0: N], and G [0: N] are output to the data driver 200 together with the generated first timing signal. Here, the first timing signal includes a load signal LOAD or TP for starting output to the data drive IC after completion of the RGB data transmission, and a horizontal synchronization start signal STH for notifying the start of scan lines.

In addition, the timing controller 100 generates a second timing signal based on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync for controlling the display of the RGB data DATA, and generates the generated second timing signal. Output to the gate driver 300.

The second timing signal may include a gate select signal (Gate clk or CPV) for controlling the output of the gate on / off signal, a vertical sync start signal STV for selecting the first scan line, and an output enable signal OE. If the polarity of the current scan line is different from the polarity of the immediately previous scan line, control to generate a wider pulse width gate on / off signal, and the polarity of the current scan line is the same as the polarity of the immediately previous scan line. Control to generate a gate on / off signal with a narrower pulse width.

The data driver 200 is a kind of source driver, which is composed of a plurality of data drive ICs, and receives RGB image data R [0: N], G [0: N], and G [0 applied from the timing controller 100. : N]) is stored in a shift register (not shown), and when the horizontal synchronization start signal STH is applied, the plurality of data configured in the liquid crystal panel 400 are converted into voltages corresponding to RGB image data. Pass on the line.                     

That is, when the horizontal synchronization start signal corresponding to the first scan line to the last scan line is input, the data driver 200 transmits the corresponding RGB image data to the liquid crystal panel 400.

The gate driver 300 is a gate driver. The gate driver 300 includes a plurality of gate driver ICs, and receives a gate selection signal (Gate clk or CPV) and a vertical synchronization start signal (STV) provided from the timing controller 100. A plurality of gate on / off signals (or gate pulses) G1, G2,..., Gn are sequentially applied to the plurality of scan lines configured in the liquid crystal panel 400. The gate on / off signal output at this time is a pulse whose width is controlled by the control of the timing controller 100.

That is, the pulse width of the gate on / off signal applied to the scan line whose polarity is different is controlled by the timing controller 100 to have a wider width, and the gate on / off signal applied to the scan line having the same polarity as the previous line. Is controlled by the timing controller 100 to have a narrower width.

The liquid crystal panel 400 includes a plurality of pixel electrodes composed of m × n matrix types, and gate on / off signals G1, G2,..., Gn provided from the gate driver 300 are applied to the corresponding pixels. As applied, the corresponding pixel electrode is driven in response to the data voltages D1, D2,..., And Dm provided from the data driver 200 to display an image.

As described above, according to the present invention, the pulse width of the gate on / off signal applied to the scan line having a different polarity when compared to the polarity of the immediately preceding scan line in the liquid crystal display panel arranged on a plane is wider. The pulse width of the gate on / off signal applied to the scan line having the same polarity is controlled to have a narrower pulse width, thereby overcoming the difference in charge rate between the scan lines generated during the line inversion driving.

In addition, it is possible to eliminate the adverse effect of the image quality displayed in the horizontal line form by overcoming the filling rate between the scan lines.

4 is a view for explaining the filling rate in the line inversion driving method according to the present invention. In particular, two-line inversion driving is taken as an example.

Referring to FIG. 4, it can be seen that the peak value of the voltage applied to the 4n-2 th scan line and charged is the same as the peak value of the voltage applied to the 4n-2 th scan line and charged, and is applied to the 4n th scan line. The lowest value of the charged voltage is applied to the 4n + 1th scan line to confirm that the lowest value of the charged voltage is the same.

That is, in the case of a specific frame of the LCD having the 2-line inversion driving method, the pulse width of the odd-numbered gate on / off signal is converted to be wider than the pulse width of the normal gate on / off signal, and the even-numbered gate on / off is output. The pulse width of the off signal is converted to be narrower than the pulse width of the normal gate on / off signal, so that the charge rate difference generated during the 2-line inversion can be overcome.

On the other hand, in the case of a specific frame of the LCD having a 3-line inversion driving method, the pulse width of the 3n (n is a positive integer including 0) th gate on / off signal is wider than the pulse width of the normal gate on / off signal. Converts and outputs the pulse widths of the 3n + 1 and 3n + 2th gate on / off signals to be narrower than the pulse widths of the normal gate on / off signals, thereby overcoming the difference in charge rate generated during 3-line reversal. It is obvious that this can be done, and it is obvious that the present invention can also be applied to a four-line inversion driving method or a five-line inversion driving method.

5 is a waveform diagram illustrating a control signal of a gate driver for driving a conventional liquid crystal display.

Referring to FIG. 5, when the gate selection signal CPV is switched from the low level to the high level according to the application of the vertical synchronization start signal STV for notifying the start of the frame, the gate on / off signals G1, G2, G3, The pulse of the G4) is changed from low to high level to maintain the high level, but the pulse of the gate on / off signals G1, G2, G3, and G4 is applied at the high level as the output enable signal OE is applied. Switch to the low level.

In this manner, the gate on / off signals are sequentially applied to the scan line corresponding to one frame, but the conventional gate on / off signals have the same pulse width regardless of the charging characteristics of the scan line. The poor image quality of FIG. 1 occurred due to the difference in the filling rate of 2.

However, according to the present invention, by adjusting the pulse width of the gate on / off signal, the poor image quality can be compensated by generating the gate on / off signal with the pulse width adjusted to reflect the charging characteristic of the line.

6 is a waveform diagram illustrating a control signal of a gate driver for driving a liquid crystal display according to a first embodiment of the present invention.                     

As shown in FIG. 6, the pulse width of the gate on / off signal is adjusted by changing the pulse width of the output enable signal OE, after applying the first and third gate on / off signals G1 (G3). Output an output enable signal (circular display) having a width wider than that of the normal output enable signal, and after the second and fourth gate on / off signals G2 (G4) are applied, the output enable signal has a narrower width than the normal output enable signal. Output the output enable signal.

In order to compensate for the deterioration of image quality caused by the two-line inversion driving method, the pulse width of the gate on / off signal applied to one line using two lines as one unit is larger than the normal width and the other Although the pulse width of the gate on / off signal applied to the line is generated to be smaller than normal, the pulse width of the gate on / off signal is applied to the line.

That is, in the three-line inversion driving method, the pulse width of the gate on / off signal applied to the first line with three lines as one unit is larger than normal, and the pulse width of the gate on / off signal applied to the second and third lines is By making it smaller than normal, it is possible to compensate for the deterioration in image quality caused by line inversion.

As described above, according to the first embodiment of the present invention, by changing only the width of the output enable signal OE, which is an input signal of the gate driver, for each line, it is possible to compensate for the image quality deterioration phenomenon generated during line inversion.

7 is a waveform diagram illustrating a control signal of a gate driver for driving a liquid crystal display according to a second exemplary embodiment of the present invention.                     

As shown in FIG. 7, the pulse width of the gate on / off signals G1, G2, G3, ... is adjusted by simultaneously changing the period of the gate selection signal CPV and the period of the output enable signal OE. The pulse width of the gate on / off signal G1 (G3) applied to the odd scan line is changed to have a pulse width larger than normal, and the gate on / off signal G2 (G4) applied to the even scan line is applied. Pulse width is changed to have a pulse width smaller than normal.

In order to compensate for the deterioration of image quality caused by the two-line inversion driving method, the pulse width of the gate on / off signal applied to one line using two lines as one unit is larger than the normal width and the other Although the pulse width of the gate on / off signal applied to the line is generated to be smaller than normal, the pulse width of the gate on / off signal is applied to the line.

That is, in the three-line inversion driving method, the pulse width of the gate on / off signal applied to the first line with three lines as one unit is larger than normal, and the pulse width of the gate on / off signal applied to the second and third lines is By making it smaller than normal, it is possible to compensate for the deterioration in image quality caused by line inversion.

As described above, according to another embodiment of the present invention, the gate selection signal CPV, which is a control signal of the gate driver, has a different period in units of lines, and in conjunction with this, the output enable signal OE is also different from each other. By changing to have a period, it is possible to improve the poor image quality due to the difference in the charge rate generated when the line reversal.                     

At this time, the position of the load signal LOAD or TP, which is a signal that latches data of the data driver 200 and commands to drive the data line, is adjusted. In particular, the position of the TP signal is interlocked with the position of the gate selection signal CPV. It is desirable to.

FIG. 8 is a waveform diagram illustrating a generation position of a TP signal in FIG. 7.

As shown in FIG. 8, the generation position of the TP signal TP-O applied to the odd-numbered line and the generation position of the TP signal TP-E applied to the even-numbered line are controlled to be generated at predetermined intervals. Thus, the position of the load signal TP, which is a signal for latching data and for driving a data line, can be adjusted. As a result, in the two-line inversion driving method or the n-line inversion driving method currently applied, it is possible to eliminate the influence of the image quality due to the difference in the charging degree.

As described above, according to the second embodiment of the present invention, the image quality deterioration phenomenon generated when the line is inverted by changing the generation period of the CPV which is the input signal of the gate driver and the generation period of the output enable signal OE for each line. Can compensate.

Next, a description will be given of a liquid crystal display capable of compensating for a deterioration in image quality caused by line reversal by maximizing the filling rate of the pixel electrode through the third and fourth embodiments of the present invention.

Fig. 9 is a waveform diagram for explaining general n-line inversion, and in particular, four-line inversion driving will be described as an example.

Referring to FIG. 9, the gate signal is the same as the dot inversion, and the data signal is repeatedly displayed with four positive (+) signals and four negative (-) signals. However, the most problematic in the above structure is the distortion of the data signal.

In terms of the charging time, the time when one signal is continuously applied to the data line is α, which is the same for all pixels, and the time when the gate is turned on is β = (α-OE).

In the four-line inversion driving, data distortions other than the data signal distortion at the position where the data signal is inverted can be ignored. This is because, in most pixels, the signals of the upper and lower pixels enter almost the same signal.

In general, the gate signal applied to the previous scan line is blocked through the OE signal between two adjacent gate signals, and then the gate signal is applied to the current scan line.

The reason why a predetermined time is provided between the gate signals is that if the gate signal is turned on before the data signal is inverted in the dot inversion driving, a signal of the opposite sign is applied to the pixel and thus does not help to display a desired image.

In addition, another reason for allowing a predetermined time between gate signals is that on / off occurs simultaneously between two adjacent gate signals.

However, in the n-line inversion driving method, preferably in a two-line or more inversion driving method, other gate signals overlap if the gate signal does not overlap only at the moment when the data signal of the first polarity is changed to the data signal of the second polarity. Even if the gate signal is applied, it is not a problem for displaying an image, but rather the charging rate can be increased.

With this in mind, the third and fourth embodiments of the present invention are disclosed.                     

FIG. 10 is a waveform diagram illustrating an output signal of a gate driver for driving a liquid crystal display according to a third exemplary embodiment of the present invention. In particular, four-line inversion driving will be described as an example.

3 and 10, the gate signal G1 of the first gate line to which data of the same polarity is applied is controlled to output a wider pulse width than the normal gate signal, and the remaining gate lines, that is, the second to fourth gate lines. The gate signals G2, G3, and G4 control to output a narrower pulse width than the normal gate signal.

More specifically, assuming that the pulse width of the normal gate signal is α and the compensation pulse width is γ, the width of the data signal applied to the first gate line is within α + 3γ and is applied to the second to fourth gate lines. Preferably, the widths of the data signals to be used are alpha-gamma.

In addition, the pulse width of the gate signal G1 applied to the first gate line is α + 3γ-OE, and the pulse widths of the gate signals G2, G3, G4 applied to the second to fourth gate lines are respectively α-γ. .

In particular, the timing controller according to the third embodiment of the present invention does not output the OE signal to the gate driver when outputting the gate signals corresponding to the data signal whose polarity is not changed so that the corresponding data voltage is sufficient. It is desirable to control the pixel electrode to be charged.

In addition, the timing controller according to the third embodiment of the present invention outputs a predetermined OE signal to the gate driver between the gate signals corresponding to the data signal whose polarity is changed so that the data signal of the first polarity is the data signal of the second polarity. It is preferable to control so as not to overlap at the moment when it changes to.

Next, FIG. 11 and FIG. 12 attaching examples for generating the gate signal of FIG. 10 will be described in more detail.

FIG. 11 is a waveform diagram illustrating an example of the implementation of FIG. 10.

Referring to FIGS. 3, 10, and 11, first, in order to make the first timing signal applied to the data driver 200, the position of the TP signal may be adjusted. Here, the period of the TP is a 4-line one cycle.

In order to use this method, the inactive section of the data enable signal DE provided by the timing controller 100 should be wide. That is, the above-described method may be applied when a section in which the inactive section of DE is doubled satisfies a condition greater than 3λ.

In general, in the liquid crystal display having the SXGA level resolution, the inactive section of DE is about 3.5 ms, so the above method may be applied when the level is 3λ <7 ms. That is, the above-described method is suitable to increase the pulse width of the portion where the polarity of the data signal is changed to within 7 dB compared with the existing one.

Meanwhile, in order to generate the second timing signal applied to the gate driver 300, the gate selection signal CPV is formed at the same time as a long period and a short period within a 4-line period.                     

Of course, the CPV period at the position where the gate signal corresponding to the first gate line is changed in the data line of the same polarity is lengthened. In this case, the OE signal for blocking the gate signal may not be present. However, even if present, the 4-line may be set as one cycle.

FIG. 12 is a waveform diagram illustrating another example of the implementation of FIG. 10.

3 and 12, first, periodically generate a DE signal provided from an external graphic controller (not shown), that is, a distance between DE inactive sections in order to generate a first timing signal applied to the data driver 200. You need to create it differently.

To this end, it is preferable to provide a predetermined line memory in the timing controller 100 to forcibly shift data by an appropriate time interval.

Advantage of FIG. 12 can be set freely the size of λ. In other words, it is possible to increase the length of the first signal whose data is changed as much as desired.

On the other hand, since the generation of the second timing signal applied to the gate driver 300 is the same as the generation of the second timing signal applied to the gate driver mentioned in FIG. 11, the description thereof is omitted.

FIG. 13 is a waveform diagram illustrating an output signal of a gate driver for driving a liquid crystal display according to a fourth embodiment of the present invention. In particular, four-line inversion driving is described as an example.

3 and 13, a gate signal existing in a data signal of the same polarity is generated to overlap with another adjacent gate signal. That is, after generating the first gate signal corresponding to the data signal of the same polarity, the second gate signal is generated before being changed to the off level, and the third gate signal is generated before the second gate signal is changed to the off level. To overlap with other gate signals.

Of course, it is preferable to generate adjacent gate signals to be spaced apart by a predetermined distance in data signals having different polarities. Here, it is preferable that the OE signal does not exist in the data signal of the same polarity, and the OE signal preferably exists between the data signals of different polarity.

As shown, the pulse width of the first gate signal present in the data signal of the same polarity is α + 3γ-OE, the pulse width of the second gate signal is α + Δt1, the pulse width of the third gate signal is α + Δt2, and the fourth The pulse width of the gate signal is α + Δt3, so that the first gate signal whose polarity of the data signal is inverted has a pulse width which is wider than the pulse width of the normal gate signal. It has a pulse width that overlaps with the gate signal. Here, (DELTA) t1-(DELTA) t3 may be the same and may differ.

Next, FIG. 14 will be described in more detail with reference to the accompanying examples for generating the gate signal of FIG. 13.

14 is a waveform diagram illustrating an example of the implementation of FIG. 13.

3, 13, and 14, first, since the generation of the first timing signal applied to the data driver 200 is the same as in FIG. 11 described above, detailed description thereof will be omitted.

Meanwhile, generation of the second timing signal applied to the gate driver 300 is as follows. That is, the vertical synchronization start signal STV is lengthened so that the gate signal width overlaps, and the duty position of the gate selection signal CPV is adjusted by the 4-line period to adjust the generation position of the gate signal.

The OE1 outputs three kinds of OE signals to block the gate signal, where OE1 is the first, fourth, seventh, and tenth gate lines, OE2 is the second, fifth, eighth, and eleventh gate lines, and OE3. Is to adjust the gate lines of the third, sixth, ninth, and twelfth. At this time, the OE signals OE1, OE2, and OE3 are each repeated in 12-line pixel periods, where OE2 is a signal shifted by OE1 by four lines, and OE3 is a signal shifted by four lines from OE2.

On the other hand, the center portion of Figure 14 is a waveform diagram for calculating the signal applied to each OE. That is, the figure shows the gate lines controlled by the respective OE signals OE1, OE2, and OE3 at once, and the hatched portions are the gate signals to be blocked using the OE signal.

This part is again shown in the lower part of Figure 14 by separate OE signals (OE1, OE2, OE3).

As such, when the OE is separated into three types and a signal is applied, a gate signal according to the fourth embodiment of the present invention can be obtained.

Although the third and fourth embodiments of the present invention described above have been described based on the 4-line inversion driving method, it is obvious that the present invention can be applied to the liquid crystal display device using the n-line inversion driving method.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the present invention, the gate on / off signal applied to the current scan line having a different polarity than the previous scan line is controlled to have a wider width, and the current scan line having the same polarity as the immediately previous scan line. By controlling the gate on / off signal to have a narrower width, it is possible to solve a problem of a horizontal line defect caused by a difference in charging characteristics between scan lines or a long charging time.

In addition, according to the present invention, when displaying an image using the n-line inversion driving method, the pulse width of the first data signal in the same polarity section is extended than the pulse width in the normal driving, the pulse width of the remaining data signal is normal The charging rate of the pixel electrode can be maximized by reducing the pulse width at the time of driving and adjusting the pulse width so that the gate signal does not overlap only when the data signal of the first polarity is changed to the data signal of the second polarity.

Further, according to the present invention, when displaying an image by using the n-line inversion driving method, the pulse width of the first data signal of the same polarity section is extended than the pulse width of the normal driving, the pulse width of the remaining data signal is normal The first gate signal is generated within the first data signal generation period, the remaining gate signals are overlapped with the gate signal applied to the previous gate line, and the data signal of the first polarity is reduced. The charging rate of the pixel electrode can be maximized by adjusting the pulse width so that the gate signal does not overlap only when the polarity data signal is changed.

Claims (16)

delete delete A matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a switching element formed in an area surrounded by the gate lines and data lines and connected to the gate lines and data lines, respectively A liquid crystal display device comprising a plurality of pixels arranged in A timing controller configured to output RGB input data input from an external graphic controller, a first timing signal having a variable pulse period, and a second timing signal according to an inverted polarity of each frame; A data driver for differently loading a time for writing each data line according to the first timing signal when the RGB input data is loaded, and converting the loaded RGB input data to output the data line; And A gate driver for outputting a plurality of gate signals for operating on / off of the switching element according to the second timing signal Including; The first timing signal controls to extend the pulse width of the first data signal to the pulse width of the normal data signal and to reduce the pulse width of the remaining data signal to the pulse width of the normal data signal in the data period of the same polarity. A liquid crystal display device characterized by the above-mentioned. The method of claim 3, wherein the second timing signal, Within the data interval of the same polarity Generating a first gate signal to be within a generation range of the first data signal, And generate at least one remaining gate signal to be adjacent to the gate signal applied to the previous gate line. The method of claim 4, wherein the timing controller, When outputting a gate signal corresponding to a data signal of which the polarity is unchanged, the output enable signal OE for applying to the gate driver is blocked to control the data voltage to be sufficiently charged in the pixel electrode. Outputting the output enable signal to the gate driver when outputting a gate signal corresponding to a data signal whose polarity is changed to block an overlap generated when a data signal of a first polarity is changed to a data signal of a second polarity; A liquid crystal display device, characterized in that. The method of claim 3, wherein the second timing signal, Within the data interval of the same polarity Generating a first gate signal to be within a generation range of the first data signal, And generate at least one remaining gate signal to overlap the gate signal applied to the previous gate line. The method of claim 6, wherein the second timing signal, When outputting a gate signal corresponding to a data signal whose polarity is changed, an output enable signal applied to the gate driver is applied to block an overlap occurring when the data signal of the first polarity is changed to the data signal of the second polarity. Liquid crystal display device comprising a. A matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a switching element formed in an area surrounded by the gate lines and data lines and connected to the gate lines and data lines, respectively In a driving method of a liquid crystal display device comprising a plurality of pixels arranged in (a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof; (b) outputting a TP signal having a controlled generation position within an N-line inversion period based on the DE signal; (c) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line; (d) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the data enable signal; And (e) based on the CPV, adjacent to a first gate signal having a wider pulse width than that in normal driving and a gate signal applied to a previous gate line so as to be within a generation range of the first data signal in a data period of the same polarity; Supplying the remaining gate signal to the gate line Method of driving a liquid crystal display comprising a. The method of claim 8, wherein the loading of the RGB input data is loaded based on a TP signal. The method of claim 8, wherein step (e) And outputting an OE signal having a generation period of an N line inversion period to supply the remaining gate signal adjacent to the gate signal applied to the previous gate line to the gate line. Way. A matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a switching element formed in an area surrounded by the gate lines and data lines and connected to the gate lines and data lines, respectively In a driving method of a liquid crystal display device comprising a plurality of pixels arranged in (a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof; periodically adjusting the distance of the inactive section of the DE signal periodically; (c) outputting a TP signal having a regulated generation position within an N-line inversion period based on the adjusted DE signal; (d) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line; (e) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the DE signal; And (f) based on the CPV, adjacent to the first gate signal having a wider pulse width than that in normal driving and the gate signal applied to the previous gate line so as to be within the generation range of the first data signal in the data period of the same polarity; Supplying the remaining gate signal to the gate line Method of driving a liquid crystal display comprising a. The method of claim 11, wherein step (b) comprises: And a distance of the inactive section of the DE signal is periodically adjusted differently using a line memory. The method of claim 11, wherein step (f) comprises: And outputting an OE signal having an occurrence period of an N line inversion period to supply the remaining gate signal adjacent to the gate signal applied to the previous gate line to the gate line. Way. A matrix form having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a switching element formed in an area surrounded by the gate lines and data lines and connected to the gate lines and data lines, respectively In a driving method of a liquid crystal display device comprising a plurality of pixels arranged in (a) receiving a control signal including RGB input data input from the outside and a DE signal for display thereof; (c) outputting a TP signal having an adjusted generation position within an N-line inversion period based on the DE signal; (d) loading the RGB input data based on the TP signal, and supplying a plurality of data signals obtained by converting the loaded RGB input data to the data line; (e) outputting a CPV having a wide generation period and a CPV having a narrow generation period within an N-line inversion period based on the DE signal; And (f) On the basis of the CPV, the first gate signal having a wider pulse width than that in the normal driving and the gate signal applied to the previous gate line so as to be within the generation range of the first data signal in the data period of the same polarity; Supplying the remaining gate signal to the gate line Method of driving a liquid crystal display comprising a. 15. The method of claim 14, wherein step (f) comprises: And outputting (N-1) OE signals having different generation periods to supply the remaining gate signals overlapping with the gate signals applied to the previous gate lines to the gate lines. Driving method of liquid crystal display device. 16. The method of claim 15, wherein in the case of a four-line inversion period, the OE signal consists of first to third OE signals, and the second OE signal is shifted four lines by the first OE signal and the third OE Is shifted by 4 lines from the second OE signal.

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