KR100806087B1 - Nonvolatile memory and manufacturing method thereof - Google Patents

Abstract

A non-volatile memory and a manufacturing method thereof are provided to ensure a wide memory margin and improve a characteristic of erasing operation and storage time. A non-volatile memory includes a substrate(100) and a gate structure. The gate structure has a tunneling dielectric layer(201) formed on the substrate, a first floating gate(202) formed on the tunneling dielectric layer, an interfacial dielectric layer(203) formed on the first floating gate, a second floating gate(204) formed on the facial dielectric layer and having a work function higher than the first floating gate, a control dielectric layer(205) formed on the second floating gate and a gate electrode(206) formed on the control dielectric layer.

Description

Nonvolatile Memory and Manufacturing Method Thereof {NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF}

1 is a diagram showing an example of a conventional nonvolatile memory.

2 illustrates a nonvolatile memory according to an embodiment of the present invention.

3 is a view illustrating a comparison of memory characteristics when a conventional nonvolatile memory and a nonvolatile memory according to an embodiment of the present invention are operated with 2 bits.

4 to 6 show energy band diagrams according to the work function level of the floating gate.

7 is a diagram illustrating a method of manufacturing a nonvolatile memory according to the first embodiment of the present invention.

8 illustrates a method of manufacturing a nonvolatile memory according to the second embodiment of the present invention.

***** Explanation of symbols for the main parts of the drawing *****

100: substrate

101: source area

102: drain region

201: tunneling dielectric film

202: first floating gate

203: interfacial dielectric film

204: second floating gate

205: control dielectric film

206: gate electrode

210: gate structure

The present invention relates to a nonvolatile memory and a method of manufacturing the same.

In general, a semiconductor memory is a volatile memory that loses data over time, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and a state in which data can be maintained once inputted. It is largely divided into non-volatile memory.

Non-volatile memory has a characteristic that once the data is input, it can be maintained over time. Recently, there is an increasing demand for flash memory that can input and output data electrically.

1 is a view showing an example of a conventional nonvolatile memory.

Referring to FIG. 1, a source region 101 and a drain region 102 in which impurities are injected into a semiconductor substrate 100 are formed. When the semiconductor substrate 100 is p-type, n-type impurities are implanted into the source region 101 and the drain region 102. The channel region 103 is set in the semiconductor substrate 100 between the source region 101 and the drain region 102.

The gate stack 110 is formed on the channel region 103.

The gate stack 110 has a structure in which the tunneling layer 104, the charge storage layer 105, the blocking layer 106, and the gate electrode 107 formed of a conductive material are sequentially formed.

The tunneling layer 104 is in contact with the source region 101 and the drain region 102 at the bottom thereof, and the charge storage layer 105 is nanocrystallized to store the charge passing through the tunneling layer 104 ( trap site).

The information recording of the nonvolatile memory is performed by applying a voltage to the gate electrode so that electrons passing through the tunneling layer 104 are trapped at the trap site of the charge storage layer 105.

The blocking layer 106 blocks electrons from escaping to the gate electrode 107 in the course of being trapped at the trap site of the charge storage layer 105, and the charge of the gate electrode 107 is injected into the charge storage layer 105. It serves to prevent you from becoming.

Unlike a metal oxide silicon (MOS) transistor in which a gate stack is formed of a gate insulating layer and a gate electrode layer, the threshold voltage (Vth) of the conventional nonvolatile memory shown in FIG. 1 is the charge storage layer 105. There is a characteristic that varies depending on whether an electron is trapped and when it is not trapped, and a conventional nonvolatile memory expresses bit information using this characteristic.

However, the conventional nonvolatile memory of this structure has a problem that it is difficult to implement multiple bits in a single device.

In addition, even when multiple bits are implemented using a single device, program margins are reduced, thereby reducing the reliability of operation of the memory device.

An object of the present invention to solve these problems is to provide a multi-bit nonvolatile memory capable of stable operation and a method of manufacturing the same.

A nonvolatile memory according to the present invention for achieving the above technical problem includes a substrate and a gate structure formed on the substrate, the gate structure including two or more floating gates having different work functions.

Preferably, the floating gate is nanocrystallized.

The gate structure includes a tunneling dielectric film formed on the substrate, a first floating gate formed on the tunneling dielectric film, an interfacial dielectric film formed on the first floating gate, a second floating gate formed on the interface dielectric film, and It is preferable to include a control dielectric film formed on the second floating gate and a gate electrode formed on the control dielectric film.

Preferably, the floating gate is silicon or metal.

The work function of the second floating gate is preferably larger than the work function of the first floating gate.

The first floating gate is nanocrystallized silicon implanted with Group 5 impurities, and the second floating gate is nanocrystallized silicon implanted with Group 3 impurities.

The interfacial dielectric film may have a thickness of 1 nanometer or more and less than 3 nanometers.

The interfacial dielectric film may have a thickness of 3 nanometers or more and 10 nanometers or less.

A method of manufacturing a nonvolatile memory device according to the present invention includes forming a gate structure including two or more floating gates having different work functions on a substrate, and forming source and drain regions by injecting impurities into the substrate. .

It is preferable that the floating gate is silicon.

Preferably, the floating gate is a metal, and after forming the source and drain regions, a gate structure including the floating gate is formed.

Preferably, the floating gate is nanocrystallized.

The forming of the gate structure may include forming a tunneling dielectric layer on the substrate, forming a first floating gate on the tunneling dielectric layer, forming an interfacial dielectric layer on the first floating gate; And forming a second floating gate on the interface dielectric layer, forming a control dielectric layer on the second floating gate, and forming a gate electrode on the control dielectric layer.

The work function of the second floating gate is preferably larger than the work function of the first floating gate.

The first floating gate is nanocrystallized silicon implanted with Group 5 impurities, and the second floating gate is nanocrystallized silicon implanted with Group 3 impurities.

The interfacial dielectric film may have a thickness of 1 nanometer or more and less than 3 nanometers.

The interfacial dielectric film may have a thickness of 3 nanometers or more and 10 nanometers or less.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention;

2 illustrates a nonvolatile memory according to an embodiment of the present invention.

As shown in FIG. 2, a nonvolatile memory according to an embodiment of the present invention includes a substrate and a gate structure.

The substrate 100 may be formed by adopting silicon, silicon germanium, tensile silicon, tensile silicon germanium, or insulating layer embedded silicon (SOI). The source region 101 and the drain region 102 including the impurity dopant are formed in the substrate 100. A channel region 103 is formed between the source region 101 and the drain region 102 of the substrate 100.

The gate structure 210 is formed on the channel region 103 in contact with the source region 101 and the drain region 102. The gate structure 210 includes two or more floating gates 202 and 204 with different work functions. The gate structure 210 includes a tunneling dielectric film 201, a first floating gate 202, an interfacial dielectric film 203, a second floating gate 204, a control dielectric film 205, and a gate electrode 206 sequentially stacked. Structure.

The tunneling dielectric layer 201 may be formed of an oxide. For example, SiO ₂ , Al ₂ O ₃ , MgO, SrO, SiN, BaO, TiO, Si ₃ N ₄ , Ta ₂ O ₅ , BaTiO ₃ , BaZrO, ZrO ₂ , HfO ₂ , Al ₂ O ₃ , Y ₂ It may be formed including at least one of O ₃ , ZrSiO, HfSiO or LaAlO ₃ .

The first floating gate 202 and the second floating gate 204 serve as a charge storage layer in an operation of the nonvolatile memory. The first floating gate 202 and the second floating gate 204 are nano-crystallized silicon or metal, and the work function of the second floating gate 204 is greater than the work function of the first floating gate 202. It is preferable.

The interfacial dielectric film 203 is formed between the first floating gate 202 and the second floating gate 204, and the characteristics of the nonvolatile memory may be adjusted by adjusting the thickness of the interfacial dielectric film 203. For example, 1) If the nonvolatile memory having a high speed is to be implemented, the thickness of the interfacial dielectric film 203 is set to 1 nanometer or more and less than 3 nanometers so that direct tunneling prevails. 2) to realize a non-volatile memory having a long charge storage time, the thickness of the interfacial dielectric film 203 is set to 3 nanometers or more and 10 nanometers or less, Fowler-Nordheim By preserving (Fowler-Nordheim; FN) tunneling, the charge storage time of nonvolatile memory can be extended. In addition, the characteristics of the non-volatile memory may be controlled by adjusting the properties of the material of the interfacial dielectric layer 203. For example, 1) to implement a nonvolatile memory having a high speed, by adopting a dielectric material having a high dielectric constant and a low energy barrier as a constituent of the interfacial dielectric film 203, the speed of the nonvolatile memory is increased. And 2) to implement a nonvolatile memory having a long charge storage time, by adopting a dielectric material having a low dielectric constant and a high energy barrier as the constituent material of the interfacial dielectric film 203, the charge storage of the nonvolatile memory You can increase your time.

One example of specific information storage and erase operations in the nonvolatile memory according to an embodiment of the present invention will be described. The substrate 100 is a p-type case.

1) In order to store information, the source region 101 is grounded or a low voltage is applied to the source region 101 to apply the first voltage of the first level to the drain region 102, and the gate electrode 206 is applied. A positive voltage of a second level higher than the first level is applied to the second voltage. In this state, a channel of electrons is formed from the source region 101 to the drain region 102 and the electrons moving to the drain region 102 tunnel through the tunneling dielectric layer 201 by an electric field formed at the gate electrode 206. The first floating gate 202 is trapped, or the tunneling dielectric film 201, the first floating gate 202, and the interfacial dielectric film 203 are tunneled and stored in the second floating gate 204. Non-volatile memory according to an embodiment of the present invention has an effect that can record the amount of high-capacity because the site where the electron is stored is wider than the conventional non-volatile memory.

2) To erase the information, when the voltage of the gate electrode 206 is set to 0 volts (V), a high voltage is applied to the source region 101, and the drain region 102 is opened, electrons fall into the source region 101. It exits and the information in the memory is erased.

FIG. 3 is a diagram illustrating a comparison of memory characteristics when a conventional nonvolatile memory and a nonvolatile memory according to an embodiment of the present invention are operated with 2 bits.

Figure 3 (a) shows the memory characteristics when the conventional non-volatile memory is operated by two bits (bit), Figure 3 (b) shows a non-volatile memory 2 bits according to an embodiment of the present invention Memory characteristics when operated in (bit).

As shown in FIGS. 3A and 3B, a nonvolatile memory according to an embodiment of the present invention may include a double nanocrystal layer having a different work function, that is, a first floating gate ( By forming the 202 and the second floating gate 204, a 2-bit memory device having a wider program margin can be realized due to the doubled charge storage nodes, and the thickness of the interfacial dielectric film 203 can be adjusted. The charge storage time can be extended.

4 to 6 are diagrams showing energy band diagrams according to the work function level of the floating gate.

4 illustrates a case in which the work functions of the first floating gate 202 and the second floating gate 204 are the same, and the work function is Ec-E1. FIG. 5 shows the first floating gate 202 and the second floating gate. The work function of 204 is the same, and the work function is Ec-E2 higher than the case of FIG.

Compared to the case of FIG. 4, a wide memory margin and a long charge storage time can be obtained in the case of FIG. 5 forming a deep potential well. However, in FIG. 5, the efficiency of the erase operation is not good due to the high potential.

6 illustrates a case where the work function Ec-E1 of the first floating gate 202 is smaller than the work function Ec-E2 of the second floating gate 204, and the work function ( Ec-E1 is as low as ΔE (E1-E2) compared to the work function Ec-E2 of the second floating gate 204. In this case, since the charges stored in the second floating gate 204 during the erase operation are erased to the substrate at a lower voltage and a shorter time than in the case of FIG. 5 with the aid of the first floating gate 202 operating as a buffer. The erase speed is faster.

As described above in detail, according to the non-volatile memory according to an embodiment of the present invention, a wide memory margin, a long charge storage time, and a fast erase characteristic can be secured.

The nonvolatile memory structure according to an embodiment of the present invention may be applied to a conventional two-dimensional planar memory device, and may be applied to a single device of any structure such as a three-dimensional multi-gate device such as a FinFET or a U-FET (glooved MOSFET). By applying, the characteristics of the nonvolatile memory can be improved.

7 is a diagram illustrating a nonvolatile memory manufacturing method according to a first embodiment of the present invention.

As shown in FIG. 7, in the nonvolatile memory manufacturing method according to the first embodiment of the present invention, a tunneling dielectric film forming step 710, a first floating gate forming step 720, and an interfacial dielectric film forming step 730 are performed. And a second floating gate forming step 740, a control dielectric film forming step 750, a gate electrode forming step 760, and a source and drain region forming step 770.

Hereinafter, a method of manufacturing a nonvolatile memory according to a first embodiment of the present invention will be described with reference to FIGS. 2 and 7.

First, the tunneling dielectric layer 201 is formed on the substrate 100. The substrate 100 may be formed by adopting silicon, silicon germanium, tensile silicon, tensile silicon germanium, or insulating layer embedded silicon (SOI). The tunneling dielectric layer 201 may be formed of an oxide. For example, SiO ₂ , Al ₂ O ₃ , MgO, SrO, SiN, BaO, TiO, Si ₃ N ₄ , Ta ₂ O ₅ , BaTiO ₃ , BaZrO, ZrO ₂ , HfO ₂ , Al ₂ O ₃ , Y ₂ It may be formed including at least one of O ₃ , ZrSiO, HfSiO or LaAlO ₃ .

Next, a first floating gate 202 is formed on the tunneling dielectric film 201, an interfacial dielectric film 203 is formed on the first floating gate 202, and a second floating gate is formed on the interfacial dielectric film 203. 204 is formed. The first floating gate 202 and the second floating gate 204 serve as a charge storage layer in an operation of the nonvolatile memory. The first floating gate 202 and the second floating gate 204 are nano-crystallized silicon, and the work function of the second floating gate 204 is greater than the work function of the first floating gate 202. desirable. The interfacial dielectric film 203 is formed between the first floating gate 202 and the second floating gate 204, and the characteristics of the nonvolatile memory may be adjusted by adjusting the thickness of the interfacial dielectric film 203. For example, 1) If the nonvolatile memory having a high speed is to be implemented, the thickness of the interfacial dielectric film 203 is set to 1 nanometer or more and less than 3 nanometers so that direct tunneling prevails. 2) to realize a non-volatile memory having a long charge storage time, the thickness of the interfacial dielectric film 203 is set to 3 nanometers or more and 10 nanometers or less, Fowler-Nordheim By preserving (Fowler-Nordheim; FN) tunneling, the charge storage time of nonvolatile memory can be extended. In addition, the characteristics of the non-volatile memory may be controlled by adjusting the properties of the material of the interfacial dielectric layer 203. For example, 1) to implement a nonvolatile memory having a high speed, by adopting a dielectric material having a high dielectric constant and a low energy barrier as a constituent of the interfacial dielectric film 203, the speed of the nonvolatile memory is increased. And 2) to implement a nonvolatile memory having a long charge storage time, by adopting a dielectric material having a low dielectric constant and a high energy barrier as the constituent material of the interfacial dielectric film 203, the charge storage of the nonvolatile memory You can increase your time.

Next, the control dielectric film 205 is formed on the second floating gate 204, and the conductive gate electrode 206 is formed on the control dielectric film 205.

Next, the gate structure is etched by etching both sides of the tunneling dielectric layer 201, the first floating gate 202, the interfacial dielectric layer 203, the second floating gate 204, the control dielectric layer 205, and the gate electrode 206. Complete 210. As a result, both surfaces of the substrate 100 are exposed.

Next, source and drain regions 101 and 102 are formed. The source region 101 and the drain 102 region are formed by doping impurity dopants on both surfaces of the exposed substrate 21, and the source region 101 and the drain region 102 are activated by heat treatment. A nonvolatile memory according to an embodiment of the present invention is completed.

8 is a diagram illustrating a nonvolatile memory manufacturing method according to a second embodiment of the present invention.

As shown in FIG. 8, in the nonvolatile memory manufacturing method according to the second embodiment of the present invention, a source and drain region forming step 810, a tunneling dielectric layer forming step 820, and a first floating gate forming step 830 are provided. ), An interfacial dielectric film forming step 840, a second floating gate forming step 850, a control dielectric film forming step 860, and a gate electrode forming step 870.

According to the nonvolatile memory manufacturing method according to the second embodiment of the present invention, source and drain regions 101 and 102 are formed before the gate structure 210 is formed. As described above, the reason for forming the source and drain regions 101 and 102 before forming the gate structure 210 is to consider a difference in melting points when the first and second floating gates are metal.

In the nonvolatile memory manufacturing method according to the second embodiment of the present invention, the source and drain regions 101 and 102 are formed before the gate structure 210 is formed. Since the method is the same as the method of manufacturing the nonvolatile memory according to the first embodiment, a detailed description of the method of manufacturing the nonvolatile memory according to the second embodiment of the present invention will be described in detail. Replace with a description.

As described above, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described in detail above, according to the present invention, the thickness of the interfacial dielectric film between the double nanocrystal layers may be adjusted according to device characteristics, thereby optimizing the characteristics of the nonvolatile memory device.

In addition, by using double nanocrystal layers having different work functions as floating gates, it is possible to secure a wider memory margin and to improve storage time and characteristics in an erase operation.

In addition, the manufacturing process of the nonvolatile memory device is simple and the reproducibility is high, there is an effect that can be stably high integration of the memory.

Claims (17)

Board; And A tunneling dielectric film formed on the substrate, a first floating gate formed on the tunneling dielectric film, an interfacial dielectric film formed on the first floating gate, and a work function formed on the interfacial dielectric film and larger than a work function of the first floating gate. A gate structure including a second floating gate having a control dielectric layer, a control dielectric layer formed on the second floating gate, and a gate electrode formed on the control dielectric layer; Non-volatile memory comprising a. According to claim 1, And the first and second floating gates are nano-crystallized. delete According to claim 1, And the floating gate is silicon. delete According to claim 1, The first floating gate is nano-crystallized silicon implanted with Group 5 impurities, And the second floating gate is nanocrystallized silicon implanted with group III impurities. According to claim 1, The thickness of the interfacial dielectric film is more than 1 nanometer and less than 3 nanometers. According to claim 1, And a thickness of the interfacial dielectric layer is greater than or equal to 3 nanometers and less than or equal to 10 nanometers. Forming a tunneling dielectric film on a substrate, forming a first floating gate on the tunneling dielectric film, forming an interfacial dielectric film on the first floating gate, and forming one of the first floating gate on the interface dielectric film Forming a gate structure comprising forming a second floating gate having a work function greater than a function, forming a control dielectric layer on the second floating gate, and forming a gate electrode on the control dielectric layer ; And Implanting impurities into the substrate to form source and drain regions; Non-volatile memory manufacturing method comprising a. The method of claim 9, And the first and second floating gates are silicon. delete The method of claim 9, And the first and second floating gates are nanocrystallized. delete delete The method of claim 9, The first floating gate is nano-crystallized silicon implanted with Group 5 impurities, And the second floating gate is nanocrystallized silicon implanted with group III impurities. The method of claim 9, The interfacial dielectric film has a thickness of 1 nanometer or more and less than 3 nanometers. The method of claim 9, And a thickness of the interfacial dielectric layer is greater than or equal to 3 nanometers and less than or equal to 10 nanometers.

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