KR100796796B1 - A thin film transistor substrate of using insulating layers having law dielectric constant and a method of manufacturing the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate using a low dielectric constant insulating film and a method of manufacturing the same. A gate wiring is formed on an insulating substrate, a data wiring insulated from and intersecting with the gate wiring is formed, and a thin film transistor connected to the gate wiring and the data wiring is formed. A protective film made of a-Si: C: O film or a-Si: O: F film deposited by PECVD is formed on the thin film transistor, and an organic insulating film made of photoresist, which is used as an etch mask at the time of contact hole, is formed on the protective film. And a pixel electrode connected to the thin film transistor is formed on the organic insulating film. In this case, by leaving the organic insulating film used as an etching mask as it is, the manufacturing process can be simplified and the processing time can be shortened. The organic insulating film is spaced apart from the pixel electrode and the data wiring together with the low dielectric constant CVD film, thereby making the pixel electrode sufficiently wide. The parasitic capacitance between the pixel electrode and the data wiring does not matter much even when formed to overlap with the data wiring. Therefore, the aperture ratio can be maximized.

Thin film transistor substrate, low dielectric constant CVD film, high opening ratio, parasitic capacitance

Description

A thin film transistor substrate using a low dielectric constant insulating film and a method of manufacturing the same {A THIN FILM TRANSISTOR SUBSTRATE OF USING INSULATING LAYERS HAVING LAW DIELECTRIC CONSTANT AND A METHOD OF MANUFACTURING THE SAME}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A.

4B is a cross sectional view taken along the line IVb-IVb ′ in FIG. 4A showing the next step of FIG. 3B.

FIG. 5B is a cross sectional view taken along the line Vb-Vb ′ in FIG. 5A and showing the next step in FIG. 4B.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and showing the next step of FIG. 6.

7 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 and 9 are cross-sectional views taken along the lines VII-VII 'and IX-IX' of FIG. 7, respectively.

10A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention.

10B and 10C are cross-sectional views taken along lines Xb-Xb 'and Xc-Xc', respectively, in FIG. 10A.

11A and 11B are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' in Fig. 10A, respectively, and are cross-sectional views in the next steps of Figs. 10B and 10C.

12A is a layout view of a thin film transistor substrate in the next steps of FIGS. 11A and 11B.

12B and 12C are sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc', respectively, in FIG. 12A.

13A, 14A, 15A and 13B, 14B, and 15B are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc', respectively, in FIG. 12A, illustrating the following steps in the order of the process.

16A and 16B are cross-sectional views of the thin film transistor substrate in the next steps of FIGS. 15A and 15B.

17A is a layout view of a thin film transistor substrate in the next step of FIGS. 16A and 16B.

17B and 17C are sectional views taken along lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A.

※ Explanation of code about main part of drawing ※

10: insulation board

22: gate line

24: gate pad

26: gate electrode

30: gate insulating film

40: semiconductor layer

55, 56: ohmic contact layer

62: data line

65 source electrode

66: drain electrode

70: protective film (CVD film)

81: organic insulating film

82: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate using a low dielectric constant insulating film capable of increasing an aperture ratio and a transmittance.

Generally, a thin film transistor substrate is used as a circuit board for driving each pixel independently in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, and is connected to a thin film transistor and a thin film transistor connected to the gate line and the data line. And a pixel electrode, a gate insulating film covering and insulating the gate wiring, and a protective film covering and insulating the thin film transistor and the data wiring. The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate wiring, a source electrode and a drain electrode, which are part of a data wiring, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

As a representative device using the above-mentioned thin film transistor substrate, there is a liquid crystal display device. As the liquid crystal display device is gradually enlarged in size and high in size, a signal distortion problem caused by an increase in various parasitic capacitances has emerged as an urgent problem. .

In addition, the need for increasing the aperture ratio is increasing due to the reduction in power consumption in the notebook computer and the need for improving the luminance to increase the viewing distance in the liquid crystal display for TVs. By the way, in order to increase the aperture ratio, it is necessary to form the pixel electrode so as to overlap the data line, but in this case, the parasitic capacitance between the pixel electrode and the data line increases. In order to solve the problems caused by the parasitic capacitance increase, a sufficient vertical separation between the pixel electrode and the data line should be secured. In order to secure the vertical separation, a protective film is mainly formed of an organic insulating layer.

However, the organic insulating film that has been used for ensuring vertical separation has the following disadvantages. First of all, the material cost is expensive, and in particular, the amount lost during spin coating is high, which encourages an increase in the material cost. Next, the organic insulating layer lacks heat resistance and thus, subsequent processes are not only limited, but also high frequency of occurrence of impurity particles due to aggregation of materials. In addition, the adhesion between the upper layer and the lower layer is weak, and the etching error is very large when forming the pixel electrode formed on the passivation layer.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate having high opening ratio and no parasitic capacitance problem.

A thin film transistor substrate for achieving the above object,

Insulating substrate;

A first signal line formed on the insulating substrate;

A first insulating film formed on the first signal line;

A second signal line formed on the first insulating film and crossing the first signal line;                     

A thin film transistor connected to the first signal line and the second signal line;

A second insulating film which is a low dielectric constant CVD film and is formed on the thin film transistor and has a first contact hole for exposing a predetermined electrode of the thin film transistor;

A third insulating film formed on the second insulating film and having a second contact hole made of an organic insulating material and exposing a predetermined electrode of the thin film transistor through the first contact hole; And

A pixel electrode formed on the third insulating layer and connected to a predetermined electrode of the thin film transistor through the first and second contact holes;

Characterized in that it comprises a.

Method for manufacturing a thin film transistor substrate according to another feature of the present invention,

Forming a gate line on the insulating substrate, the gate line including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line;

Forming a gate insulating film;

Forming a semiconductor layer;

Stacking and patterning a conductive material to cross the gate line, a data pad connected to the data line, a source electrode connected to the data line and adjacent to the gate electrode, and opposite to the source electrode with respect to the gate electrode. Forming a data line including a drain electrode positioned at the second electrode;

Depositing a low dielectric constant CVD film to form a protective film;                     

Forming a contact hole for exposing the gate pad, the data pad, and the drain electrode by patterning the passivation layer together with the gate insulating layer using a photosensitive organic insulating layer as an etching mask; And

Stacking and patterning a transparent conductive layer on the photosensitive organic insulating layer to form an auxiliary gate pad, an auxiliary data pad, and a pixel electrode respectively connected to the gate pad, the data pad, and the drain electrode through the contact hole;

Characterized in that it comprises a.

Hereinafter, a thin film transistor substrate using a low dielectric constant insulating film and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor substrate shown in FIG.

1 and 2, the first gate wiring layers 221, 241, and 261 formed of chromium (Cr) or molybdenum (Mo) alloy, and the like on the insulating substrate 10, and aluminum (Al) or silver (Ag) alloy, etc. A gate wiring formed of a double layer of second gate wiring layers 222, 242, and 262 is formed. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.                     

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, the first data wiring layers 621, 651, 661, and 681 made of Cr or Mo alloy, etc., and the second data wiring layers 622 made of Al or Ag alloy, etc. Data wirings 62, 65, 66, and 68 formed of double layers of 652, 662, and 682 are formed.

The data wires 62, 65, 66, and 68 are formed in the vertical direction and intersect the gate line 22 to define a pixel and the data line 62, which is a branch of the data line 62, of the ohmic contact layer 54. It is connected to one end of the source electrode 65 and the data line 62 extending to the upper part, and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. ) And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65.

The a-Si: C: O film or a-Si: O: deposited by the plasma enhanced chemical vapor deposition (PECVD) method on the data lines 62, 65, 66, 68 and the semiconductor layer 40 which is not covered by these. A protective film 70 made of an F film (low dielectric constant CVD film) is formed. At this time, the a-Si: C: O film and the a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (dielectric constant of 2 to 4). ), The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. In addition, it is excellent in adhesiveness and step coverage with other films, and because it is an inorganic CVD film, heat resistance is superior to that of an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method are 4 to 10 times faster than the silicon nitride film by the deposition rate or the etching rate. It is also very advantageous in terms of time.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the data pad 68, respectively. The contact hole 74 exposing the gate pad 24 together with the gate insulating layer 30 is formed. Is formed. In this case, the contact holes 74 and 78 exposing the pads 24 and 68 may be formed in various shapes having an angle or a circular shape, and the area thereof does not exceed 2 mm × 60 μm, preferably 0.5 mm × 15 μm or more. Do.

In addition, when the contact holes 74, 76, and 78 are formed as described above, the photosensitive organic insulating layer 81 used as an etching mask is left without being removed in the photolithography process, thereby simplifying the manufacturing process and shortening the process time. In addition, since the organic insulating film 81 spaces the pixel electrode and the data wiring together with the low dielectric constant CVD film, the parasitic capacitance between the pixel electrode and the data wiring is greatly problematic even when the pixel electrode is formed wide enough to overlap the data wiring. It doesn't work. Therefore, the aperture ratio can be maximized.

The pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed on the organic insulating layer 81 through the contact hole 76. In addition, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 are formed on the organic insulating layer 81 through the contact holes 74 and 78, respectively. have. Here, the pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

The pixel electrode 82 is also formed to overlap the data line 62 to maximize the aperture ratio. In this way, even when the pixel electrode 82 is overlapped with the data line 62 to maximize the aperture ratio, the dielectric constant of the passivation layer 70 is low, so that the parasitic capacitance formed therebetween is small.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as illustrated in FIGS. 3A and 3B, the first gate wiring layers 221, 241, and 261 are laminated by depositing Cr or Mo alloy having excellent physicochemical properties on the substrate 10, and Al or the low resistance. Second gate wiring layers 222, 242, and 262 are stacked by depositing an Ag alloy and the like, and then patterned to form a horizontal gate including the gate line 22, the gate electrode 26, and the gate pad 24. Form the wiring.

In this case, when the first gate wiring layers 221, 241, and 261 are formed of Mo alloy and the second gate wiring layers 222, 242, and 262 are formed of Ag alloy, both of these layers are Ag alloy etchant. Etched by a mixture of phosphoric acid, nitric acid, acetic acid and deionized water. Therefore, the gate wirings 22, 24, and 26 of the double layer may be formed by one etching process.

In addition, since the etching ratio of the Ag alloy and the Mo alloy by the phosphoric acid, nitric acid, acetic acid, and ultrapure water mixture is larger than that of the Ag alloy, a taper angle of about 30 ° necessary for the gate wiring can be obtained.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is sequentially stacked, and the semiconductor The layer 40 and the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, as illustrated in FIGS. 5A to 5B, the first data wiring layers 651, 661, and 681 are deposited by depositing Cr or Mo alloys, and the second data wiring layer 652 by depositing Al or Ag alloys. , 662, and 682 are stacked, and then photo-etched to form a data line 62 intersecting the gate line 22 and a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26. The data line 62 is separated from the data pad 68 and the source electrode 64 connected to one end and includes a drain electrode 66 facing the source electrode 65 around the gate electrode 26. A data wiring is formed.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, the a-Si: C: O film or the a-Si: O: F film is grown by chemical vapor deposition (CVD) to form a protective film 70. In this case, in the case of a-Si: C: O film, SiH (CH ₃ ) ₃ , SiO ₂ (CH ₃ ) ₄ , (SiH) ₄ O ₄ (CH ₃ ) ₄ , and Si (C ₂ H ₅ O ₄ ) is used as a basic source, and is deposited while flowing a gas mixed with an oxidant such as N ₂ O or O ₂ and Ar or He. In the case of an a-Si: O: F film, vapor deposition is performed while flowing a gas containing O ₂ added to SiH ₄ , SiF _{4, or the} like. At this time, CF ₄ may be added as an auxiliary source of fluorine.

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process to form contact holes 74, 76, and 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68. Form. Here, the contact holes 74, 76, 78 may be formed in an angled shape or a circular shape, the area of the contact holes 74, 78 exposing the pads 24, 68 is greater than 2mm x 60㎛. It is preferable that it is 0.5 mm x 15 micrometers or more.

At this time, in forming the contact holes 74, 76, and 78 as described above, the photosensitive organic insulating layer 81 used as an etching mask is left without being removed in the photolithography process, thereby simplifying the manufacturing process and shortening the process time. In addition, since the organic insulating film 81 together with the low dielectric constant CVD film spaces the pixel electrode and the data wiring, the parasitic capacitance between the pixel electrode and the data wiring is large even when the pixel electrode is formed sufficiently wide to overlap the data wiring. It doesn't matter. Therefore, the aperture ratio can be maximized.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is deposited, photo-etched, and connected to the drain electrode 66 through the first contact hole 76, and the second and second electrodes. The auxiliary gate pad 86 and the auxiliary data pad 88 are formed to be connected to the gate pad 24 and the data pad 68 through the three contact holes 74 and 78, respectively. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO. This is to prevent the metal oxide film from being formed on the upper portions of the metal films 24, 66, and 68 exposed through the contact holes 74, 76, and 78.

As described above, by using a low dielectric constant insulating film (low dielectric constant CVD film) such as a-Si: C: O or a-Si: O: F formed by PECVD as the protective film 70, the parasitic capacitance problem and the aperture ratio are maximized. In addition, when the contact hole is formed by patterning the passivation layer 70 and the gate insulating layer 30, the photosensitive organic insulating layer 81 used as an etch mask in the photolithography process is left without being removed. In addition to simplifying and shortening the process time, the organic insulating film 81 together with the low dielectric constant CVD film separates the pixel electrode and the data wiring, so that the pixel electrode and the data are formed even if the pixel electrode is formed wide enough to overlap the data wiring. The parasitic capacitance between the wirings is not a big problem. Therefore, the aperture ratio can be maximized.

In addition, since the deposition and etching speed is high, process time can be reduced, and the organic insulating film used as an etching mask is left as it is, which is very advantageous in terms of process time. This will be described in detail with reference to the accompanying drawings.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9.

FIG. 7 is a layout view of a thin film transistor substrate for a liquid crystal display device according to a second exemplary embodiment of the present invention, and FIGS. 8 and 9 are lines VIII-VIII 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. The cross section for

First, the first gate wiring layers 221, 241, and 261 made of chromium (Cr) or molybdenum (Mo) alloy and the like on the insulating substrate 10, and aluminum (Al) or silver (Ag) alloy, as in the first embodiment. A gate wiring formed of a double layer of the second gate wiring layers 222, 242, and 262 formed of the back and the like is formed. The gate wiring includes a gate line 22, a gate pad 24, and a gate electrode 26.

The storage electrode line 28 is formed on the substrate 10 in parallel with the gate line 22. The storage electrode line 28 also includes a double layer of the first gate wiring layer 281 and the second gate wiring layer 282. The storage electrode line 28 overlaps with the conductive pattern 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor that improves the charge retention capability of the pixel. The pixel electrode 82 and the gate to be described later will be described. It may not be formed if the holding capacity generated by the overlap of the lines 22 is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and the storage electrode line 28 to cover the gate wirings 22, 24, 26, and 28.

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, the first data wiring layers 621, 641, 651, 661, and 681 made of Cr or Mo alloy and the like and the second data wiring layers 622 and 642 made of Al or Ag alloy and the like. Data lines 62, 64, 65, 66, and 68 formed of a double layer of 652, 662, and 682 are formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And data line portions 62, 68, and 65 made up of a source electrode 65 of and separated from the data line portions 62, 68, and 65, and on the gate electrode 26 or the channel portion C of the thin film transistor. On the other hand, the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor pattern 64 for the storage capacitor located on the storage electrode line 28 are also included. When the storage electrode line 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66, 68 may be formed of a single layer of Al or Ag as in the first embodiment.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66, 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD film) deposited by plasma enhanced chemical vapor deposition (PECVD) method The protective film 70 which consists of these is formed. At this time, the a-Si: C: O film and the a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a very low dielectric constant of 4 or less. Therefore, even a thin thickness does not cause a parasitic capacity problem. In addition, it is excellent in adhesiveness and step coverage with other films, and because it is an inorganic CVD film, heat resistance is superior to that of an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method are 4 to 10 times faster than the silicon nitride film by the deposition rate or the etching rate. It is also very advantageous in terms of time.

The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24.

At this time, in forming the contact holes 74, 76, and 78 as described above, the photosensitive organic insulating layer 81 used as an etching mask is left without being removed in the photolithography process, thereby simplifying the manufacturing process and shortening the process time. In addition, since the organic insulating film 81 spaces the pixel electrode and the data wiring together with the low dielectric constant CVD film, the parasitic capacitance between the pixel electrode and the data wiring is greatly problematic even when the pixel electrode is formed wide enough to overlap the data wiring. It doesn't work. Therefore, the aperture ratio can be maximized.

On the passivation layer 81, a pixel electrode 82 is formed which receives an image signal from a thin film transistor and generates an electric field together with the electrodes of the upper plate. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the conductive capacitor pattern 64 for the storage capacitor through the contact hole 72 to transmit the image signal to the conductor pattern 64.

On the other hand, an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 7 to 9 using four masks will be described in detail with reference to FIGS. 8 to 10 and 10A to 17C. .

First, as shown in FIGS. 10A to 10C, the first gate wiring layers 221, 241, 261, and 281 are laminated by depositing Cr or Mo alloy having excellent physicochemical properties, and the like, as in the first embodiment. The second gate wiring layers 222, 242, 262, and 282 are stacked by depositing the small Al or Ag alloy, and then photo-etched to include the gate lines 22, the gate pads 24, and the gate electrodes 26. The gate wiring and the sustain electrode line 28 are formed.                     

Next, as shown in FIGS. 11A and 11B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 600 to 600 연속 continuous deposition, followed by deposition by a method such as sputtering the first conductive film 601 made of Cr or Mo alloy or the like and the second conductive film 602 made of Al or Ag alloy. After the conductor layer 60 is formed, the photosensitive film 110 is applied thereon with a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 12B and 12C. At this time, the channel portion C of the thin film transistor among the photoresist patterns 112 and 114, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the first portion 114. The thickness of the second wiring 112 is smaller than that of the second portion 112 positioned at the portion where the data lines 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, All of the 40 must be removed to reveal the gate insulating film 30.

First, as shown in FIGS. 13A and 13B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductive layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

In this way, as shown in FIGS. 13A and 13B, only the conductor layers of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the storage capacitor, are provided. All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. In this case, the remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. . In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 14A and 14B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 14A and 14B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder.

 On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 67 of the channel part C is removed through ashing.

Next, as shown in Figs. 15A and 15B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 thereunder are removed by etching. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness.

In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the photosensitive film second portion 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively simple, but it is difficult to find an appropriate etching condition. In the former case, the etching condition is relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in Figs. 16A and 16B, a-Si: C: O film or a-Si: O: F film is grown by chemical vapor deposition (CVD) to form a protective film 70. In this case, in the case of a-Si: C: O film, SiH (CH ₃ ) ₃ , SiO ₂ (CH ₃ ) ₄ , (SiH) ₄ O ₄ (CH ₃ ) ₄ , and Si (C ₂ H ₅ O ₄ ) is used as a basic source, and is deposited while flowing a gas mixed with an oxidant such as N ₂ O or O ₂ and Ar or He. In the case of an a-Si: O: F film, vapor deposition is performed while flowing a gas containing O ₂ added to SiH ₄ , SiF _{4, or the} like. At this time, CF ₄ may be added as an auxiliary source of fluorine.

17A to 17C, the protective film 70 is etched together with the gate insulating film 30 to electrically conduct the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the sieve pattern 64, respectively.

In this case, when forming the contact holes 74, 76, and 78 using the patterning of the protective layer 70 together with the gate insulating layer 30, an organic insulating layer 81 of photoresist material is used as an etching mask, and the organic insulating layer 81 ) Is included as is, as shown in FIG. 17B.                     

In addition, the area of the contact holes 74 and 78 exposing the pads 24 and 68 does not exceed 2 mm x 60 m, and is preferably 0.5 mm x 15 m or more.

Finally, as shown in FIGS. 8 to 10, a pixel connected to the drain electrode 66 and the conductive capacitor conductor 64 for the storage capacitor by depositing and etching the ITO layer or the IZO layer having a thickness of 400 kHz to 500 kHz. An electrode 82, an auxiliary gate pad 86 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68 are formed.

In this case, when the pixel electrode 82, the auxiliary gate pad 86, and the auxiliary data pad 88 are formed of IZO, chromium etchant may be used as an etchant. Thus, the data exposed through the contact hole during the photolithography process for forming them may be used. Corrosion of the wiring or gate wiring metal can be prevented. Such chromium etchant includes (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O).

In addition, in order to minimize the contact resistance of the contact portion, it is preferable to stack IZO in a range of 200 ° C. or less at room temperature, and a target used to form the IZO thin film preferably includes In ₂ O ₃ and ZnO. The ZnO content is preferably in the range of 15-20 at%.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.                     

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD film) formed by CVD according to the present invention has an AOC (array on color filter) structure in which a thin film transistor array is formed on a color filter. It is also useful as a buffer layer separating the color filter and the thin film transistor.

In the present invention, by forming a protective film using a low dielectric constant CVD film, it is possible to solve the parasitic capacitance problem, to realize a high opening ratio structure, to shorten the process time, and to increase the material cost and subsequent heat resistance due to the use of the organic insulating film. Problems such as the limitation of the process and a large etching error due to the lack of adhesion with the neighboring film can be solved.

Claims (9)

Insulating substrate; A first signal line formed on the insulating substrate; A first insulating film formed on the first signal line; A second signal line formed on the first insulating film and crossing the first signal line; A thin film transistor connected to the first signal line and the second signal line; A second insulating film which is a low dielectric constant CVD film and is formed on the thin film transistor and has a first contact hole for exposing a predetermined electrode of the thin film transistor; A third insulating film formed on the second insulating film and having a second contact hole made of an organic insulating material and exposing a predetermined electrode of the thin film transistor through the first contact hole; And A pixel electrode formed on the third insulating layer and connected to a predetermined electrode of the thin film transistor through the first and second contact holes; Thin film transistor substrate comprising a. In claim 1, The low dielectric constant CVD film is a thin film transistor substrate consisting of a-Si: C: O. In claim 1, The low dielectric constant CVD film is a thin film transistor substrate consisting of a-Si: O: F. In claim 1, The dielectric constant of the low dielectric constant CVD film has a value between 2 and 4. Forming a gate line on the insulating substrate, the gate line including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line; Forming a gate insulating film; Forming a semiconductor layer; Stacking and patterning a conductive material to cross the gate line, a data pad connected to the data line, a source electrode connected to the data line and adjacent to the gate electrode, and opposite to the source electrode with respect to the gate electrode. Forming a data line including a drain electrode positioned at the second electrode; Depositing a low dielectric constant CVD film to form a protective film; Forming a contact hole for exposing the gate pad, the data pad, and the drain electrode by patterning the passivation layer together with the gate insulating layer using a photosensitive organic insulating layer as an etching mask; And Stacking and patterning a transparent conductive layer on the photosensitive organic insulating layer to form an auxiliary gate pad, an auxiliary data pad, and a pixel electrode respectively connected to the gate pad, the data pad, and the drain electrode through the contact hole; Method of manufacturing a thin film transistor substrate comprising a. In claim 5, Forming the protective film, At least one of gaseous SiH (CH ₃ ) ₃ , SiO ₂ (CH ₃ ) ₄ , (SiH) ₄ O ₄ (CH ₃ ) ₄ is used as the primary source, and N ₂ O or O ₂ is used as the oxidant To deposit by PECVD. In claim 5, Forming the protective film, A method of manufacturing a thin film transistor substrate, which is a step of depositing by PECVD using at least one of gaseous SiH ₄ , SiF ₄ and CF ₄ and O ₂ . In claim 5, The data line and the semiconductor layer are formed together through a photolithography process using a photoresist pattern having a first portion and a second portion having a thicker thickness than the first portion. In the photolithography process, the photoresist pattern having the first portion is formed to be positioned between the source electrode and the drain electrode, and the photoresist pattern having the second portion is formed to be positioned above the data line. Manufacturing method. delete

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