KR100796607B1 - Poly silicon crystallization method and fabricating method for thin film transistor using the same - Google Patents

Abstract

A polysilicon crystallization method and a method for manufacturing a thin film transistor by using the same are provided to prevent warpage of a substrate and to improve the quality of grain by forming polycrystalline silicon at low temperature. A buffer layer(102) is formed on a substrate(101). A silicon carbide layer(103) is formed on the buffer layer. An amorphous silicon layer(104) is formed on the silicon carbide layer. A polycrystalline silicon layer as a semiconductor layer is formed by heat-treating the amorphous silicon layer. A gate insulating layer is formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. A heat-treating process is performed by using an in-line furnace apparatus. The heat-treating process is performed during 25 minutes to 3 hours in the temperature of 550 to 750 degrees centigrade.

Description

Polycrystalline silicon crystallization method and manufacturing method of thin film transistor using same {Poly Silicon Crystallization Method and Fabricating Method for Thin Film Transistor Using The Same}

1A to 1H illustrate a method of manufacturing a thin film transistor including a polycrystalline silicon crystallization method according to Example 1 of the present invention.

2A to 2H illustrate a method of manufacturing a thin film transistor including a polycrystalline silicon crystallization method according to Embodiment 2 of the present invention.

3A to 3D illustrate a method of manufacturing a thin film transistor including a polysilicon crystallization method according to Example 3. FIG.

<Brief Description of Drawings>

101 substrate 102 buffer layer

103 silicon carbide layer 104 amorphous silicon

105: gate insulating film 106: gate electrode

107a, 107b. 107c: semiconductor layer in source / channel / drain regions

108: interlayer insulating film

109a and 109b: source / drain electrodes

The present invention relates to a polycrystalline silicon crystallization method and a method for manufacturing a thin film transistor using the same, and more particularly, to a method for crystallizing an amorphous silicon layer by a solid phase crystallization method using a silicon carbide layer and a method for manufacturing a thin film transistor using the same. It is about.

In general, an amorphous silicon thin film and a polycrystalline silicon thin film are used as a semiconductor layer in a thin film transistor. The amorphous silicon thin film has advantages of easy large area deposition, low temperature deposition, and good interfacial properties. However, the amorphous silicon thin film has low field effect mobility, is not applicable to a high speed operation circuit, and has a light leakage current. On the other hand, the polycrystalline silicon thin film has the advantage of being applicable to a high field effect mobility and a high speed operation circuit, and thus is widely used as a semiconductor layer for TFT. However, even in the case of polycrystalline silicon thin film, high temperature deposition is required and the interface characteristics are bad.

There have been many reports on the method of fabricating polycrystalline silicon, and there are largely a method of directly depositing polycrystalline silicon and a method of making polycrystalline silicon through a process of crystallizing after depositing amorphous silicon.

The former method includes a method of depositing polycrystalline silicon using a Low Pressure Chemical Vapor Deposition (LPCVD) method, a Plasma Enhanced Vapor Deposition (PECVD) method, or the like. Since the LPCVD method uses an expensive silica or quartz as a substrate material at a deposition temperature of 550 ° C. or higher, the manufacturing cost is high and it is not suitable for mass production. In the case of PECVD, the SiF ₄ / SiH ₄ / H ₂ mixed gas can be deposited below 400 ° C, but it is difficult to suppress the grains, especially due to the nonuniformity of the grain growth direction during deposition. It is known to have serious problems.

In the latter method, that is, the method of depositing and crystallizing amorphous silicon, the solid phase crystallization (SPC) method, the excimer laser annealing (ELA) method, the sequential lateral crystallization (SLS) method, the metal Metal Induced Crystallization (MIC) method, Metal Induced Lateral Crystallization (MILC) method, Super Grain Silicon (SGS) method and the like.

The ELA method is a method of crystallizing a thin film in an instant by administering an excimer laser having a strong energy in an amorphous silicon thin film to form a polycrystalline silicon thin film having a large crystal grain size and excellent crystallinity. This is possible. Recently, the SLS method is used instead of the ELA method. The SLS method is a crystallization method in which the size of silicon grains can be improved by side-growing grains by a predetermined length by appropriately adjusting the irradiation range of the laser beam using the size of the laser energy and the mask. However, such a method requires an expensive auxiliary equipment such as a laser, and thus can be said to have a limitation in mass production and large area LCD driving TFTs.

On the other hand, the metal induced crystallization (MIC) method uses a gold, silver, aluminum, and the like at a low temperature of about 200 ° C. to form a metastable silicide due to diffusion of silicon at the interface of amorphous silicon. Formation lowers the crystallization energy to promote the crystallization of silicon. In contrast, in metals such as nickel and titanium, diffusion of the metal by annealing is dominant. That is, a silicide phase is formed by metal diffusion from the metal and silicon interface in the direction of the silicon layer, and the silicide promotes crystallization and lowers the crystallization temperature.

However, in the case of manufacturing a thin film transistor using the MIC phenomenon, a metal component used to induce crystallization of amorphous silicon remains in the crystalline silicon constituting the active layer of the thin film transistor, so that a current leakage occurs in the channel portion of the thin film transistor. A problem arises. Recently, instead of the method of inducing the crystallization of silicon by the metal directly contacted or implanted into the silicon, such as MIC, the silicide generated by the reaction of the metal and silicon continues to propagate to the side to induce the crystallization of silicon sequentially. A method of crystallizing a silicon layer using a metal induced lateral crystallization (MILC) phenomenon has been proposed.

This method has the advantage that little metal component is used, which does not affect the current leakage and other operating characteristics of the transistor active layer.

In order to solve the problem there is a SGS (Super Grain Silicon) method for producing a polycrystalline silicon layer as a crystallization method using a cover layer. The method comprises forming an amorphous silicon layer on a substrate and a capping layer thereon, depositing a metal catalyst layer on the capping layer to form a metal catalyst capping layer using a heat treatment or a laser, and then cap After depositing a metal catalyst layer on the ping layer and diffusing the metal catalyst through the capping layer to the amorphous silicon layer using a heat treatment or a laser to form a seed (seed), using this to obtain a polycrystalline silicon layer. However, even in the above method, it is difficult to control uniformly low concentrations of the metal catalyst and thus there is a problem that metal remains, and it is difficult to control the location growth direction and the size of crystal grains where crystallization starts.

Therefore, there is a solid crystallization method as a simple crystallization method without causing problems of other crystallization methods as described above. Solid phase crystallization (SPC) is a method of forming polycrystalline silicon that can withstand high temperatures of 600 ° C. or more and is a method of forming polycrystalline silicon by heat-treating amorphous silicon at a high temperature for a long time. Heat treatment is usually performed in a furnace, and it is performed for a long time at high temperature, so that a desired polycrystalline silicon phase cannot be obtained, the substrate may be damaged due to warpage, and the grain growth direction is irregular, so that it is connected to polycrystalline silicon in application to thin film transistors. The gate insulating film to be grown is irregular and there is a problem that the breakdown voltage of the device is lowered. In addition, since the grain size of the polycrystalline silicon is nonuniform, it may reduce the electrical characteristics of the device.

On the other hand, the solid state crystallization method by the rapid thermal annealing (RTA) process can be made in a relatively short time, but there is a disadvantage that the electrical properties of the crystallized polycrystalline silicon is easy to deform the substrate due to severe thermal shock.

 In the present invention, to solve the problems described above, by using a silicon carbide layer having excellent thermal conductivity crystallization of amorphous silicon at low temperature, a crystallization method of polycrystalline silicon having a stable and excellent crystallinity and a method of manufacturing a thin film transistor using the same To provide.

The present invention to achieve the above object, the present invention is a substrate; A buffer layer formed on the substrate; A semiconductor layer having a source / drain region and a channel region on the buffer layer; A gate electrode formed in a region corresponding to the channel region; A gate insulating film formed between the gate electrode and the semiconductor layer; Provided is a thin film transistor comprising silicon carbide positioned under the semiconductor layer.

The present invention also provides a polycrystalline silicon layer formed by forming a buffer layer on a substrate, forming a silicon carbide layer on the buffer layer, forming an amorphous silicon layer on the silicon carbide layer, and heat-treating the amorphous silicon layer. With semiconductor layer And forming a gate insulating film on the semiconductor layer, and forming a gate electrode on the gate insulating film.

The present invention also provides a buffer layer on a substrate, an amorphous silicon layer on the buffer layer, a silicon carbide layer on the amorphous silicon layer, and heat treatment of the amorphous silicon layer to crystallize the polycrystalline silicon layer. Removing the silicon carbide layer. Forming the polycrystalline silicon layer as a semiconductor layer, forming a gate insulating film positioned on the semiconductor layer, and forming a gate electrode positioned on the gate insulating film. do.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in more detail.

1A to 1H are diagrams sequentially illustrating a method of manufacturing a thin film transistor according to Embodiment 1 of the present invention.

First, referring to FIG. 1A, a buffer layer 102 is formed on a substrate 101. In general, a thin film transistor drive display device is typically a transparent substrate made of alkali-free glass, quartz or silicon oxide, etc. In the present invention, as the substrate, an insulating and transparent glass substrate, a flexible substrate, or a metal such as stainless steel is used. Board | substrate etc. are used. The buffer layer 103 may form a buffer layer 102 between the substrate 101 and the amorphous silicon 103 layer in order to prevent diffusion of contaminants into the thin film of amorphous silicon 103. The buffer layer 103 may be formed of silicon oxide (SiO 2), silicon nitride (SiNX), silicon oxide nitride (SiOxNy), or a composite layer thereof, using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or the like. It is formed by depositing to a thickness of 300 to 10000 Pa, preferably 500 to 3000 Pa at a temperature of 600 ℃ or less using the vapor deposition method of.

Thereafter, the silicon carbide layer 103 is formed on the buffer layer 102 with reference to FIG. 1B. The silicon carbide layer 102 is deposited using conventional deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, and the thickness thereof is 100 kPa to 1 µm. To form. Since the thickness of 100 Å or less is difficult to deposit and is not preferable because it may adversely affect the characteristics of the thin film transistor device when deposited to 1 ㎛ or more. Since the silicon carbide layer has good thermal conductivity, it can improve crystallinity during heat treatment and reduce damage to the substrate.

On the other hand, group III nitride (III-N), a wide-gap (wide-gap) semiconductor, is expected to be a great next-generation communication power device material, and a high-conductivity and electrically insulating substrate is needed for a power device for communication. Silicon carbide (SiC) having a lattice constant such as -N has attracted attention as an excellent candidate. That is, SiC has a thermal conductivity of 41.5W / m.K [room temperature], which is about 1.5 times better than the existing heat-resistant alloy steel [26.6 W / m.K, room temperature]. Therefore, it can be used in crystallization to obtain polycrystalline silicon of better quality than conventional.

 As shown in FIG. 1C, an amorphous silicon layer 104 is formed on the silicon carbide layer 103 by using a plasma enhanced chemical vapor deposition (PECVD), a low pressure chemical vapor deposition (LPCVD), or a sputtering conventional deposition method. do. Although the thickness of the amorphous silicon layer 104 may be deposited to be 2000 Å or less, if the thickness is too thin, polycrystalline silicon may form a thin film transistor, and thus may affect the characteristics of the device. It is preferable.

Subsequently, the substrate on which the amorphous silicon 104 is deposited is subjected to heat treatment using solid phase crystallization to crystallize to form a polycrystalline silicon layer.

The heat treatment method of forming the crystallization is heat treatment using a furnace, in-line furnace, rapid thermal annealing (RTA), etc. In the present invention, 550 using an in-line furnace It is preferable to crystallize by heat treatment at from -750 ℃ for 25 minutes to 3 hours. Because heat treatment below 550 ℃ process time is too long and heat treatment above 750 ℃ may damage the substrate is not preferred. In general, in case of heat treatment in general furnace, it is performed for a long time at high temperature, so it is impossible to obtain the desired polycrystalline silicon phase, and the substrate may be damaged due to warpage, and the grain growth direction is irregular. There is a problem in that the breakdown voltage of the device is lowered because the gate insulating film to be connected is grown irregularly. In-line furnaces offer cost savings over conventional furnaces, can be specified for different temperatures and times, and reduce damage to the substrate because the substrate is placed on a quartz-setter. It can be done. In addition, there is an advantage that can increase the product yield by shortening the process time.

On the other hand, the solid state crystallization method by the rapid thermal annealing (RTA) process can be made in a relatively short time, but there is a disadvantage that the electrical properties of the crystallized polycrystalline silicon is easy to deform the substrate due to severe thermal shock.

As shown in FIG. 1C, the substrate including amorphous silicon is heat-treated to crystallize into polycrystalline silicon, and then, as shown in FIG. 1D, the polycrystalline silicon layer is patterned into islands to form a semiconductor layer 107. Subsequently, as shown in FIG. 1E, SiO 2, SiN x, SiO x N y, or a composite layer thereof is formed on the semiconductor layer 107 to a thickness of 300 to 3000 kPa, preferably 500 to 1000 kPa, using a method such as PECVD or LPCVD. The gate insulating film 105 is formed. Thereafter, a conductive material such as a metal material or a doped polysilicon is formed on the gate insulating layer 105 using a method such as sputtering, heat evaporation, PECVD, LPCVD, or the like to form a gate metal layer having a thickness of 1000 to 8000 kPa, preferably 2000 to 4000 kPa. Is deposited to form the gate electrode 106. The gate electrode is made of metal such as AlNd and Mo.

Thereafter, n + ions are implanted into the semiconductor layer 104 using the gate electrode 106 as a mask to form source / drain regions 107a and 107b. The ion-doped semiconductor layer 107 is activated by a heat treatment process in an excimer laser annealing method (ELA), a RTA or a furnace, preferably in a heat treatment process in an RTA or a furnace.

Subsequently, an interlayer insulating layer 108 such as SiO ₂ or SiNx is formed over the entire surface of the substrate over the gate electrode 106, and then the interlayer insulating layer 108 and the gate insulating layer 105 are exposed to expose the source / drain regions 107a and 107b. ) To form a contact hole, and the contact hole is sufficiently filled with AlNd, Mo, or the like to form source / drain electrodes 109a / 109b to complete the thin film transistor.

Hereinafter, Embodiment 2 of the present invention will be described with reference to FIGS. 2A to 2H.

2A to 2H are views illustrating a method of manufacturing the thin film transistor according to the second embodiment.

2A and 2B, the buffer layer 102 is formed on the substrate 101. In general, a thin film transistor driving display device is a transparent substrate made of alkali-free glass, quartz, or silicon oxide, and the like. In the present invention, the substrate 101 is an insulating and transparent glass substrate, a flexible substrate, or a stainless steel. Metal substrates such as steel are used. The buffer layer 103 may form a buffer layer 102 between the substrate 101 and the amorphous silicon 103 layer in order to prevent diffusion of contaminants into the thin film of amorphous silicon 103. The buffer layer 103 may be formed of silicon oxide (SiO 2), silicon nitride (SiNX), silicon oxide nitride (SiOxNy), or a composite layer thereof, using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or the like. It is formed by depositing to a thickness of 300 to 10000 Pa, preferably 500 to 3000 Pa at a temperature of 600 ℃ or less using the vapor deposition method of.

Thereafter, an amorphous silicon layer 104 is formed on the buffer layer 102.

The deposition method of the amorphous silicon layer 104 uses a conventional deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, etc., the thickness of the amorphous silicon 104 Although it may be deposited below 2000 kW, if the thickness is too thin, it is preferable to deposit a thickness of 300 to 1000 kW because polycrystalline silicon may affect the device characteristics when forming a thin film transistor.

 Thereafter, the silicon carbide layer 103 is formed on the amorphous silicon layer 104. As the deposition method of the silicon carbide layer 103, a conventional deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or the like is used. do. Since the thickness of 100 Å or less is difficult to deposit and is not preferable because it may adversely affect the characteristics of the thin film transistor device when deposited to 1 ㎛ or more. Since the silicon carbide layer has good thermal conductivity, it can improve crystallinity during heat treatment and reduce damage to the substrate.

Subsequently, as shown in FIG. 2C, after the substrate including the silicon carbide layer 103 is heat treated to crystallize the amorphous silicon layer 104 into a polycrystalline silicon layer, the silicon carbide layer remains on the surface of the semiconductor layer. Since the silicon carbide layer 103 is etched and removed, since the characteristics of the thin film transistor may be affected. Thereafter, the polycrystalline silicon layer is patterned using a photolithography process to form the semiconductor layer 107.

The patterned semiconductor layer 107 is crystallized by heat treatment by a solid phase crystallization method. The method of crystallizing by heat treatment is performed by heat treatment using a furnace, an in-line furnace, rapid thermal annealing (RTA), or the like. In the present invention, an in-line furnace is used for heat treatment at 550 to 750 ° C. for 25 minutes to 3 hours to perform solid phase crystallization. Because the process time is too long when the heat treatment below 550 ℃, it is not preferable because the substrate is damaged when the heat treatment at 750 ℃ or more. In-line furnaces are cost effective compared to conventional furnaces and can be specified for different temperatures and times. In addition, since the substrate is placed on a setter made of quartz, damage to the substrate can be reduced, so that heat treatment can be performed at 750 ° C., and the process time can be shortened to increase product yield.

Subsequently, as shown in FIG. 2C, the SiO 2, SiN x, SiO x N y, or a composite layer thereof on the semiconductor layer 107 is gated to a thickness of 300 to 3000 Å, preferably 500 to 1000 Å using a method such as PECVD or LPCVD. An insulating film 105 is formed. Thereafter, as shown in FIG. 2F, a conductive material such as a metal material or a doped polysilicon is formed on the gate insulating film 105 using a method such as sputtering, heat evaporation, PECVD, LPCVD, and preferably, The gate electrode 106 is formed by depositing a gate metal layer with a thickness of 2000 to 4000 microns. The gate electrode 106 uses a metal such as AlNd, Mo, or the like.

Thereafter, as shown in FIG. 2F, the semiconductor layer 107 is doped with ions using the gate electrode 106 as a mask to form source / drain regions 107a and 107b, and excimer laser annealing method (ELA) The ion-doped semiconductor layer is activated by a heat treatment process in a RTA or a furnace, preferably in a heat treatment process in an RTA or a furnace.

Subsequently, as shown in FIGS. 2G and 2H, an interlayer insulating film 108 such as SiO 2, SiN x, or a double layer using the same is formed on the gate electrode 106 over the substrate, and then the source / drain regions 107a and 107b. The interlayer insulating film 108 and the gate insulating film 105 are etched to form a contact hole, and the source / drain electrodes 109a and 109b are formed using AlNd, Mo, or the like to complete the semiconductor device.

Hereinafter, Embodiment 3 of the present invention will be described with reference to FIGS. 3A to 3D.

Example 3 is the same as Example 2 except for partially forming a silicon carbide layer on amorphous silicon.

3A to 3D, the buffer layer 102 is formed on the substrate 101. In general, a thin film transistor driving display apparatus is a transparent substrate made of alkali-free glass, quartz, or silicon oxide. In the present invention, the substrate 101 is an insulating and transparent glass substrate, a flexible substrate, or stainless steel. A metal substrate such as the above is used. The buffer layer 103 may form a buffer layer 102 between the substrate 101 and the amorphous silicon 103 layer in order to prevent diffusion of contaminants into the thin film of amorphous silicon 103. The buffer layer 103 may be formed of silicon oxide (SiO 2), silicon nitride (SiNX), silicon oxide nitride (SiOxNy), or a composite layer thereof, using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or the like. It is formed by depositing to a thickness of 300 to 10000 Pa, preferably 500 to 3000 Pa at a temperature of 600 ℃ or less using the vapor deposition method of.

Thereafter, an amorphous silicon layer 104 is formed on the buffer layer 102.

The deposition method of the amorphous silicon layer 104 uses a conventional deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, etc., the thickness of the amorphous silicon 104 Although it may be deposited below 2000 kW, if the thickness is too thin, it is preferable to deposit a thickness of 300 to 1000 kW because polycrystalline silicon may affect the device characteristics when forming a thin film transistor.

 Thereafter, as shown in FIG. 3C, a silicon carbide layer 103 is formed on the amorphous silicon layer 104. As the deposition method of the silicon carbide layer 103, a conventional deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or the like is used. do. It is not preferable because it is difficult to deposit when deposited below 100 ,, and may affect the characteristics of the thin film transistor device when deposited at 1 μm or more. When the silicon carbide layer is used, since the thermal conductivity is good, the crystallinity of the amorphous silicon may be improved during heat treatment, and the damage of the substrate may be reduced. The silicon carbide layer on the amorphous silicon layer is partially formed by patterning using a photolithography process. This can be useful for changing the properties of the desired part because the partial properties of the amorphous silicon on which partially patterned silicon carbide is deposited during crystallization can be improved.

Referring to FIG. 3C, the entire substrate on which the partially formed silicon carbide layer 103 is deposited is crystallized by heat treatment using solid phase crystallization, and the substrate including the silicon carbide layer 103 is heat treated to form an amorphous silicon layer 103. Crystallized into a polycrystalline silicon layer. Thereafter, the silicon carbide layer 103 is etched and removed to improve the surface characteristics of the semiconductor layer. Thereafter, as shown in FIG. 3D, the polycrystalline silicon layer is patterned using a photolithography process to form a semiconductor layer 107.

Since the process sequence of forming the thin film transistor with the semiconductor layer is the same as the process sequence of Example 2, a specific process sequence is omitted in order to avoid duplication.

As described above, in the present invention, by crystallizing the amorphous silicon layer using the solid phase crystallization method using the silicon carbide layer, polycrystalline silicon can be formed at low temperature to prevent substrate warpage, and the quality of crystal grains can be improved. Therefore, a thin film transistor having more excellent characteristics can be manufactured.

Claims (11)

delete delete Forming a buffer layer on the substrate, Forming a silicon carbide layer on the buffer layer, Forming an amorphous silicon layer on the silicon carbide layer, The amorphous silicon layer is heat-treated to crystallize the polycrystalline silicon layer as a semiconductor layer Forming, Forming a gate insulating film on the semiconductor layer, And forming a gate electrode on the gate insulating film. The method of claim 3, wherein The heat treatment is a method of manufacturing a thin film transistor, characterized in that the heat treatment using an in-line furnace equipment. The method of claim 3, wherein The heat treatment is a method of manufacturing a thin film transistor, characterized in that the heat treatment for 25 minutes to 3 hours at a temperature of 550 to 750 ℃. The method of claim 3, wherein The silicon carbide (SiC) layer has a thickness of 100 kHz to 1 ㎛ manufacturing method of a thin film transistor. Forming a buffer layer on the substrate, Forming an amorphous silicon layer on the buffer layer, Forming a silicon carbide layer on the amorphous silicon layer, Heat treating the amorphous silicon layer to crystallize a polycrystalline silicon layer, Removing the silicon carbide layer, Forming the polycrystalline silicon layer as a semiconductor layer, Forming a gate insulating film on the semiconductor layer, And forming a gate electrode on the gate insulating film. The method of claim 7, wherein The heat treatment is a method of manufacturing a thin film transistor, characterized in that the heat treatment using an in-line furnace equipment. The method of claim 7, wherein The heat treatment is a method of manufacturing a thin film transistor, characterized in that the heat treatment for 25 minutes to 3 hours at a temperature of 550 ℃ to 750 ℃. The method of claim 7, wherein The silicon carbide (sic) layer has a thickness of 100 mW to 1 m. The method of claim 7, wherein And the silicon carbide layer is formed in part on the amorphous silicon layer.

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