KR100771229B1 - Method for forming soi mosfet by annealing in high-pressure hydrogen ambient - Google Patents
Method for forming soi mosfet by annealing in high-pressure hydrogen ambient Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 23
- 229910052739 hydrogen Inorganic materials 0.000 title claims description 20
- 239000001257 hydrogen Substances 0.000 title claims description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 title claims description 19
- 238000000137 annealing Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 7
- 230000005527 interface trap Effects 0.000 claims description 5
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims description 2
- 229910052805 deuterium Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000008569 process Effects 0.000 description 15
- 239000007789 gas Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H01L21/76—Making of isolation regions between components
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract
Description
도 1은 본 발명의 일 실시예에 따른 고압 수소에서 열처리한 SOI MOSFET 시편과 기존의 성형가스(forming gas)에서 열처리한 시편의 전기적 특성을 비교한 그래프이다.1 is a graph comparing the electrical characteristics of the SOI MOSFET specimens heat-treated in high pressure hydrogen and the specimens heat-treated in the conventional forming gas according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 완전 공핍형 SOI MOSFET 소자의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a fully depleted SOI MOSFET device according to an embodiment of the present invention.
도 3 및 도 4는 본 발명의 일 실시예에 따른 완전 공핍형 SOI MOSFET의 전압-전류 특성을 디커플드(decoupled) 조건에서 측정한 결과를 나타낸 그래프로서,도 3은 게이트 절연막 영역의 전류-전압 특성 곡선이고, 도 4는 매몰 산화막 영역의 전류-전압 특성 곡선이다.3 and 4 are graphs showing the results of measuring the voltage-current characteristics of a fully depleted SOI MOSFET in a decoupled condition according to an embodiment of the present invention. 4 is a voltage characteristic curve, and FIG. 4 is a current-voltage characteristic curve of the buried oxide region.
도 5는 본 발명의 일 실시예에 따른 완전 공핍형 SOI MOSFET의 전하 이동도 특성곡선이다.5 is a charge mobility characteristic curve of a fully depleted SOI MOSFET according to an embodiment of the present invention.
본 발명은 모스 전계효과 트랜지스터(MOS(metal-oxide-silicon) field effect transistor, 이하 'MOSFET'라 한다) 중 특히 완전공핍형(fully depleted) SOI(silicon-on-insulator) MOSFET의 제조방법에 있어서, 게이트 절연막 계면(front interface)과 매몰 산화막 계면(back interface)의 계면 트랩전하를 패시베이션(passivation, 비활성화)하여 전기적 특성을 향상시키는 SOI MOSFET의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a fully depleted silicon-on-insulator (SOI) MOSFET, particularly among metal-oxide-silicon (MOS) field effect transistors (MOSMOS). The present invention relates to a method for fabricating an SOI MOSFET which improves electrical characteristics by passivating the interface trap charges at the gate insulating film front interface and the buried oxide back interface.
일반적으로 차세대 반도체 소자로 유망한 완전 공핍형 SOI MOSFET은 초고집적화, 저전력 및 저전압소자, 고속동작 기능 등의 이점을 갖고 있어 최근에 많이 연구되고 있다.In general, fully depleted SOI MOSFETs, which are promising next-generation semiconductor devices, have been studied in recent years because they have advantages such as high integration, low power and low voltage devices, and high speed operation functions.
SOI 소자는 접합정전용량을 줄일 수 있어 스위칭 동작을 향상시키며 저전압에서 전류수송 능력을 증가시킴과 동시에 누설전류를 줄일 수 있는 장점을 가지고 있다.SOI devices have the advantage of reducing junction capacitance, improving switching behavior, increasing current carrying capability at low voltages, and reducing leakage current.
그러나 최근 소자가 스케일링 됨에 따라 SOI의 두께 또한 줄어들면서 매몰 산화막의 계면 트랩전하가 소자의 전기적 특성에 크게 영향을 주게 되었다.However, as the device scales recently, the thickness of the SOI also decreases, and the interfacial trap charge of the buried oxide film greatly influences the electrical characteristics of the device.
기존의 반도체 소자의 제작 공정의 마지막 단계에서 성형가스(forming gas)를 이용한 열처리 공정을 수행하는데, 이는 트랜지스터 계면에 존재하는 계면 트랩전하를 효과적으로 패시베이션 시켜준다. In the last step of the fabrication process of the conventional semiconductor device, a heat treatment process using a forming gas is performed, which effectively passivates the interface trap charge existing at the transistor interface.
보통 4% 정도의 수소를 사용함이 일반적이다.Usually 4% of hydrogen is used.
그러나, 이러한 성형가스 열처리 공정은 일반적으로 SOI 소자 구조에서 발생하는 두 계면을 효과적으로 모두 패시베이션하기에 불충분하다.However, this forming gas heat treatment process is generally insufficient to effectively passivate both interfaces occurring in the SOI device structure.
SOI 소자는 매몰 산화막(buried oxide)을 가진 구조로 인하여 일반적인 게이트 절연막 계면과 매몰 산화막 계면의 두 계면을 가지고 있는데, 계면에서의 결함은 소자의 성능에 크게 영향을 준다.The SOI device has two interfaces, a general gate insulating film interface and a buried oxide film interface, due to the structure having a buried oxide. Defects at the interface greatly affect the performance of the device.
특히 완전 공핍형 SOI MOSFET에서는 SOI 필름두께가 점차 스케일링 다운(scaling down)됨에 따라 front 게이트와 back 게이트 사이에 강한 커플링이 존재하므로 계면에서의 결함이 소자의 특성열화에 미치는 영향이 더욱 증가되는 경향이 있다.Particularly in fully depleted SOI MOSFETs, as the SOI film thickness scales down, there is a strong coupling between the front and back gates, so the effect of defects at the interface on the deterioration of the device tends to increase. There is this.
따라서 이러한 매몰 산화막 계면의 특성을 향상시키는 것이 더욱 필요하다.Therefore, it is further necessary to improve the characteristics of the buried oxide film interface.
매몰 산화막 계면의 경우 실리카(SiO2)의 게이트 절연막 계면에 비해 계면 전하의 밀도가 높고 표면 실리콘 반도체층에 의해 매몰되어 있기 때문에 대기압(1기압)에서 행해졌던 일반적인 성형가스 열처리 조건에서는 충분한 양의 수소가 확산되기 어려워서, 계면전하가 잔존함으로써 소자의 전하 이동도 특성이 현저히 악화되는 문제가 있다.In the case of the buried oxide film interface, since the density of the interfacial charge is higher than that of the gate insulating film interface of silica (SiO 2 ) and is buried by the surface silicon semiconductor layer, a sufficient amount of hydrogen is used in the general forming gas heat treatment condition performed at atmospheric pressure (1 atm). Is difficult to diffuse, and there is a problem that the charge mobility characteristics of the device are remarkably deteriorated due to remaining of interfacial charges.
본 발명의 목적은 상기와 같은 종래기술의 문제점을 해결하기 위하여 고압의 가스 분위기에서 열처리하는 방법을 통하여 매몰 산화막 계면의 트랩 전하를 패시베이션 시킴으로써 전하이동도 및 문턱전압곡선의 기울기 등의 전기적 특성이 향상된 초박막(ultra-thin body) 완전 공핍형 SOI MOSFET 소자를 제공하는 데 있다.An object of the present invention is to improve the electrical properties such as the charge mobility and the slope of the threshold voltage curve by passivating the trap charge of the buried oxide layer through a method of heat treatment in a high-pressure gas atmosphere to solve the problems of the prior art as described above To provide an ultra-thin body fully depleted SOI MOSFET device.
본 발명의 또다른 목적은 기존의 공정에 비하여 별도의 복잡한 공정을 거치지 아니하고서도 계면 특성이 향상된 완전공핍형의 SOI MOSFET 소자의 제조방법을 제공하는 데 있다.It is another object of the present invention to provide a method for manufacturing a fully depleted SOI MOSFET device having improved interface characteristics without undergoing a separate complicated process compared to the existing process.
상기 목적을 달성하기 위하여 본 발명의 SOI MOSFET 제조방법은 일반적이고 표준적인 SOI MOSFET의 제조방법에 있어서, SOI MOSFET 소자가 고압의 가스 분위기에서 열처리되는 공정을 포함한다.In order to achieve the above object, the SOI MOSFET manufacturing method of the present invention includes a process in which a SOI MOSFET device is heat-treated in a high-pressure gas atmosphere in a general and standard SOI MOSFET manufacturing method.
본 발명의 SOI MOSFET 제조방법은 일반적이고 표준적인 SOI MOSFET의 제조방법에 있어서, SOI MOSFET 소자의 게이트 절연막 계면(front interface)과 매몰 산화막 계면(back interface)을 고압의 가스 분위기에서 열처리하여 계면 트랩전하를 패시베이션(passivation)하는 것을 특징으로 한다.The SOI MOSFET manufacturing method of the present invention is a general and standard method of manufacturing a SOI MOSFET, wherein the gate insulating film front interface and the buried oxide back interface of the SOI MOSFET device are heat treated in a high-pressure gas atmosphere to provide an interface trap charge. Passivation (passivation) is characterized in that.
본 발명에서 바람직하게는 상기 열처리 압력은 3 내지 25기압인 것을 특징으로 한다.In the present invention, the heat treatment pressure is preferably 3 to 25 atmospheres.
본 발명에서 바람직하게는 상기 열처리 온도는 250 내지 500℃ 인 것을 특징으로 한다.In the present invention, the heat treatment temperature is preferably 250 to 500 ° C.
본 발명에서 바람직한 상기 열처리 시간은 10분 내지 120분인 것을 특징으로 한다.In the present invention, the heat treatment time is preferably 10 minutes to 120 minutes.
본 발명에서 바람직하게는, 가스 분위기는 100% 수소 및 100% 중수소로부터 선택된 하나 이상인 것을 특징으로 한다.Preferably, the gas atmosphere is at least one selected from 100% hydrogen and 100% deuterium.
본 발명에서는 일반적인 벌크 실리콘 반도체 소자의 패시베이션 문제를 해결하기 위하여 일반적인 반도체 소자의 마지막 열처리 공정에 사용된 3-4%의 수소가 함유된 성형가스 대신에 100% 고농도의 수소를 사용하여 고압에서 열처리하는 것을 제안한다. 특히 바람직하게는 10기압 이상의 가스 분위기에서 수행함을 특징으로 한다.In the present invention, in order to solve the passivation problem of the bulk silicon semiconductor device in general, heat treatment at high pressure using 100% high concentration hydrogen instead of 3-4% hydrogen-containing forming gas used in the final heat treatment process of the general semiconductor device. Suggest that. Especially preferably, it is carried out in a gas atmosphere of 10 atmospheres or more.
다량의 수소가 SOI의 두 계면(front/back interface)에 충분히 공급되면계면에 존재하는 트랩과 수소 결합을 형성함으로써, 전기적으로 불활성화(inactive)됨으로써, 계면 트랩전하의 패시베이션을 극대화할 수 있다.When a large amount of hydrogen is sufficiently supplied to the front / back interface of the SOI, it is possible to maximize the passivation of the interface trap charge by forming a hydrogen bond with the trap existing on the interface and electrically inactive.
본 발명의 일 실시예로서 SOI MOSFET 소자를 제작하는 공정은 다음과 같다.As an embodiment of the present invention, a process of fabricating an SOI MOSFET device is as follows.
<실시예><Example>
1) 완전 공핍형 SOI MOSFET 을 형성하기 위한 SOI 필름 두께는 30nm 이하로 형성한다. 1) The thickness of the SOI film for forming a fully depleted SOI MOSFET is 30 nm or less.
2) 표준 SOI MOSFET 제작공정을 이용하여 소자를 제작한다.2) Fabricate device using standard SOI MOSFET manufacturing process.
해당 기술분야의 당업자라면 일반적으로 공지의 SOI MOSFET 제조공정으로부터 알 수 있는 방법을 이용할 수 있다.Those skilled in the art can generally use methods known from known SOI MOSFET manufacturing processes.
3) 100% 수소 분위기에서 공정온도 400℃, 공정압력 10기압, 공정시간 30분간 열처리를 실시한다.3) Heat treatment at 100 ℃ hydrogen atmosphere for process temperature of 400 ℃, process pressure of 10 atm and process time for 30 minutes.
이하, 첨부한 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.
본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 공지 기능 및 구성에 대한 상세한 설명은 생략한다.Detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.
도 1은 본 발명의 일 실시예에 따른 고압 수소에서 열처리한 본 발명의 SOI MOSFET 시편과 기존의 성형가스에서 열처리한 시편의 전기적 특성을 나타낸다. Figure 1 shows the electrical characteristics of the SOI MOSFET specimen of the present invention heat-treated in high-pressure hydrogen according to an embodiment of the present invention and the specimen heat-treated in the conventional forming gas.
즉, 전압(VG)-전류(ID) 특성곡선과 전압에 대한 트랜스컨덕턴스(transconductance, Gm) 특성곡선을 함께 도시하였다.That is, the voltage (V G ) -current (I D ) characteristic curve and the transconductance (G m ) characteristic curve with respect to the voltage are also shown.
트랜스컨덕턴스는 전류전압이득을 나타낸다.The transconductance represents the current voltage gain.
도 1을 참조하면, 삼각형 도트로 표시된 선은 본 발명의 일 실시예에 따라 수소 가스 분위기 하에서 300℃, 10기압에서 20분간 열처리한 SOI MOSFET 소자의 전기적 특성을 도시한 것이고, 사각형 도트로 표시된 선은 기존의 표준공정인 4% 수소가 함유된 성형가스 분위기에서 400℃, 대기압 하에 20분 동안 열처리한 소자의 전기적 특성을 도시한 것이다.Referring to FIG. 1, a line indicated by a triangle dot shows electrical characteristics of an SOI MOSFET device heat-treated at 300 ° C. and 10 atmospheres for 20 minutes in a hydrogen gas atmosphere according to an embodiment of the present invention. Shows the electrical characteristics of the device heat-treated for 20 minutes at 400 ℃, atmospheric pressure in a molding gas atmosphere containing 4% hydrogen, the existing standard process.
도 1에서 알 수 있듯이, 본 발명의 SOI MOSFET 소자의 시편은 계면 전하 밀도의 감소로 구동전류가 현저히 증가하고 트랜스컨덕턴스(transconductance (Gm))가 향상되었다. 또한 문턱전압곡선의 기울기가 72 mV/dec에서 63 mV/dec로 크게 향상되어 스위칭 특선이 개선되었다.As can be seen in Figure 1, the specimen of the SOI MOSFET device of the present invention significantly increased the drive current and the transconductance (G m ) by the reduction of the interfacial charge density. In addition, the slope of the threshold voltage curve has been greatly improved from 72 mV / dec to 63 mV / dec, thereby improving switching characteristics.
도 2는 본 발명의 일 실시예에 따른 완전 공핍형 SOI MOSFET 소자의 구조를 나타낸 단면도인데, 실리콘 기판 위에 매몰 산화막이 적층되고 그 위에 표면 실리콘 반도체를 형성하여 불순물을 주입해서 소스와 드레인을 형성하였으며, 소스와 드레인 간에 채널영역을 형성하고 상부에 실리카(SiO2)절연막과 도전층으로 다결정 실리콘을 적층한 구조이다.2 is a cross-sectional view showing a structure of a fully depleted SOI MOSFET device according to an embodiment of the present invention, in which a buried oxide film is stacked on a silicon substrate, and a surface silicon semiconductor is formed thereon to form a source and a drain by implanting impurities. In addition, a channel region is formed between the source and the drain, and polycrystalline silicon is stacked on top of a silica (SiO 2 ) insulating film and a conductive layer.
상기 실시예는 점선의 원형으로 표시한 게이트 절연막 계면(front interface)과 실선의 원형으로 표시한 매몰 산화막 계면(back interface)의 2개의 계면을 가지는 SOI MOSFET 구조를 나타낸다. 상기 2개의 계면특성에 의해 소자의 구동 전류/전하이동도가 영향을 받는다. 특히, 소자가 스케일링됨에 따라 SOI의 두께가 얇아지면서 매몰 산화막 계면의 트랩전하가 소자의 전기적 특성에 더욱 영향을 주게 되었다.The above embodiment shows an SOI MOSFET structure having two interfaces, a gate insulating film front interface shown by a dotted circle and a buried oxide back interface shown by a solid line. The two interfacial properties influence the drive current / charge mobility of the device. In particular, as the device is scaled, as the thickness of the SOI becomes thinner, the trap charge of the buried oxide interface has more influence on the electrical characteristics of the device.
도 3과 도 4는 본 발명의 일 실시예에 따른 완전 공핍형 SOI MOSFET의 전압-전류 특성을 디커플드(decoupled) 조건에서 측정한 결과를 나타낸 그래드이다.3 and 4 are graphs showing the results of measuring the voltage-current characteristics of a fully depleted SOI MOSFET in a decoupled condition according to an embodiment of the present invention.
도 3은 게이트 절연막의 영역의 전압(VG)-전류(ID) 특성곡선이고, 도 4는 매몰 산화막 영역의 전압(VG)-전류(ID) 특성곡선이다. 이를 참조하면, 문턱전압 이하의 특성을 게이트 절연막 계면과 매몰 산화막 계면으로 나누어 측정한 결과, 매몰 산화막의 계면특성이 상대적으로 더 크게 향상되었음을 알 수 있다. 이는 기존 의 성형가스 분위기에서 열처리 공정을 적용할 경우, 수소의 농도가 낮아서, 상대적으로 깊은 곳에 존재하는 매몰산화막 계면까지 수소가 충분히 침투하지 못하므로 계면 특성이 상대적으로 나쁜 것으로 평가된다. 3 is a voltage (V G ) -current (I D ) characteristic curve of the region of the gate insulating film, Figure 4 is a voltage (V G ) -current (I D ) characteristic curve of the buried oxide region. Referring to this, as a result of dividing the characteristics below the threshold voltage into the gate insulating film interface and the buried oxide film interface, it can be seen that the interfacial properties of the buried oxide film are significantly improved. This is because when the heat treatment process is applied in the existing molding gas atmosphere, the concentration of hydrogen is low, so that the hydrogen does not sufficiently penetrate to the buried oxide film interface existing in a relatively deep, the interface characteristics are evaluated as relatively bad.
그러나, 본 발명의 일 실시예에 따른 고압, 고농도 수소열처리의 경우, 수소가 매몰 산화막 계면에 충분히 확산 공급되어 계면을 패시베이션함으로써, 소자의 구동전류를 현저하게 개선된다. 고압 수소 열처리는 게이트 절연막 계면보다 매몰 산화막 계면특성에 더 영향을 주는 것으로 볼 수 있다.However, in the case of high pressure and high concentration hydrogen heat treatment according to an embodiment of the present invention, hydrogen is sufficiently diffused and supplied to the buried oxide film interface to passivate the interface, thereby significantly improving the driving current of the device. The high pressure hydrogen heat treatment may be seen to affect the buried oxide film interface characteristics more than the gate insulating film interface.
도 5는 본 발명의 일 실시예에 따른 완전공핍형 SOI 반도체소자의 전하이동도 특성 향상을 나타내는 그래프이다.5 is a graph showing an improvement in charge mobility characteristics of a fully depleted SOI semiconductor device according to an embodiment of the present invention.
도 5를 참조하면 상기 실시예에 따른 완전공핍형 SOI MOSFET 소자의 전하 이동도가 고압 수소 열처리 후 약 600cm2/Vs 에서 약 800cm2/Vs 로 개선됨을 알 수 있다.With reference to Figure 5 if after fully depleted charge mobility of the high-voltage SOI MOSFET device hydrogen heat treatment according to the embodiment, it can be seen in improved about 600cm 2 / Vs to about 800cm 2 / Vs.
상기 도면을 참조하면, 결론적으로 고압, 고농도의 수소를 열처리함으로써 SOI 소자의 매몰 산화막 계면의 충분한 패시베이션이 가능하고 이로 인해 소자의 구동전류, 전하이동도, 스위칭 등의 전기적 특성이 향상되어 차세대 고속, 저전력 소자로서 크게 유용할 것으로 기대된다. Referring to the drawings, in conclusion, heat treatment of high pressure and high concentration of hydrogen enables sufficient passivation of the buried oxide interface of the SOI device, thereby improving the electrical characteristics such as driving current, charge mobility, switching, etc. It is expected to be very useful as a low power device.
상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술분야의 숙련된 당업자라면 하기의 특허등록청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art can vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.
상술한 바와 같이 본 발명에 의하면, SOI MOSFET 소자에서 전기적 특성에 영향을 미치는 매몰 산화막 계면(back interface)을 포함한 두 계면(front/back interface)의 트랩전하를 모두 충분히 패시베이션함으로써 소자의 구동전류, 전하이동도, 스위칭 등 전기적 특성을 향상시키는 효과가 있다.As described above, according to the present invention, the driving current and the charge of the device are sufficiently passivated by fully passivating the trap charges of both front and back interfaces including the buried oxide back interface which affects the electrical characteristics in the SOI MOSFET device. There is an effect of improving the electrical characteristics, such as mobility, switching.
또한, 기존의 공정에 비하여 별도의 복잡한 공정을 거치지 아니하고서도 완전공핍형의 SOI MOSFET 소자의 계면 특성을 향상시키는 제조방법을 제공함으로써 결과적으로 이러한 소자를 이용한 고속, 저전력 전자제품을 생산하는 경제적인 가치창출의 효과가 있다.In addition, by providing a manufacturing method that improves the interfacial characteristics of a fully depleted SOI MOSFET device without going through a complicated process compared to the existing process, as a result, the economic value of producing high-speed, low-power electronic products using such a device There is an effect of creation.
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