KR100760143B1 - Circuit for tracking tuner filter of broadcasting receiver - Google Patents

Abstract

A tuner filter tracking circuit in a broadcasting receiver is provided to reduce time for sweeping a broadband filter and minimize size of a register necessary for data storage. A center frequency of a tuner filter(120) is sequentially changed so that the center frequency of the tuner filter(120) is tuned to a selected channel. Herein, the powers of frequencies outputted from the tuner filter(120) are respectively measured. The measured powers of the frequencies are sequentially compared with each other, thereby detecting a frequency having the maximum power. The detected frequency is set to the center frequency for the selected channel.

Description

Tuner filter tracking circuit of a broadcast receiver {Circuit for tracking tuner filter of broadcasting receiver}

1 is a schematic block diagram of a tuner filter tracking circuit of a broadcast receiver according to the present invention;

2 is a timing diagram illustrating the operation of a latch according to the present invention;

3 is a timing diagram illustrating the operation of the tuner filter tracking circuit according to the present invention;

4 is a view showing a center frequency variable example of a tuner filter according to the present invention;

FIG. 5 is a diagram for explaining an output change according to a change in the center frequency of the tuner filter as shown in FIG. 4.

Explanation of symbols on the main parts of the drawings

110: oscillator 120: tuner filter

130: power measurement unit 140: N-bit ADC

150: a plurality of latches 160: clock generator

170: N-bit comparator 180: up / down counter

190: control unit

The present invention relates to a tuner filter tracking circuit of a broadcast receiver. More particularly, the present invention relates to a tuner filter tracking circuit of a broadcast receiver that adjusts a center frequency of a tuner filter to pass only a signal of a band corresponding to a selected channel among high frequency signals received through an antenna. A tuner filter tracking circuit is provided.

In general, in a broadcast receiver, a tuner performs a channel selection function to enable a user to watch a desired channel. The tuner amplifies and selects a received signal and restores only a signal of a desired channel.

The tuner of the broadcast receiver has a wider bandwidth (45 to 850 MHz) than the other wireless communication devices.

As such, since the frequency band of the signal received by the tuner is wide, there is a high probability of being interfered with by adjacent channels. Interference caused by such adjacent channels causes deterioration of reception characteristics.

Therefore, in order to pass only the signal of the band corresponding to the selected channel among the high frequency signals received through the antenna, the center frequency of the tuner filter must be changed according to the selected channel. That is, the center frequency of the maximum output should be searched while varying the center frequency of the tuner filter in response to channel selection.

To this end, the broadcast receiver should have a filter tracking circuit to set the center frequency of the tuner filter corresponding to the selected channel.

Such a filter tracking circuit is preferably designed so that its structure is not complicated and does not take much time to sweep the wideband filter.

Accordingly, an object of the present invention is to provide a tuner filter tracking circuit of a broadcast receiver capable of reducing the time required for sweeping a wideband filter in minimizing filter tracking and minimizing the size of a register required for data storage.

The tuner filter tracking circuit of the broadcast receiver according to the present invention for achieving the above object is characterized in that it comprises an oscillator, tuner filter, A / D converter, a plurality of latches, comparison unit and control unit.

The oscillator serves to generate the same frequency as the selected channel in response to channel selection, and the tuner filter filters and outputs the frequency output from the oscillator while sequentially changing the center frequency under the control of the controller. Perform.

The power measuring unit measures the power of the frequency output from the tuner filter, and the A / D converter converts the frequency power measured by the power measuring unit into an N bit digital code.

The plurality of latches serve to store N bits of digital codes outputted from the A / D converter, and the comparator compares the N bits of digital codes outputted from the plurality of latches. Therefore, an up signal or a down signal is output.

The controller detects a center frequency at which the output of the tuner filter is maximum based on the signal output from the comparator, and sets the detected center frequency as the center frequency of the tuner filter for the selected channel.

The tuner filter may vary the center frequency sequentially according to the control of the controller.

The plurality of latches may include a plurality of first latches for storing an odd-numbered digital code among the N-bit digital codes output from the A / D changing unit and N-bit digital outputs from the A / D changing unit. And a plurality of second latches for storing digital codes output evenly among the codes.

The tuner filter tracking circuit of the broadcast receiver according to the present invention may further include an up / down counter for performing an up counting or down counting operation according to the signal output from the comparator.

The controller detects a point in time at which the current and previous states are the same without being toggled by the output of the comparator or the up / down counter. The center frequency set in the filter may be set as the center frequency of the tuner filter for the selected channel.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. However, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a schematic block diagram of a tuner filter tracking circuit of a broadcast receiver according to the present invention.

As shown in FIG. 1, the tuner filter tracking circuit of the broadcast receiver according to the present invention includes an oscillator 110, a tuner filter 120, a power measurement unit 130, and an N-bit analog-to-digital converter. Converter, hereinafter referred to as " ADC "), a plurality of latches 150, a clock generator 160, an N-bit comparator 170, an up / down counter 180, and a controller 190 It is composed.

The oscillator 110 generates the same frequency as that of the tuning target channel under the control of the controller 190 and applies it to the tuner filter 120.

The tuner filter 120 filters and outputs the frequency output from the oscillator 110 while sequentially changing the center frequency from low to high under the control of the controller 190.

The power measuring unit 130 measures the power of the frequency output from the tuner filter 120 and outputs it to the N-bit ADC 140.

The N-bit ADC 140 converts the frequency input from the power measuring unit 130 into an N bit digital code.

The latches 150 alternately store N-bit digital codes output from the N-bit ADC 140 in synchronization with the latch clock latch_clk generated by the clock generator 160.

The plurality of latches 150 may include N first latch latch_A and N second latch latch_B.

2 is a timing diagram illustrating the operation of the latch according to the present invention.

As shown in FIG. 2, odd-numbered digital codes D1, D3, D5,... Of digital codes output from the N-bit ADC 140 are stored in the N first latch latch_A. The second latch latch_B stores even-numbered digital codes D2, D4, D6,... Among the digital codes output from the N-bit ADC 140.

The N-bit comparator 170 compares the N-bit digital codes output from the N first latch latch_A and the N second latch latch_B, and according to a result of the comparison, an N-bit comparator 170 Output a Down-Signal.

For example, the N-bit comparator 170 outputs an up signal when the digital code output from the N second latch latch_B is larger than the digital code output from the N first latch latch_A. When the digital code output from the first latch latch_A is larger than the digital code output from the second latch latch_B, the down signal may be output.

Alternatively, the N-bit comparator 170 outputs an up signal when the digital code output from the N first latch latch_A is larger than the digital code output from the N second latch latch_B, and the second latch. When the digital code output from the latch_B is larger than the digital code output from the first latch_A, the down signal may be output.

The up / down counter 180 performs up counting or down counting according to the signal output from the N-bit comparator 170. The up / down counter 180 is operated in synchronization with the count clock count_clk output from the clock generator 160.

The controller 190 operates the filter tracking mode to find the center frequency of the tuner filter 120 corresponding to the selected channel in response to the channel selection. In this case, the controller 190 switches the switch 115 for the filter tracking mode to the oscillator 110 so that the signal generated from the oscillator 110 is applied to the tuner filter 120.

The controller 190 monitors a counting operation of the up / down counter 180 to detect a center frequency at which the output of the tuner filter 120 is maximum, and tunes the detected center frequency to a selected channel. Set to the center frequency of the filter 120.

After setting the center frequency of the tuner filter 120 as described above, the switch 115 is switched back to the antenna 105 side so that the signal received through the antenna 105 is applied to the tuner filter 120. .

3 is a timing diagram for explaining the operation of the tuner filter tracking circuit according to the present invention.

As shown in FIG. 3, the N-bit digital code output from the N-bit ADC 140 is synchronized with the latch clock latch_clk input from the clock generator 160 to latch the first latch latch_A and the second latch. Stored alternately in latch latch_B.

That is, the odd-numbered digital codes D1, D3, D5,... Output from the N-bit ADC 140 are stored in the first latch latch_A, and the N-bit ADC ( The even-numbered digital codes D2, D4, D6, ... outputted at 140 are stored.

N-bit comparator 170 is an N-bit digital code ((D1, D2), (D3, D2), (D3, D4), (D5, D4), (D5, D6) input from a plurality of latches 150 ), ...) are compared to output an up or down signal.

The up / down counter 180 performs an up counting or down counting operation according to the signal output from the N-bit comparator 170. The counting operation of the up / down counter 180 is repeated until the point at which the output of the tuner filter 120 is maximized is detected.

The output of the up / down counter 180 maintains its previous state (up-up or down-down) immediately after passing the point where the output of the tuner filter 120 becomes maximum.

The controller 190 monitors the operation of the up / down counter 180 so that the output of the up / down counter 180 is not toggled and the current (n) and previous (n-1) states are the same. If is detected, the tuner filter 120 is set to the center frequency set in the tuner filter 120 at the previous time point n-1 as the center frequency for the currently selected channel.

As an example, the center frequency of the tuner filter 120 is sequentially changed as shown in FIG. 4. Until the output of the tuner filter 120 is maximum, as shown in FIG. 5, the n + 1 th response is greater than the n th response. After passing the point where the output of the tuner filter 120 is maximized, the n th response is greater than the n + 1 th response.

That is, since the n th response is greater than the n + 1 th response until the power of the frequency output from the tuner filter 120 becomes maximum, the output of the N-bit comparator 170 is up-down-up. If the output of the tuner filter 120 has the maximum value at the time t = 3 as shown in FIG. 5, the up signal is generated since the n th response is smaller than the n + 1 th response in the subsequent sequence. Therefore, the output of the N-bit comparator 170 is up-down-up-up, and accordingly, the output of the up / down counter 180 is up-down-up-up.

The controller 190 monitors the output of the N-bit comparator 170 or the up / down counter 180 so that the output of the N-bit comparator 170 or the up / down counter 180 is not toggled. By detecting a point in time at which the states of (n) and (n-1) are the same, the center frequency at which the output of the tuner filter 120 is maximized can be found.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

As described above, according to the present invention, in order to adjust the center frequency of the tuner filter to the selected channel in response to channel selection, the center frequency of the tuner filter is sequentially changed, and at this time, the power of the frequency output from the tuner filter is measured. do. Then, the power of the measured frequency is sequentially compared and outputs an up signal or a down signal according to the comparison result, and detects the center frequency at which the output of the tuner filter is maximum based on the signal output from the comparator, Set the detected center frequency as the center frequency for the selected channel.

Therefore, according to the present invention, it is possible to reduce the time required for sweeping a tuner filter that receives a wideband signal, such as a broadcast receiver, and only two data output from the tuner filter may be stored at a time, thereby requiring a register for data storage. Can minimize the size.

Claims (5)

An oscillator for generating the same frequency as the selected channel in response to channel selection; A tuner filter for filtering a frequency output from the oscillator while sequentially changing a center frequency; A power measuring unit measuring power of a frequency output from the tuner filter; An A / D converter converting the frequency power measured by the power measuring unit into an N bit digital code; A plurality of first latches for storing the odd-numbered digital codes of the N-bit digital codes output from the A / D converter and an even-numbered output of the N-bit digital codes output from the A / D converter A plurality of latches having a plurality of second latches for storing the digital codes, wherein the plurality of latches alternately store the N-bit digital codes; A comparator for comparing the N-bit digital codes output from the plurality of first latches and the plurality of second latches provided in the plurality of latches, and outputting an up signal or a down signal according to the comparison result; And A controller for detecting a center frequency at which the output of the tuner filter is maximum based on the signal output from the comparator, and setting the detected center frequency to the center frequency of the tuner filter for the selected channel; Tuner filter tracking circuit. The method of claim 1, The tuner filter is a tuner filter tracking circuit of the broadcast receiver, characterized in that for varying the center frequency in sequence under the control of the controller. delete The method of claim 1, And an up / down counter for performing an up counting or down counting operation according to the signal output from the comparator. The method according to claim 1 or 4, The controller detects a point in time at which the current and previous states are the same without being toggled by the output of the comparator or the up / down counter. A tuner filter tracking circuit of a broadcast receiver, characterized in that for setting the center frequency was set to the center frequency of the tuner filter for the selected channel.

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