KR100756711B1 - Semiconductor memory device to prevent data destruction - Google Patents

Abstract

A plurality of memory cells MC each storing n values (n is a natural number not less than 3) are arranged in a matrix form in the memory cell array 1, and each memory cell is a word line WL0. WL31 and bit lines BL0-BLn + 1. Each memory cell stores n-valued data by the first write operation and the second write operation. The reading section sets the potential of the word line and reads data from the memory cells in the memory cell array. If the data read by the reading section and written in the second writing operation contain an uncorrectable error, the control section changes the potential of the word line supplied to the reading section when reading the data written in the first writing operation.

Semiconductor memory device, NAND flash memory, memory cell, word line, bit line

Description

Semiconductor memory device to prevent data destruction {SEMICONDUCTOR MEMORY DEVICE WHICH PREVENTS DESTRUCTION OF DATA}

1A-1E illustrate a relationship between data in a memory cell and a threshold voltage of the memory cell in accordance with the present invention.

2A-2D illustrate a relationship between data in a memory cell and a threshold voltage of the memory cell, according to the prior art.

3 shows a schematic configuration of a semiconductor memory device to which the present invention is applied.

FIG. 4 is a circuit diagram showing the configuration of the memory cell array and bit line control circuit shown in FIG.

5A and 5B are cross-sectional views illustrating memory cells and select transistors.

6 is a cross-sectional view illustrating one NAND cell in a memory cell array.

FIG. 7 is a circuit diagram showing an example of a data memory circuit shown in FIG.

8 is a diagram showing a recording order for a NAND cell.

9 is a flowchart showing an example of a first page program.

10 is a flowchart showing an example of a second page program.

FIG. 11A shows data in each data cache after reading internal data, and FIG. 11B shows data in each data cache after the first setting of each data cache.

12A is a diagram showing data in each data cache after the first step of writing the second page, and FIG. 12B is a diagram showing data in each data cache after the second setting of each data cache.

FIG. 13A shows data in each data cache after the second step of writing the second page, and FIG. 13B shows each data cache when the first step in the writing of the second page is omitted. A diagram showing the data in the interior.

14 is a waveform diagram illustrating an example of operations of a word line, a bit line, and a selection gate line in a verify operation.

15 is a flowchart showing a first page read operation.

16 is a flowchart showing a second page reading operation.

Fig. 17 is a flowchart showing a reading procedure on the user side.

Fig. 18 is a flowchart showing a reading sequence of a second page in the second embodiment.

Fig. 19 is a flowchart showing a reading sequence of a first page in the third embodiment.

<Explanation of symbols for main parts of the drawings>

1: Memory Cell Array (MCA)

1-1: ECC area

2: bit line control circuit

3: thermal decoder

4: data input / output buffer

5: data input / output terminal

6: word line control circuit

7: control signal and control voltage generator circuit

7-1: fuse circuit

8: Control signal input terminal

9: controller

The present invention relates to, for example, a NAND flash memory using EEPROM, and more particularly, to a semiconductor memory device capable of storing multivalued data in a single memory cell.

In a NAND flash memory, a plurality of memory cells arranged in a column direction are connected in series to form a NAND cell, and each NAND cell is connected to a corresponding bit line through a selection gate. Each bit line is connected to a latch circuit for latching write data and read data. A nonvolatile semiconductor memory device capable of storing multi-value data in this NAND flash memory has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2000-195280).

In recent years, miniaturization of elements has progressed, and the distance between cells has been reduced. Therefore, the influence of the floating gate capacitance between the cells adjacent to each other is increasing. Specifically, a problem arises in that a threshold voltage of a cell in which data is already written is adjacent to the cell and subsequently fluctuates due to a threshold voltage of the cell in which data is written. In particular, since a multivalued memory that stores a plurality of data sets each of two or more bits in a single cell stores a plurality of data sets by using a plurality of threshold voltages, it corresponds to one data set. The threshold voltage distribution must be controlled to be extremely narrow. Therefore, the influence of the threshold voltage of the adjacent cell is remarkable.

To solve this problem, in a memory cell in which 1-bit (first page) data is stored, the 1-bit (first page) data may have a threshold voltage lower than the original threshold voltage before storing the next data. V-level) to write to adjacent memory cells. After writing data to this adjacent memory cell, writing is performed to raise the voltage to the original threshold voltage (word line potential "b" (V <= B)) when writing the second page. However, it is difficult to find out whether the data of the first page is recorded at the original threshold voltage or the lower threshold voltage before and after writing the second page. Therefore, in order to find out, a writing method has been proposed in which a flag memory cell (called a flag cell) is prepared according to each page and a read operation is performed in accordance with the data in this flag cell (for example, Japanese patent application) See Publication 2004-192789).

When the data of the second page is written based on this recording method, when the data of the first page is "1" and the data of the second page is "0", the data in the memory cell is from "0" to "1". And the threshold voltage is increased to level A, for example. In addition, when the data of the first page is "0", its threshold voltage is determined as the voltage including the level A. Thus, their threshold voltage distributions overlap each other. Therefore, when recording is interrupted, for example, due to an abnormal interruption of power during recording of the second page, a problem arises that previously written first page data is also destroyed. Therefore, there is a need for a semiconductor memory device capable of avoiding destruction of data of the first page even when writing of the second page is abnormally interrupted.

According to a first aspect of the present invention, a memory cell array in which a plurality of memory cells are arranged in a matrix form, each memory cell is connected to a word line and a bit line, and n (where n is a natural number not smaller than 3) ), A recording unit for writing n-valued data into the memory cell in which k values (k <n) are stored, from the memory cells in the memory cell array. A reading section for setting the potential of the word line for reading data, and when reading the k-valued data when the uncorrectable error is included in the data read by the reading section. And a control unit for changing the potential of the word line supplied to the reading unit.

According to a second aspect of the present invention, there is provided a memory cell for storing n values (where n is a natural number not smaller than 3), and a controller for controlling the memory cell, wherein the controller is configured to perform a first write operation. The threshold voltage of the memory cell is set from the first threshold voltage to the first threshold voltage or the second threshold voltage (the first threshold voltage <the second threshold voltage), and the threshold voltage of the memory cell is set to the first threshold voltage. When the threshold voltage is 2, the threshold voltage of the memory cell is set to be equal to or greater than a third threshold voltage (the second threshold voltage ≤ the third threshold voltage) by a second write operation, and the threshold voltage of the memory cell is In the case of the first threshold voltage, the threshold voltage of the memory cell is set to the first threshold voltage or the fourth threshold voltage (the first threshold voltage <the fourth threshold voltage) by a third write operation. A semiconductor memory device is provided.

According to a third aspect of the present invention, there is provided a memory cell for storing n values (where n is a natural number not less than 3), a first flag memory cell, a second flag memory cell, and the memory cell and the first value. And a controller configured to control first and second flag memory cells, wherein the controller controls the threshold voltage of the memory cell from a first threshold voltage to a first threshold voltage or a second threshold voltage (the first threshold voltage) by a first write operation. Set the threshold voltage <the second threshold voltage, and when the threshold voltage of the memory cell is the second threshold voltage, the threshold voltage of the memory cell is changed to a third threshold voltage (the second threshold voltage) by a second write operation. Set the threshold voltage ≤ the third threshold voltage) and write data to the second flag memory cell to achieve the third threshold voltage, wherein the threshold voltage of the memory cell is the first threshold In the case of pressure, writing is performed to achieve the threshold voltage of the memory cell as the first threshold voltage or the fourth threshold voltage (the first threshold voltage <the fourth threshold voltage) by a third write operation, and the memory When the threshold voltage of the cell is the third threshold voltage, a write is performed to set the threshold voltage of the memory cell to a fifth threshold voltage, and a write is performed to the first flag memory cell to set the fourth threshold voltage. There is provided a semiconductor memory device which performs the following.

DESCRIPTION OF EMBODIMENTS Now, embodiments according to the present invention will be described with reference to the accompanying drawings.

(First embodiment)

3 shows a schematic configuration of a semiconductor memory device storing data having three or more values, for example, a configuration of a NAND flash memory storing four values (2 bits).

The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line. In the memory cell array 1, electrically rewritable memory cells, for example made of EEPROM cells, are arranged in a matrix. The bit line control circuit 2 and word line control circuit 6 for controlling the bit lines are connected to this memory cell array 1.

The bit line control circuit 2 includes a plurality of data storage circuits and flag data storage circuits, which will be described later. The bit line control circuit 2 reads data in the memory cells of the memory cell array 1 through the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and Data is written to the memory cells in the memory cell array 1 by applying a write control voltage to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data in the memory cell read out by the data storage circuit is output from the data input / output terminal 5 to the outside via the data input / output buffer 4.

In addition, the write data input from the outside to the data input / output terminal 5 is input to the data storage circuit selected by the column decoder 3 through the data input / output buffer 4.

The word line control circuit 6 is connected to the memory cell array 1. This word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for a read, write or erase operation to the selected word line.

The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4 and the word line control circuit 6 are connected to the control signal and the control voltage generator circuit 7. And controlled by it. The control signal and control voltage generator circuit 7 are connected to the control signal input terminal 8 and controlled by a control signal input from the outside via the control signal input terminal 8.

The bit line control circuit 2, the column decoder 3, the word line control circuit 6, and the control signal and control voltage generator circuit 7 constitute a write circuit and a read circuit.

In addition, the memory cell array 1 has an ECC region 1-1 in which an error correction code ECC is stored.

In addition, the data input / output terminal 5 and the control signal input terminal 8 of the NAND flash memory are connected to a controller 9 provided outside the NAND flash memory chip. This controller 9 transmits / receives data or commands between the NAND flash memory and a host device, for example, not shown.

In addition, the control signal and control voltage generator circuit 7 has a fuse circuit 7-1. This fuse circuit 7-1, for example, consists of a nonvolatile memory, a laser fuse or a latch circuit, stores data necessary for controlling the operation of the write circuit and the read circuit, which will be described later. It should be noted that in the case of latch circuits, the data stored in certain blocks in the memory cell array are stored in the latch circuits at power up.

4 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. In the memory cell array 1, a plurality of NAND cells are arranged. A NAND cell consists of, for example, a memory cell MC consisting of 32 EEPROMs connected in series and a selection gate S1 and S2. The first select gate S1 is connected to the bit line BL0, and the second select gate S2 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are equally connected to the word lines WL0, WL1, WL2 through WL31. In addition, the first select gate S1 is equally connected to the select line SGD, and the second select gate S2 is equally connected to the select line SGS.

In addition, a plurality of memory cells (memory cells surrounded by dotted lines) arranged every other bit line and connected to one word line constitute one sector. Data is recorded or read in units of sectors. For example, data corresponding to two pages is stored in one sector. Further, the first and second flag cells FC1 and FC2 for storing flags are connected to respective word lines. In other words, in this embodiment, one sector includes two first and second flag cells FC1 and FC2.

The bit line control circuit 2 includes a plurality of data storage circuits 10 and flag data storage circuits 10a and 10b. Each of the data storage circuit 10 and the flag data storage circuits 10a and 10b includes a pair of bit lines BL0 and BL1, BL2 and BL3, ..., BLi and BLi + 1 or BLn and Connected to BLn + 1).

As indicated by the dotted lines, the memory cell array 1 includes a plurality of blocks. Each block consists of a plurality of NAND cells, and data is erased in block units. In addition, the erase operation is performed simultaneously through two bit lines connected to the data storage circuit 10 and the flag data storage circuits 10a and 10b.

In the read operation, the program verify operation, and the program operation, one of the two bit lines BLi and BLi + 1 connected to the data storage circuit 10 is selected according to an address signal specified from the outside. In addition, one word line is selected according to an external address so that one sector (corresponding to two pages) is selected. The conversion of two pages is performed using the address.

Note that the number of first and second flag cells FC1 and FC2 connected to one sector is not limited to one, and a plurality of flag cells may be connected to one sector as indicated by a dotted line. In this case, as described later, it is preferable to determine the data stored in the flag cell based on the majority of the data stored in the plurality of flag cells.

In addition, the cells in which ECC data are stored and the data storage circuits connected to these cells are the same as those of the circuit configuration shown in FIG. 4, and thus they are omitted in FIG. 4.

5A and 5B are cross-sectional views illustrating memory cells and select transistors. 5A shows a memory cell. In the substrate 41, an n-type diffusion layer 42 is formed as a source and a drain of the memory cell. The floating gate (FG) 44 is formed on the substrate 41 via the gate insulating film 43, and the control gate (CG) 46 is formed on the floating gate 44 via the insulating film 45. It is. 5B shows a select gate. In the substrate 41, an n-type diffusion layer 47 is formed as a source and a drain. The control gate 49 is formed on the substrate 41 via the gate insulating film 48.

6 shows a cross section of one NAND cell in a memory cell array. In this example, one NAND cell is constructed by connecting 32 memory cells MC having the configuration shown in Fig. 5A in series. The first select gate S1 and the second select gate S2 having the configuration shown in FIG. 5B are provided on the drain side and the source side of the NAND cell.

FIG. 7 is a circuit diagram illustrating an example of the data storage circuit 10 shown in FIG. 4. The flag data storage circuits 10a and 10b also have the same configuration as the data storage circuit 10.

The data storage circuit 10 includes a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDC), and a dynamic data cache Q (dynamic data). cache Q, DDCQ), and temporary data cache (TDC). SDCs, PDCs, and DDCs hold input data in write operations, hold read data in read operations, temporarily hold data in verify operations, and manipulate internal data when storing multi-value data. Used. The TDC is used to amplify the data on the bit line, to temporarily hold the data in the data read operation, and to manipulate the internal data in storing the multi-value data. The DDCQ stores data indicating whether a verify level has been reached which is slightly lower than a particular verify level in the write operation described later.

The SDC is composed of clocked inverter circuits 61a and 61b and transistors 61c and 61d constituting a latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. The signal EQ2 is supplied to the gate of this transistor 61c. The transistor 61d is connected between the input terminal of the clocked inverter circuit 61b and ground. The signal PRS is supplied to the gate of this transistor 61d. The node N2a of the SDC is connected to the input / output data line IO through the column select transistor 61e, and the node N2b is connected to the input / output data line IOn through the column select transistor 61f. It is connected. The column select signal CSLi is supplied to the gates of these transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC through transistors 61g and 61h. The signal BLC2 is supplied to the gate of the transistor 61g, and the signal BLC1 is supplied to the gate of the transistor 61h.

The PDC consists of clocked inverter circuits 61i and 61j and a transistor 61k. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. The signal EQ1 is supplied to the gate of this transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 61l. One end of the current path of the transistor 61l is connected to ground through the transistor 61m. The signal CHK1 is supplied to the gate of this transistor 61m.

In addition, the other end of the current path of the transistor 61l is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. The signal CHK2n is supplied to the gate of this transistor 61n. In addition, the gate of the transistor 61o is connected to a junction node between the transistors 61g and 61h. Signal COMi is supplied to the other end of the current path of transistors 61n and 61o. This signal COMi common to all the data storage circuits 10 is a signal indicating whether all of the data storage circuits 10 have been verified. That is, as described later, if they are verified, node N1b of the PDC goes low. In this state, when the signals CHK1 and CHK2n go high, when the verification is completed, the signal COMi goes high.

In addition, the TDC consists of, for example, a MOS capacitor 61p. This capacitor 61p is connected between the junction node N3 of the transistors 61g and 61h and ground. In addition, the DDC is connected to the junction node N3 through the transistor 61q. The signal REG is supplied to the gate of the transistor 61q.

The DDC consists of transistors 61r and 61s. The signal VREG is supplied to one end of the current path of the transistor 61r, and the other end of this current path is connected to the current path of the transistor 61q. The gate of this transistor 61r is connected to the node N1a of the PDC through the transistor 61s. The signal DTG is supplied to the gate of this transistor 61s.

The DDCQ consists of transistors 61Qr and 61Qs. The signal VREG is supplied to one end of the current path of the transistor 61Qr, and the other end of this current path is connected to the junction node N3 through the transistor 61Qq. The signal REGQ is supplied to the gate of the transistor 61Qq. The gate of the transistor 61Qr is connected to the node N1a of the PDC through the transistor 61Qs. The signal DTGQ is supplied to the gate of this transistor 61Qs.

In addition, one end of the current path of the transistors 61t and 61u is connected to the junction node N3. The signal VPRE is supplied to the other end of the current path of the transistor 61u, and the BLPRE is supplied to the gate of the transistor 61u. The signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLo via the transistor 61v, and is connected to one end of the bit line BLe through the transistor 61w. . The other end of the bit line BLo is connected to one end of the current path of the transistor 61x. The signal BIASo is supplied to the gate of this transistor 61x. The other end of the bit line BLe is connected to one end of the current path of the transistor 61y. The signal BIASe is supplied to the gate of this transistor 61y. The signal BLCRL is supplied to the other end of the current path of these transistors 61x and 61y. Transistors 61x and 61y are turned on in accordance with signals BIASo and BIASe to be complementary to transistors 61v and 61w, thereby applying a potential of signal BLCRL to unselected bit lines.

Each of the above signals and voltages is generated by the control signal and control voltage generator circuit 7 shown in FIG. Under the control of this control signal and control voltage generator circuit 7, the following operations are controlled.

Since this memory is a multivalued memory, 2-bit data can be stored in a single cell. The two bit transition is performed using the address (first page or second page).

(Explanation of the action)

The operation in the above configuration will now be described.

1A to 1E illustrate a relationship between data in a memory cell and a threshold voltage of the memory cell. When erase is performed, the data in the memory cell becomes " 0 ". As shown in Fig. 1A, when the first page is written, the data in the memory cell becomes data " 0 " and data " 2 ". The threshold voltage distribution of the data "2" is set slightly lower than the threshold voltage distribution of the original data "2".

Thereafter, as shown in Fig. 1B, data is recorded in an adjacent cell before recording the second page. The threshold voltage distribution of data "2" then increases due to the data written to this cell. Then, when the data of the second page is written, the data in the memory cell becomes data "0" to "3" having original threshold voltages as shown in Fig. 1E. In this embodiment, the data in the memory cell is defined in ascending order from the lower threshold voltage.

The difference between the operation of this embodiment shown in Figs. 1A to 1E and the recording operation of the prior art shown in Figs. 2A to 2D is as described below.

In this embodiment, after writing data in the adjacent cell, the second page is written in two steps. As shown in Fig. 1C, since it is preferable to perform the write operation with the threshold voltage of level "b" or more in the first step, the data "2" of the first page is written with the original threshold voltage "b". As another alternative, the data " 2 " of the first page is written with threshold voltages of " b " and " c " (indicated by dashed lines in FIG. 1C). In addition, as shown in Fig. 1D, the data " 2 " is similarly recorded in the second flag cell FC2. It can be determined that the data of the second page has been written based on the data in this second flag cell FC2. Then, in the second step of the operation of recording the second page, when the data of the first page is "1" and the data of the second page is "0", data "1" is recorded. In addition, when the data of the first page is "0" and the data of the second page is "1", data "3" is recorded. In this manner, the threshold distribution of FIG. 1E can be set.

Even when the power is turned off during the write operation of the second page, the threshold voltage of the first page data does not overlap with the threshold voltage of other data as shown in Figs. 1B and 1C. Therefore, the data of the first page is not destroyed even if the writing operation of the second page fails. Accordingly, in the read operation, when the potential of the word line is set to the potential "a" or "b" shown in Fig. 1E, the data of the first page can be read.

In contrast, in the case of the prior art shown in Figs. 2A to 2D, after writing data to the adjacent cells shown in Fig. 2B, the level " a " and the " a " The write operation is performed simultaneously to achieve the level "b". As shown in Fig. 2C, the data "2" does not reach the original threshold voltage during the write operation of the second page. In addition, when data "1" is recorded, there is a possibility that the threshold voltage distribution of data "1" overlaps with the threshold voltage distribution of data "2". In this state, when the power is turned off, the first page is destroyed. Therefore, it is difficult to read the first page data.

8 shows a write order for a NAND cell. In the block, the write operation is performed from the memory cell close to the source line according to each page. In Fig. 8, the number of word lines is four for convenience.

In the first write operation, one-bit data is written to the first page of the memory cell 1.

In the second write operation, one-bit data is written to the first page of the memory cell 2 adjacent to the memory cell 1 in the word direction.

In the third write operation, 1-bit data is written to the first page of the memory cell 3 adjacent to the memory cell 1 in the bit direction.

In the fourth write operation, one-bit data is written to the first page of the memory cell 4 adjacent to the memory cell 1 in the diagonal direction.

In the fifth write operation, one-bit data is written to the second page of the memory cell 1.

In the sixth write operation, one-bit data is written to the second page of the memory cell 2 adjacent to the memory cell 1 in the word direction.

In the seventh write operation, one-bit data is written to the first page of the memory cell 5 adjacent to the memory cell 3 in the bit direction.

In the eighth write operation, one-bit data is written to the first page of the memory cell 6 adjacent to the memory cell 3 in the diagonal direction.

In the ninth write operation, one-bit data is written to the second page of the memory cell 3.

In the tenth write operation, one-bit data is written to the second page of the fourth memory cell 4 adjacent to the memory cell 3 in the word direction.

In the eleventh write operation, one-bit data is written to the first page of the memory cell 7 adjacent to the memory cell 5 in the bit direction.

In the twelfth write operation, one-bit data is written to the first page of the memory cell 8 adjacent to the memory cell 5 in the diagonal direction.

In the thirteenth write operation, one-bit data is written to the second page of the memory cell 5.

In the fourteenth write operation, one-bit data is written to the second page of the memory cell 6 adjacent to the memory cell 5 in the word direction.

In the fifteenth write operation, one-bit data is written to the second page of the memory cell 7.

In the sixteenth write operation, one-bit data is written to the second page of the memory cell 8 adjacent to the memory cell 7 in the word direction.

Now, the specific recording operation will be described later.

(Program operation and program verification operation)

(1st page program operation)

9 is a flowchart showing an example of a program operation for a first page. In the program operation, an address is first addressed to select two pages (one sector) shown in FIG. The memory can perform the program operation only in the order of the first page and the second page of these two pages. Thus, the first page is first selected based on the address.

When the transistor 61d shown in Fig. 7 is turned on during the input of this address, the nodes N2a of all the SDCs are set to the ground potential Vss (S11).

Subsequently, write data is input externally and stored in the SDC in all the data storage circuits 10 (S12). At this time, in the case of recording data, data "0" is input externally, but the node N2a of the SDC is set to the power supply voltage Vdd. In addition, when the write operation is not selected, the data "1" is input externally, but the node N2a of the SDC is set to the ground potential Vss. Thereafter, when a write command is input, data in the SDC of all the data storage circuits 10 are transferred to the PDC (S13). That is, the signals BLC1 and BLC2 have a predetermined voltage, for example, Vdd + Vth (Vdd: power supply voltage (for example, 3V or 1.8V, but not limited to this voltage), Vth: N− Threshold voltage of the channel MOS transistor), and the transistors 61h and 61g are turned on. The data in node N2a is then transmitted to the PDC via transistors 61g and 61h. Therefore, when data "1" (write operation is not performed) is input from the outside, the node N1a of the PDC is set to the low level. When data "0" (write operation is performed) is input, the node N1a of the PDC is set to a high level. Thereafter, the data in the PDC is set to the potential of the node N1a, and the data in the SDC is set to the potential of the node N2a.

(Data Reverse Operation) (S14)

The signal VPRE is then set to Vdd, while the signal BLPRE is set to Vdd + Vth and the junction node N3 is temporarily precharged to Vdd. Thereafter, the signal DTG is set to Vdd + Vth, and data in the PDC is transmitted to the DDC. The signal REG is then set to Vdd and the signal VREG is set to Vss. When the data in the DDC is at the high level, the junction node N3 changes to the low level. When data in the DDC is at the low level, the junction node N3 remains at the high level. Thereafter, the signals SEN1n and LAT1n are temporarily turned off, the signal EQ1 is set to Vdd, and the nodes N1a and N1b are set to the same potential. The signal BLC1 is then set to Vdd + Vth, and the data in the TDC (potential of the junction node N3) is transferred to the PDC. As a result, when data "1" is latched in the PDC from the beginning, this data becomes data "0". When data "0" is latched, this data becomes data "1".

When a write command is input, the control signal and the control voltage generator circuit 7 supply the program voltage Vpgm (e.g., 20V) to the selected word line, and Vpass (e.g., 10V) to the unselected word. Feed the line. However, since these voltages do not increase immediately, the data inversion operation is performed at the waiting time. Therefore, the recording speed is not reduced.

In inverting the input data in this manner, when performing the so-called page copy in which the data of the first page written to the memory cell is read into the page buffer and this data is written to another page without being output to the outside, The operation is performed first, but the SDC takes "1" for the recorded data (data "0") and the SDC takes "0" for unrecorded data (data "1"). This data in the SDC matches the input data as inverted data. That is, SDC = "1" is achieved when the write operation is performed, and SDC = "0" is achieved when the write operation is not performed. Matching the next write data with the SDC in this manner may facilitate inputting data from outside and rewriting part of the read data. Therefore, when page copying is not performed, data input from the outside is always inverted in the page buffer.

After the data inversion operation, the data in the PDC is also copied to the DDC.

On the other hand, in the program operation for the first page, data is not written to the flag cell. Thus, the PDC in the flag data storage circuit 10a has data "1".

(Program operation) (S15)

The potential of the signal BLC1, BLCLAMP, BLSo or BLSe shown in FIG. 7 is set to Vdd + Vth. The transistors 61h, 61t, 61v or 61w are then turned on, and the data held in the PDC is supplied to the bit line. When data " 1 " (write operation is not performed) is stored in the PDC, the bit line is set to Vdd (power supply voltage). When data "0" (write operation is performed) is stored in the PDC, the bit line is set to Vss (ground potential). In addition, data should not be written to a cell that is connected to the selected word line and has an unselected page (no bit line is selected). Thus, Vdd is also supplied to the bit line connected to this cell as in the example of data " 1 ". Here, Vdd is supplied to the selection line SGD, the potential Vpgm 20V is applied to the selected word line, and the potential Vpass 10V is applied to the unselected word line in the selected block. Then, when the bit line is set to Vss, the channel of the cell is set to Vss and the word line is set to Vpgm. Thus, the recording operation is performed. On the other hand, when the bit line is set to Vdd, the cell's channel is not set to Vss but is booted by coupling. Thus, the potential difference between the gate and the channel is reduced to approximately Vpgm / 2, and no write operation is performed.

Since the multivalued memory narrows the threshold voltage distribution, the original verify level "v '" and the lower verify level "v *'" are set. A method is adopted in which an intermediate potential (between Vdd and Vss, for example 1V) is supplied to a bit line of a cell having a verify level greater than the verify level "v * '" and less than or equal to the verify level "v'", This decreases the recording speed. At this point, when the signal VREG is set to Vdd and the signal REG is set to intermediate potential + Vth (e.g. 1V + Vth), the bit line is set to Vss and the DDC is at a high level. At the right, the bit line is set to an intermediate potential. The bit line stays at Vss when the DDC is at the low level. When the bit line is set to Vdd, the bit line stays at Vdd.

When the write data is "0", the data in the memory cell changes to "2" as shown in Fig. 1A. When the write data is "1", the data in the memory cell remains as "0".

(First Page Verification Operation) (S16)

In recording the first page, the recording operation is performed until the verification level "v '" is reached as shown in Fig. 1A. Therefore, in the first step of the verify operation, as shown in Fig. 1A, the verify operation is performed using the potential "v * '" lower than the original potential "v'" of the word line in the verify operation. Then, in the second step, the potential of the word line is set to "v '". From now on, "*" means a potential lower than the original value.

First, a potential Vread for a read operation is given to an unselected word line and a selection line SGD in a selected block. In addition, in the data storage circuit 10 shown in FIG. 7, for example, Vdd + Vth is supplied to the signal BLPRE, and a predetermined voltage, for example, 1V + Vth, is set to set the signal VPRE to Vdd. Is supplied to the signal BLCLAMP, and the bit line is precharged to 1V.

Subsequently, the selection line SGS at the source side of the cell is set to a high level. The cell with a threshold voltage higher than the potential "v * '" is turned off. Thus, its bit line remains at a high level. In addition, the cell with the threshold voltage lower than the potential "v * '" is turned on. Therefore, its bit line is set to Vss.

Then, a predetermined voltage, for example Vdd + Vth, is supplied to the signal BLPRE to set the signal VPRE to Vdd. As a result, the junction node N3 of the TDC is precharged to Vdd. Then, the signal BLCLAMP is set to a predetermined voltage, for example, 0.9V + Vth, to turn on the transistor 61t. The node N3 of the TDC is set to a low level when its bit line is at a low level and to a high level when its bit line is at a high level.

Here, when the write operation is performed, data representing the low level is stored in the DDC shown in FIG. When the write operation is not performed, data representing the high level is stored in the DDC. Therefore, when the signal VREG is set to Vdd and the signal REG changes to the high level, the node N3 of the TDC is forcibly changed to the high level only when the write operation is not performed. After this operation, data in the PDC is transferred to the DDC, and the potential of the TDC is transferred to the PDC. The high level signal is latched in the PDC only when data is not written in the cell and data "2" is written in the cell and the threshold voltage of this cell reaches the verifying potential "v * '". In addition, the low-level signal is latched to the PDC only when the threshold voltage of the cell has not reached "v * '".

Then, when the voltage of the word line is increased from "v * '" to "v'", the cell having a threshold voltage lower than "v '" is turned on, and its bit line is set to Vss.

Then, a predetermined voltage, for example Vdd + Vth, is supplied to the signal BLPRE to set the signal VPRE to Vdd, whereby the junction node N3 of the TDC is precharged to Vdd. Thereafter, the signal BLCLAMP is set to a predetermined voltage, for example, 0.9 V + Vth, to turn on the transistor 61t. The node N3 of the TDC is set to a low level when its bit line is at a low level and to a high level when its bit line is at a high level.

Here, when the write operation is performed, data representing the low level is stored in the DDC shown in FIG. In the case where the write operation is not performed, data representing the high level is stored in the DDC. Therefore, when the signal VREG is set to Vdd and the signal REG changes to the high level, the node N3 of the TDC is forcibly set to the high level only when no write operation is performed. After this operation, data in the PDC is transferred to the DDC, and the potential of the TDC is transferred to the PDC. The high-level signal is latched in the PDC only when data is not written in the cell and data "2" is written in the cell and the threshold voltage of this cell reaches the verifying potential "v '". In addition, the low level signal is latched to the PDC only when the threshold voltage of the cell has not reached " v '.

As a result, the DDC is set to a high level when the threshold voltage of the cell exceeds "v * '" and when the write operation is not selected. When the write operation is performed and when the threshold voltage of the cell is not greater than "v * '", the DDC is set to the low level. When the threshold voltage of the cell exceeds "v '" and when the write operation is not selected, the PDC is set to a high level. When the write operation is performed and when the threshold voltage of the cell is not greater than "v '", the PDC is set to the low level.

When the PDC is at the low level, the write operation is performed again, and this program operation and the verify operation are repeated until the data in all the data storage circuits 10 are changed to the high level (S18 to S15). However, in the case of a write operation for a cell in which the PDC is at a low level and the DDC is at a high level, that is, a cell that is not less than "v * '" and not greater than "v'", suppressing the write speed. An intermediate potential is applied to its bit line.

The program operation is executed in such a manner that the value of the program execution count counter PC cleared in step S14 does not exceed the maximum number of programs.

(Adjacent cell program)

As shown in Fig. 8, after writing 1-bit data in the first page of the memory cell 1, the data is written in the first page of the memory cell 2 adjacent to the memory cell 1 in the word direction. Operation, writing data in the first page of the memory cell 3 adjacent to the memory cell 1 in the bit line direction, and writing in the first page of the memory cell 4 adjacent to the memory cell 1 in the diagonal direction. The operation of recording data is performed sequentially. When these write operations are performed, the threshold voltage of the memory cell 1 is increased due to the inter-floating-gate capacity according to the write data. Thus, as shown in FIG. 1B, the threshold voltage distribution of each of the data "0" and the data "2" in the memory cell 1 extends toward a higher potential.

Subsequently, in the fifth write operation shown in FIG. 3, 1-bit data is written to the second page of the memory cell 1.

(2nd page program)

1C and 1D show the recording order of the second page program. In the case of the prior art shown in Fig. 2, data is written to the second page to simultaneously achieve the threshold voltage levels "a '", "b'" and "c '". However, for this embodiment, in the first step of the second page program, data is written to achieve the threshold voltage level "b '" in the cell in which the data is written on the first page at the threshold voltage level "v'". Then, in the second step, a write operation is performed using the input data of the second page to simultaneously achieve the threshold voltage levels "a '" and "c'". Alternatively, in the first step of the second page program, data is written to achieve threshold voltage levels "b '" and "c'" in the cell where data is written on the first page at threshold voltage level "v '". do. Then, in the second step, a write operation is performed to achieve the threshold level "a '". That is, data "2" and "3" can be recorded in the first step, and data "1" can be recorded in the second step.

10 is a flowchart showing an example of a second page program. In the second page program, the two pages shown in Fig. 4 are likewise first selected according to the address. At the same time, the page buffer is reset (S21).

Subsequently, write data is input externally and stored in the SDC in all data storage circuits (S22). When data " 1 " (write operation is not executed) is input externally, the node N2a of the SDC in each data storage circuit 10 enters the low level. When data "0" (write operation is executed) is input from the outside, the node N2a enters a high level.

(Internal Data Read Operation) (S23)

First, before writing data into the cell, it is necessary to determine whether the data of the first page of the memory cell is "0" or "2". Thus, an internal read operation of reading data in the memory cell is performed. The internal data read operation is entirely the same as the read operation. In the determination as to whether the data in the ordinary memory cell is "0" or "2", the potential "b" at the time of the read operation is supplied to the selected word line. However, in the program operation for the first page, data " 2 " is written, leading to " v '" lower than the normal threshold voltage. Thus, in some cases, the threshold voltage of the memory cell may be lower than the potential "b '". Thus, in the internal data read operation, the potential "a" is supplied to the word line to perform the read operation.

11A shows data in a data cache after an internal data read operation. That is, when writing the data of the first page, the data in the PDC is at the low level ("0") when no data is recorded and at the high level ("1") when the data is recorded.

(First setting of data cache) (S24)

The data stored in each data cache is then as shown in Fig. 11B by manipulating each data cache. That is, the operation of transmitting or copying data in the SDC, DDC, DDCQ, or PDC shown in FIG. 7 may set the data in each data cache as shown in FIG. 11B. Since the operation of each data cache is not essential in this embodiment, description thereof is omitted.

During this setting for each data cache or during an internal read operation, the data in the flag cell is also loaded. In addition, the program execution count counter PC is cleared.

Data "1" of the memory cell is written in the first flag cell FC1, and data "2" of the memory cell is written in the second flag cell FC2. Thus, each data cache associated with each memory cell and each flag cell is also set according to the data written in the memory cell.

In the first step of the second page write operation, data is written to achieve level "b" or more for the cell in which the first page data is written at the verify level "v '", and based on the second page write data The write operation that achieves "a" is not executed. As a result, the write data of the first page and the write data of the second page are controlled so that their threshold voltage distributions do not overlap.

(First step) (S25)

Subsequently, data is written to the memory cell. First, the signal BLC1 is set to Vsg (Vdd + Vth, for example 2.5V + Vth). Then, the bit line is set to Vss when the PDC has data "0", and the bit line is set to Vdd when the PDC has data "1". Then, after the signal BLC1 is set to Vss, the signal VREG is set to Vdd and the signal REG is set to the intermediate potential + Vth (1V + Vth). As a result, when the bit line is set to Vss, the bit line is provided with the intermediate potential 1V.

Here, assuming that the selected word line has the potential of Vpgm and the unselected word line has the potential of Vpass, the write operation is not executed when the bit line has Vdd. In addition, when the bit line has Vss, a write operation is performed. When the bit line has the intermediate potential 1V, a small amount of data is recorded.

(First stage verification operation)

Subsequently, a verify operation is executed. However, the verification operations S26 and S27 at the level "a" are omitted at this time. Therefore, in this example, the potential of the word line is first set to "b * '", and the write verify operation is executed (S28 and S29). This verification procedure is the same as that of the first page. The program operation and the verify operation are repeated until all PDCs change to the high level (S25, S28, S29, S32, and S33). When the write operation is completed, the data in each data cache becomes as shown in Fig. 12A. In addition, when the recording operation is completed, control proceeds from step S32 to step S34. In step S34, when it is assumed that there is a second program, control proceeds to step S24.

(Second setting of data cache)

Then, data to be stored in each data cache is set as shown in FIG. 12B by manipulating each data cache.

Data "1" in the memory cell is written in the first flag cell FC1, and data "2" in the memory cell is written in the second flag cell FC2. Thus, each data cache connected with the first and second flag cells FC2 is also set in accordance with the data written in the memory cell as shown in Fig. 12B. However, since the operation of writing data "2" in the memory cell and the second flag cell FC2 has been completed, PDC = 1 is achieved.

(Second stage) (S25)

Subsequently, data is written to the memory cell. First, the signal BLC1 is set to Vsg. As a result, the bit line has a potential Vss when the PDC has data "0", and the bit line has a potential of Vdd when the PDC has data "1". Then, after the signal BLC1 is set to Vss, the signal VREG is set to Vdd and the signal REG is set to the intermediate potential + Vth (1V + Vth). As a result, when the bit line has a potential Vss, the bit line is provided with an intermediate potential 1V.

Here, assuming that the selected word line has the potential Vpgm and the unselected word line has the potential Vpass, the write operation is not performed when the bit line has the potential Vdd. In addition, a write operation is performed when the bit line has the potential Vss, and a small amount of data is written when the bit line has the intermediate potential 1V.

13A shows data in each data cache after the second step of the second page write operation.

(Verification Operation at Second Step Verification Level "a") (S26 and S27)

After the program operation, the verify voltages " a * '" and " a' " are sequentially set in the word line to execute the write verify operation. The verification procedure is the same as that of the first page, but the cell in which data "2" or "3" is recorded is also passed in this verification operation. Thus, instead of setting the signal VPRE and the signal VREG to high level and charging the TDC to Vdd, the SDC is set to high level and the TDC is charged to Vdd only in the memory cell in which data " 1 " is written. . According to this operation, this verify operation does not skip the memory cell in which data "2" or "3" is written.

(Verification Operation in Second Step Verification Level "b") (S28 and S29)

Subsequently, the verify voltages "b * '" and " b' " are sequentially set for the word line and the write verify operation is executed. The verification procedure is the same as that of the first page, but the memory cell in which data "3" is written also passes this verification operation. Therefore, instead of setting the signal VPRE and the signal VREG to high level and charging the TDC to Vdd, the TDC of the memory cell in which the signal REG is set to high level and data "2" is written to Vdd. Is charged. According to this operation, the memory cell in which data "3" is written is not passed in this verifying operation. Data "2" was recorded in the first step. Therefore, the verify operation at this second stage verify level "b" is not performed because the write data "2" does not exist.

(Verification Operation in Second Step Verification Level "c") (S30 and S31)

Subsequently, the verify voltages "c * '" and " c' " are set sequentially for the word line, and the write verify operation is executed. The verification procedure is the same as in the first step.

The program operation and the verify operation are thus repeated until the data in all the PDCs changes to "1". During the verify operation, the operation of writing data "1" ends earlier. Therefore, if there are no cells to which data "1" is to be written, the program verify (a * 'and a') operations are not executed. In addition, when there are no cells to which data "2" is to be written, program verify (b * 'and b') operations are not performed.

Fig. 14 shows an example of the operation of the word line WL, the bit line BL and the selection gate line SGD in the verify operation. The bit line BL is charged, and the potential of the word line WL is set to "a * '". Subsequently, in order to turn on the selection gate S1, the selection gate line SGD is set to a high level, and the bit line BL is discharged. As a result, the verify operation is performed at the potential "a * '" of the word line WL. Subsequently, the potential of the word line WL is set to "a '" to discharge the bit line, and the verify operation is performed to the potential "a'" of the word line WL.

(First page read operation)

15 shows a flowchart of the first page reading operation. First, an address is specified, and two pages shown in FIG. 4 are selected. As shown in Figs. 1B and 1C, the threshold voltage distribution changes before and after writing the second page. Therefore, in order to perform the read operation, the potential of the word line is first set to "b", and it is determined whether the data in the second flag cell FC2 is "0" or "1" (S41 and S42). If it is found by the determination that a plurality of second flag cells FC2 are present, it is determined as "0" or "1" based on the majority vote of these cells.

When the data read out from the second flag cell FC2 is "0" (the data in the memory cell is "2"), the second page is written. Thus, the threshold voltage distribution of the cell is as shown in FIG. 1C. In order to determine the data in such a cell, it may be sufficient to set the potential of the word line to "b" to perform a read operation. However, the result of performing the read operation with the word line potential "b" is already read into the data storage circuit 10. Therefore, it is preferable to output the data stored in the data storage circuit 10 to the outside.

On the other hand, when the data read from the second flag cell FC2 is "1" (the data in the memory cell is "0"), the second page is not written. Thus, the threshold voltage distribution of the cell is as shown in FIG. 1A or 1G. In order to determine such data in the memory, the potential of the word line is set to " a " to perform a read operation (S44). The data is thus read into the data storage circuit 10. Thereafter, the data read into the data storage circuit 10 is output to the outside (S43).

(2nd page read operation)

16 shows a flowchart of the second page read operation. In the second page read operation, an address is first assigned, and the two pages shown in FIG. 4 are selected. As shown in Figs. 1B and 1C, the threshold voltage distribution changes before and after writing the second page. However, a threshold voltage distribution as shown in Fig. 1E is obtained after writing the second page. Therefore, in order to perform the read operation, the potential of the word line must be changed twice to "c" and "a".

First, the word line potential is set to " c " to execute the read operation (S51). Subsequently, the word line potential is set to " a " to perform a read operation (S52). If the threshold voltage of the cell is lower than the word line potential "a" or higher than the word line potential "c", the data is set to "1". When the threshold voltage of the cell is higher than the word line potential "a" or lower than the word line potential "c", the data is set to "0". "1" must be output as the second page data before writing the second page. However, the threshold voltage distribution shown in FIG. 1A is obtained. Thus, when the same read operation as that after writing the second page is executed, the output data can be made " 0 ". Therefore, it is determined whether the data in the first flag cell FC1 is "0" or "1" (S53). As a result, when the data in the first flag cell FC1 is "1" and the second page is not written, the output data is fixed as "1" (S54). In addition, when the data in the flag cell is "0", the read data is output (S55).

Data is read from the memory cell in accordance with the sequences shown in FIGS. 15 and 16. However, as described above, when the power is turned off while writing the second page and the second page data is not normally written, the first page data read from the memory cell may be inaccurate. Therefore, the operation when reading the first page data will now be described.

(Reading procedure)

17 is a flowchart showing a reading procedure from the user side. For example, a read command is input from the non-shown user side controller to the NAND flash memory via the controller 9 shown in FIG. 3 (S61). As a result, data in the memory cell according to the address is read out and transferred to the SDC (S62). Subsequently, data read from the NAND flash memory to the controller 9 are sequentially transferred. The controller 9 executes the calculation to decode the ECC (S63). After all the data has been transmitted, the controller 9 determines whether there is an error in the data or whether this error can be corrected using ECC (S64). If there are no errors or these errors can be corrected using ECC, the data read is normal. If the error cannot be corrected using ECC, there is a possibility that abnormal termination has occurred during the recording operation. Recording defects are classified into the following three types as in the prior art.

(1) An error occurs while writing the first page, and the first page data cannot be read.

(2) An error occurs while writing the second page, and the first page data cannot be read.

(3) An error occurs while writing the second page, and the second page data cannot be read.

Since the cell in the write operation has an error in (1) and (3), the read operation is of course not possible. The first embodiment solves the case of (2). That is, the destruction of the first page data is avoided, and therefore the first page data can be read.

In the first embodiment, the results for the individual recording steps can be classified as follows.

(1) Write first page (flag cell: remains erased)

In the case of recording failure in the main body cell (cells other than the first and second flag cells and the ECC cell)

Failed to read the first page due to a normal read operation (word line potential "a")

Failed first page read by using special command and word line potential "a"

In case of successful recording in the main body cell

Successful first page read by normal read (word line potential "a")

First page read success by using special command and word line potential "a"

(2) write data to adjacent cells

(3) Second step of the operation of writing the second page (second flag cell FC2 → potential " b ")

In the case of a write failure in the second flag cell FC2 and a write failure in the main body cell

Successful first page read by normal read (word line potential "a")

First page read success by using special command and word line potential "a"

In the case of successful data writing in the second flag cell FC2 and writing failure in the main body cell

Failed to read first page due to normal read (word line potential "b")

Successful first page read using special command and word line potential "a"

In the case of writing failure in the second flag cell FC2 and writing success in the main body cell

Successful first page read by normal read (word line potential "a")

First page read success by using special command and word line potential "a"

In the case of writing success in the second flag cell FC2 and writing success in the main body cell

Successful first page read by normal read (word line potential "b")

First page read success by using special command and word line potential "a"

(4) Second step of the operation of writing the second page (second flag cell FC2, potential "b" unchanged)

Successful first page read by normal read (word line potential "b")

Failed first page read by using special command and word line potential "a"

In the above relationship, when the first step of the second page program operation is interrupted, the read operation at the word line potential "b" in the case of a write success in the second flag cell FC2 and a write failure in the main body cell. Is executed. Thus, the read operation fails because the threshold voltage of the main body cell does not reach the potential "b".

In this case, therefore, as shown in step S65 of Fig. 17, a special read command (xxh + read command) is supplied from the outside regardless of the data in the flag cell. In response to this special command, a read operation is performed at the word line potential "a" (S66). Data read from the memory cell into the SDC is sequentially transferred to the controller 9. The controller 9 performs a calculation to decode the ECC (S67).

After all data has been sent to the controller 9, it is determined whether there is an error or whether such an error can be corrected using ECC (S68). As a result, when there is no error or this error can be corrected by the ECC, the read data is output (S69). In addition, when an error cannot be corrected using ECC, this error is regarded as an error caused by (1) or (3) or a deterioration of the cell due to neglect, etc., and therefore data cannot be read. (S70).

(Clear operation)

In the erase operation, the address is first addressed, and the block indicated by the dotted line in Fig. 4 is selected. When the erase operation is executed, the data in the memory cell becomes " 0 " and data " 1 " is output regardless of the read operation performed on both the first page and the second page.

According to the first embodiment, in the write operation of the second page, data is written to the adjacent cell after the first page is written, and data "2" having an extended threshold voltage distribution is set to the original threshold voltage, Then other data is recorded. Therefore, even when an error occurs in the second page recording, it is possible to prevent the data "0" or "2" recorded in the first page recording from being destroyed. Thus, the first page data can be read.

Note that the recording speed is lowered when the second page recording is performed in two stages, i.e., the first stage and the second stage. Therefore, for the user who can destroy the first page and want to perform the write operation at high speed, the write operation and the verify operation "b" of the memory cell data "2" are not executed in the first step, but in the second step. The recording operation can be performed. In the case of such a user, for example, another write command can be set, or the data for this user can be sent to the fuse circuit 7-1 provided in the control signal and control voltage generator circuit 7 to enable switching. Can be set.

13B shows data in each data cache when the first step of the second page write operation is omitted.

In addition, the conditions adopted for the write operation and the read operation according to the first embodiment can be set, for example, as follows.

· The power is cut off after the first page write and then the power is turned back on to perform the second page write.

· Consecutive writing of the first and second pages and discontinuous writing of the first and second pages are switched using a command.

The user wants the first page data not to be destroyed. In this case, when the writing method and the reading method according to the first embodiment have been previously set using the fuse circuit 7-1, no new command need be input.

(2nd Example)

According to the first embodiment, in the second page write, the data "0" to "1" of the memory cell are written to the first flag cell FC1, and the data "0" to "2" of the memory cell is the second. It is written to the flag cell FC2. However, when the threshold voltage distribution of the second flag cell FC2 illustrated in FIG. 1C is lower than the threshold voltage “c”, the first flag cell FC1 may be omitted.

18 shows the reading sequence of the second page in the second embodiment. The same reference numerals denote the same parts as in the first embodiment. In the case of the second embodiment, when dividing the output data, the data in the second flag cell FC2 is used instead of the data in the first flag cell FC1 (S71).

The second embodiment can achieve the same effect as that of the first embodiment. In addition, since the first flag cell FC1 can be omitted in the second embodiment, the configuration can be simplified.

(Third Embodiment)

According to the first embodiment, in the second page write, data "0" to "1" of the memory cell is written to the first flag cell FC1, and data "0" to "2" of the memory cell is the second. It is written to the flag cell FC2. However, like the write sequence of the memory cell, there are only writes of data "0" to "1" and writes of data "2" to "3". Therefore, writing data in the second flag cell FC2 may in some cases prevent the increase in the writing speed. Therefore, only the first flag cell FC1 is used without using the second flag cell FC2.

In this case, data is written only to the first flag cell FC1 in the second page program operation. The second page read sequence is as shown in FIG.

FIG. 19 is a flowchart showing a reading sequence of the first page in the third embodiment, wherein the same reference numerals denote the same parts as those in FIG. In the first page read, the data is first read at read level "a" (S41). When it is determined that data is recorded in the first flag cell FC1 as a result of the determination on the first flag cell FC1 (S42), the data of the second page is recorded. Therefore, data is read again at the read level "b" (S81). In addition, when data is not recorded in the first flag cell FC1, the data of the second page is not recorded. Therefore, the result of reading data at the read level "a" is output (S43).

(Reading procedure)

The reading procedure by the user is as shown in FIG. However, the relationship between the first page read, the first flag cell FC1 and the main body cell is as described below.

(1) First page (flag cell remains erased)

· In case of write failure in the main body cell

Failed to read the first page due to a normal read operation (word line potential "a")

Failed to read first page by using special command and word line potential "b"

In case of successful recording in the main body cell

Successful first page read by normal read operation (word line potential "a")

Failed to read first page using special command and word line potential "b"

(2) write data to adjacent cells

(3) Second step of the operation of writing data of the second page (the first flag cell FC1 remains in an erased state)

· In case of write failure in the main body cell

Successful first page read by normal read operation (word line potential "a")

In case of successful recording in the main body cell

Successful first page read by normal read operation (word line potential "a")

(4) Second step of the operation of writing the data of the second page (data is written in the first flag cell FC1 at the potential "a")

In the case of writing failure in the first flag cell FC1

Failed to read the first page due to a normal read operation (word line potential "a")

First page read success by using special command and word line potential "b"

In the case of successful writing in the first flag cell FC1

Successful first page read by normal read (word line potential "b")

First page read success by using special command and word line potential "b"

In the second step of the operation of writing the second page, when the first flag cell FC1 has a write failure, a read operation is performed at the word line potential "a". In the first step, data of the first page is recorded at the potential " b " However, in the second step, there is a possibility that the data of the second page is written beyond the potential "a". Therefore, reading data at the word line potential " a " fails.

In this case, therefore, as shown in step S65 of FIG. 17, a special command is supplied from the outside to the NAND flash memory, and a read operation is performed at the word line potential " b " regardless of the flag cells.

According to the third embodiment, data is written using only the first flag cell FC1 without using the second flag cell FC2. Thus, the writing operation of the second page can be improved. In addition, even when an error occurs in the second page write operation, the data of the first page can be read. Therefore, the reliability of the semiconductor memory device can be improved.

(Example 4)

According to the first, second and third embodiments, as shown in Fig. 10, the second page write operation is executed in the order of the first step and the second step. However, when the write operation in the adjacent cell shown in Fig. 1B ends, data may be written to achieve level "b" before the data of the second page is determined.

Therefore, after the write operation in the last adjacent cell, the data "2" can be continuously recorded at the maximum original threshold voltage "b '". As another alternative, a new command can be supplied from the outside, and data "2" can be written with the maximum original threshold voltage "b '" after the write operation in the last adjacent cell in response to this command.

According to the fourth embodiment, since the data "2" can be written to achieve the original threshold voltage "b '" before the second page data is determined, the speed of the entire write operation can be increased. In the first, second, and third embodiments, the speed of writing the first page data is much higher than the speed of writing the second page data, and thus there is an imbalance. However, in the case of the fourth embodiment, the speed of writing the second page data can be increased, whereby the speed of writing the data in the first page can be almost the same as the speed in the second page.

(Example 5)

According to the first to fourth embodiments, in recording data on the second page, the data of the first page is recorded in the first step with the potential "b '" or more, and then based on the recording data of the second page. A write operation is performed on the erase cell at the potential "a '". This operation prevents the threshold voltage distribution of the first page data from overlapping with the threshold voltage distribution of the second page data. However, similarly to the write operation in the main body cell, data is recorded in the flag cell in the first step or the second step. Thus, when a correction using ECC cannot be performed in the read sequence, a read operation is performed using a special read command.

However, for example, the first page data is written to achieve the potential "b '" in the first step of the second page write, and then the data is written in the flag cell in the second step. Subsequently, in the third step, data is written at the potential "a '" into the erase cell based on the write data of the second page. When this operation is performed, it is possible to prevent the threshold voltage distribution of the first page data from overlapping with the threshold voltage distribution of the second page data. In addition, performing a read operation according to the data in the flag cell can read the data of the first page without using the ECC.

For example, when the first flag cell FC1 is used as, for example, in the third embodiment, when the recording operation is interrupted due to the interruption of power or the like during the writing operation of the second page, The relationship between one page reading, the first flag cell FC1 and the main body cell is as follows.

(1) First page (first flag cell is in an erased state)

· In case of write failure in the main body cell

Failed to read the first page due to a normal read operation (word line potential "a")

In case of successful recording in the main body cell

Successful first page read by normal read operation (word line potential "a")

(2) write to adjacent cells

(3) First step of the operation of writing the second page (the first flag cell is in the erased state, and data is written to the main body cell to achieve the potential "b '").

· In case of write failure in the main body cell

Successful first page read by normal read operation (word line potential "a")

In the case of successful data recording in the main body cell

Successful first page read by normal read operation (word line potential "a")

(4) Second step of the operation of writing the second page (data is written to the first flag cell FC1 to achieve a threshold voltage higher than the threshold voltage in the potential "a" or the erased state).

In the case of writing failure in the first flag cell FC1

Successful first page read by normal read operation (word line potential "a")

In the case of successful writing in the first flag cell FC1

Successful first page read by normal read operation (word line potential "b")

(5) Third step of the operation of writing the second page (data is recorded in the main body cell at the potential "a '")

· In case of write failure in the main body cell

Successful first page read by normal read operation (word line potential "b")

In case of successful recording in the main body cell

Successful first page read by normal read operation (word line potential "b")

As described above, according to the fifth embodiment, data is written to the first flag cell FC1 to achieve the potential "a" in the second stage of the write operation on the second page. Setting the word line potential "a" or "b" can read data from the first page regardless of the failure or success of data writing in the first flag cell FC1. Thus, the data of the first page can be read without using the ECC. Thus, data can be read without waiting for the computation time required to decode the ECC, thereby enabling high speed reading.

Additional advantages and modifications can readily be made to those skilled in the art. Accordingly, the invention is not to be limited in terms of the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general concept of the invention as defined by the appended claims and their equivalents.

According to the present invention, a semiconductor memory device capable of storing multi-value data in a single memory cell can be provided.

Claims (20)

A memory cell array in which a plurality of memory cells are arranged in a matrix form, each memory cell being connected to a word line and a bit line and storing n values (where n is a natural number not less than 3); a recording unit for recording n-valued data in the memory cell in which k values (k <n) are stored; A reading section which sets a potential of the word line and reads data from the memory cells in the memory cell array, and A control section for changing the potential of the word line supplied to the reading section when reading the k-valued data when the data read by the reading section contains an uncorrectable error Semiconductor memory device comprising a. The method of claim 1, And the memory cell array has a storage area for storing an error correction code. The method of claim 1, The control unit operates the reading unit in response to a first read command, and reads in response to a second read command different from the first read command when the data read by the reading unit contains the uncorrectable error. A semiconductor memory device for operating a part. a memory cell that stores n values, where n is a natural number not less than 3, and A control unit for controlling the memory cell, The control unit sets the threshold voltage of the memory cell from the first threshold voltage to the first threshold voltage or the second threshold voltage (the first threshold voltage <the second threshold voltage) by a first write operation, and the memory If the threshold voltage of the cell is the second threshold voltage, the threshold voltage of the memory cell is set to be equal to or greater than a third threshold voltage (the second threshold voltage ≤ the third threshold voltage) by a second write operation, and When the threshold voltage of the memory cell is the first threshold voltage, the threshold voltage of the memory cell is changed to the first threshold voltage or the fourth threshold voltage by the third write operation (the first threshold voltage <the fourth threshold voltage). Voltage). The method of claim 4, wherein Further comprising a flag memory cell, And the controller is configured to perform a write to set a threshold voltage of the flag memory cell selected simultaneously with the memory cell by the second write operation to be greater than or equal to the third threshold voltage from the first threshold voltage. The method of claim 4, wherein The control unit performs a read operation on whether the threshold voltage of the memory cell is greater than or equal to the third threshold voltage in a first read operation, and when the data read by the first read operation includes an uncorrectable error. And a read operation as to whether the threshold voltage of the memory cell is greater than or equal to the second threshold voltage. The method of claim 4, wherein Further comprising a flag memory cell, And the controller is configured to perform a write to set a threshold voltage of the flag memory cell selected simultaneously with the memory cell by the third write operation to be greater than or equal to the fourth threshold voltage from the first threshold voltage. The method of claim 7, wherein The controller reads the threshold voltage of the memory cell in which data is written by the third write operation, and corresponds to the read threshold voltage when the threshold voltage of the flag memory cell is not less than the fourth threshold voltage. And outputs fixed data when the threshold voltage of the flag memory cell is lower than the fourth threshold voltage. The method of claim 7, wherein The control unit performs a read operation on whether the threshold voltage of the memory cell is greater than or equal to the fourth threshold voltage in the first read operation, and the data read by the first read operation includes an uncorrectable error. And if the threshold voltage of the memory cell is greater than or equal to the third threshold voltage. The method of claim 4, wherein Further comprising a flag memory cell, The control unit may set the threshold voltage of the flag memory cell selected simultaneously with the memory cell by the third write operation from the first threshold voltage to the third threshold voltage or the fourth threshold voltage (the first threshold voltage <the first threshold voltage). 4 threshold voltage) or more, and when the threshold voltage of the memory cell is the first threshold voltage, writing is performed to set the threshold voltage of the memory cell to the first threshold voltage or the fourth threshold voltage. A semiconductor memory device. The method of claim 4, wherein The controller may be configured to set the threshold voltage of the memory cell to the third threshold voltage (the second threshold voltage ≤ the third threshold) when the threshold voltage of the memory cell is the second threshold voltage. Voltage) or the fourth threshold voltage (the third threshold voltage <the fourth threshold voltage), and when the threshold voltage of the memory cell is the first threshold voltage, the memory cell by the third write operation. And write to set the threshold voltage of the threshold voltage to the first threshold voltage or the fifth threshold voltage (the first threshold voltage <the fifth threshold voltage <the third threshold voltage). The method of claim 4, wherein The controller may be configured to set the threshold voltage of the memory cell to the third threshold voltage (the second threshold voltage ≤ the third threshold voltage) by the second write operation when the threshold voltage of the memory cell is the second threshold voltage. ) And when the threshold voltage of the memory cell is the third threshold voltage, the threshold voltage of the memory cell is determined as the third threshold voltage or the fifth threshold voltage by the third write operation. Set the threshold voltage <the fifth threshold voltage, and when the threshold voltage is the first threshold voltage, set the threshold voltage of the memory cell to the first threshold voltage or the fourth threshold voltage (the first threshold voltage < And write to set the fourth threshold voltage <the third threshold voltage). The method of claim 4, wherein And the controller performs a write operation to set the threshold voltage of the memory cell to the third threshold voltage according to a command after the first write operation. a memory cell that stores n values, where n is a natural number not less than 3, A first flag memory cell, A second flag memory cell, and A control unit controlling the memory cell and the first and second flag memory cells; The control unit sets the threshold voltage of the memory cell from the first threshold voltage to the first threshold voltage or the second threshold voltage (the first threshold voltage <the second threshold voltage) by a first write operation, and the memory When the threshold voltage of the cell is the second threshold voltage, the threshold voltage of the memory cell is set to be equal to or greater than a third threshold voltage (the second threshold voltage ≤ the third threshold voltage) by a second write operation. Write is performed to set the third threshold voltage in a two flag memory cell, and when the threshold voltage of the memory cell is the first threshold voltage, the threshold voltage of the memory cell is determined by a third write operation. Write is performed to set a first threshold voltage or a fourth threshold voltage (the first threshold voltage <the fourth threshold voltage), and the threshold voltage of the memory cell is the third threshold. In the case of a threshold voltage, a write operation is performed to set one of the third threshold voltage and the fifth threshold voltage (the third threshold voltage <the fifth threshold voltage) in the memory cell and the first flag memory cell. 4 A semiconductor memory device for writing a threshold voltage. The method of claim 14, The control unit performs a first read operation relating to whether the threshold voltage of the memory cell is greater than or equal to the third threshold voltage, and performs a second read operation related to whether the threshold voltage of the memory cell is greater than or equal to the fourth threshold voltage. Performing a read operation, and outputting the data read by the second read operation when the read data has no error or has a correctable error. The method of claim 14, When the threshold voltage of the second flag memory cell is lower than the third threshold voltage, the first flag memory cell is not used. The controller reads the threshold voltages of the memory cells written by the second and third write operations, and reads the threshold voltage when the threshold voltage of the second flag memory cell is not less than the fourth threshold voltage. And outputs data corresponding to the data and outputs fixed data when the threshold voltage of the second flag memory cell is less than the fourth threshold voltage. The method of claim 14, The controller performs the first read operation to determine whether the threshold voltage of the memory cell is greater than or equal to the fourth threshold voltage without writing to the second flag memory cell in the second write operation. Perform the second read operation to determine whether the threshold voltage of the memory cell is greater than or equal to the third threshold voltage, and output a result when data is written to the first flag memory cell, And outputting a result of the determination made in the first read operation when data is not recorded in the first flag memory cell. The method of claim 14, And the controller performs a write operation to set the threshold voltage of the memory cell to the third threshold voltage according to a command after the first write operation. The method of claim 14, The control unit may set the threshold voltage of the first flag memory cell selected simultaneously with the memory cell by the third write operation from the first threshold voltage to the fourth threshold voltage (the first threshold voltage <the fourth threshold voltage). And setting the threshold voltage of the memory cell to the first threshold voltage or the fourth threshold voltage by a fourth write operation when the threshold voltage of the memory cell is the first threshold voltage. A semiconductor memory device performing the. The method of claim 15, And the memory cell is included in the memory cell array, wherein the memory cell array has a storage area in which an error correction code is stored.

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