KR100733466B1 - Delay locked loop circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit of a synchronous DRAM, and more particularly to a power down mode for low power operation of a semiconductor. The present invention relates to a circuit for operation of a stable delay locked loop (DLL) circuit during down mode operation. The present invention is to prevent the interruption of the phase update operation that may occur when the power down mode is entered, and until the clock signal indicating the last period of the phase update is activated. Delays the clock buffer off.

DLL, clock buffer, power down mode, phase update, PRE CHARGE, clock buffer controller

Description

DELAY LOCKED LOOP CIRCUIT}

1 is a block diagram for explaining the configuration of a delay locked loop circuit according to the prior art.

2 is a block diagram for explaining the configuration of a delay locked loop circuit of the present invention;

3 is a circuit diagram showing a power down controller and a clock buffer controller of the present invention together.

4 is a circuit diagram illustrating another embodiment of a power down controller and a clock buffer controller of the present invention.

200: control means 220: power down mode control unit

240: clock buffer control unit 242: signal delay unit

244 logic unit 246 reset unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit of a synchronous DRAM, and more particularly to a power down mode for low power operation of a semiconductor. The present invention relates to a delay locked loop (DLL) circuit that performs stable operation during down mode operation.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using fixed internal clock signals in synchronization with external clock signals input from external devices such as memory controllers. Do this. This is because the time synchronization between the reference clock signal and the data is very important for stable data transfer between the memory and the memory controller. In other words, for reliable transmission of data, the data must be located at the edge or center of the clock accurately by back-compensating the time that the data is loaded on the bus from the clocks of the components transmitting the data. Because. The clock synchronizing circuit that performs this role includes a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit, and frequency multiplies when the frequency of the external clock signal and the internal clock signal are different. Since the function should be used, PLL is mainly used. In the case where the frequency of the external clock signal and the internal clock signal are the same, most of them use a delay locked loop DLL.

The delay lock loop (DLL) circuit compensates for the clock delay component that occurs in the process of outputting the clock signal to the data output terminal of the semiconductor memory device to generate an internal clock signal, thereby outputting the clock signal used for the final data input / output. Synchronize the signal. Since the delay locked loop circuit has less noise than the phase locked loop circuit and can be implemented with a small area, it is common to use a delay locked loop circuit as a synchronous circuit in a semiconductor memory device. Among them, the most recent technology includes a register that can store a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register when the power is turned off, and when the power is applied again, the fixed delay value stored in the register is loaded to fix the clock. Register-controlled DLL loops, which can reduce the time required for initial clock lock, are most widely used.

1 is a block diagram illustrating a configuration of a delay locked loop (DLL) according to the prior art.

As shown in FIG. 1, the delay locked loop circuit DLL is largely composed of a DLL clock buffer control 10, a DLL clock buffer 20, a first phase delay unit & a delay line < RTI ID = 0.0 > Delay shift control block (30), second phase delay & delay controller (40), preclock duty controller (PREDCC: Pre Duty cycle correction, 50), clock duty controller (DCC: duty cycle correction, 60), delay replication Replica delay (70), phase detector (80), mode generator (90), delay lock loop (DLL control, 100), clock generator (Clock generator, 110), output driver (OUTdriver, 120).

The clock buffer control unit 10 includes a signal having a reverse signal ckeb_com of the clock enable signal and a power down mode information of the mode register setting MRS, and a signal having precharge information. ) And outputs a clock buffer enable signal (clkbuf_enb) that controls the clock buffer 20. When there is no read / write operation of DRAM for low power operation of DRAM, power-down mode (PD Mode: Power) is applied due to the low logic value (Low) of the clock enable signal (CKE). down mode). At this time, the clock buffer unit 20 does not generate an internal clock signal, thereby turning off the power for current saving of the delay locked loop DLL.

The clock buffer unit 20 receives and buffers an external clock signal in response to the clock buffer enable signal clkbuf_enb, thereby first and second internal clock signals clkin1 and clkin2 in phase and a reference internal clock signal refclk. And a third internal clock signal contclk.

The first phase delay unit & delay controller 30 phases the first internal clock signal clkin1 in response to the first fixed state signal fast_mode_end and the second fixed state signal lock_state output from the mode generator 90. Delay to output the first internal delay clock signal mixout_r.

The second phase delay unit & delay controller 40 phases the second internal clock signal clkin2 in response to the third fixed state signal fast_mode_endf and the fourth fixed state signal lock_statef output from the mode generator 90. Delay is output as the second internal delay clock signal mixout_f.

The preclock duty controller 50 buffers the first internal delay clock signal mixout_r and outputs the rising clock rclk, and buffers and inverts the second internal delay clock signal mixout_f to poll the falling clock fclk. Will print Here, the duty of the rising clock rclk and the falling clock fclk has a complementary value. That is, when the high pulse width of the external clock is large, the high pulse width of the rising clock rclk is large while the high pulse width of the falling clock fclk is small.

The clock duty controller 60 receives a rising clock rclk and a polling clock fclk having a complementary clock duty, adjusts a clock duty of the clock, and adjusts a rising feedback clock ifbclkr and a falling feedback clock ififlklkf. Will print

The delay replication model unit 70 inputs the internal rising feedback clock ifbclkr and the internal polling feedback clock ifbclk to the clock outside the chip until the phase delay unit and the output clock of the phase delay unit are outside the chip. By modeling the delay elements of the outputted compensated rising feedback clock (fbclkr) and the compensated polling feedback clock (fbclkf) to compensate for the time difference between the external clock and the actual internal clock. Accurate delay factors determine the distortion value of the delay fixed line circuit performance, and the delay replication model unit 70 may reduce, simplify, or use the basic circuit as it is. In fact, the delay replication model unit 70 models a clock buffer, a delay locked loop clock driver, an R / F divider, and an output buffer.

The phase comparator 80 outputs the compensated rising feedback clock fbclkr and the compensated falling feedback clock output from the delay replication model unit 70 and the reference internal clock signal refclk output from the clock buffer unit 20, respectively. Compare and output a phase detection signal. In general, to reduce the power consumption of the delay locked loop circuit, the frequency from the external clock is lowered through a divider.

The mode generator 90 uses the first position comparison control signal fine output from the phase comparator 80, the first coarse delay control signal FM_pdout, and the first fine delay control signal coarse. A first fixed state signal fast_mode_end and a second fixed state signal lock_state indicating that the clock is delayed by the delay unit & delay control unit 30, and output from the phase comparator 80; The clock is fixed by the second phase delay unit & delay control unit 40 using the second position comparison control signal finef, the second coarse delay control signal FM_pdoutf, and the second fine delay control signal coarsef. A third fixed state signal fast_mode_end and a fourth fixed state signal lock_state are output.

Depending on the output logic values of the first and fourth fixed state signals output from the mode generator 90, the speed of phase update performed by the delay locked loop circuit DLL varies (where phase update is a delay locked loop circuit). (DLL) means that the compensated rising feedback clock (fbclkr) and the compensated polling feedback clock are tracked by comparing the phase difference between the reference internal clock signal (refclk) to be determined. same.

When the phase difference between the reference internal clock signal refclk, the compensated rising feedback clock fbclkr, and the compensated falling feedback clock fbclkf is large, the first fixed state signal fast_mode_end and the third fixed state signal fast_mode_endf are ' Maintaining the low logic value low, the phase delay & delay controller 30 receives four unit delays at once in the phases of the compensated rising feedback clock fbclkr and the compensated falling feedback clock fbclkf. Shift by (unit delay) When the phase difference is less than four unit delays, the first fixed state signal fast_mode_end and the third fixed state signal fast_mode_endf maintain a 'high' logic value and a compensated rising feedback clock. The phase of fbclkr and the compensated polling feedback clock fbclkf are shifted by two unit delays at a time. When the phase difference is less than one unit delay, the second fixed state signal lock_state and the fourth fixed state signal lock_statef are raised from the low logic value high to the high logic value feedback signal. Fine-turn the phase of. When the phase is in phase, the clock duty controller 60 is enabled by the phase update locking information signal DCC_ENb, and the phase update operation is terminated (compensated with the compensated rising feedback clock fbclkr. The polling feedback clock (fbclkf) is controlled differently and is controlled together after the phase update is locked.)

The delay locked loop controller 100 outputs a reset signal for controlling the operation of the delay locked loop circuit DLL in response to the DLL reset signal dll_resetb and the DLL deactivation signal dis_dll applied from the outside of the memory.

The clock generator 110 receives the third internal clock signal contclk and the phase update locking information signal DCC_ENb from the clock buffer unit 20 to inform the start of the phase update period when the power down mode exits. A second clock pulse8_11 indicating a pulse2 and an end is output.

The output driver 120 buffers and outputs the rising feedback clock fbclkr and the compensated falling feedback clock fbclkf output from the clock duty controller.

When the slow down loop slowly exits the power down mode from the delay locked loop circuit DLL having the structure as shown in FIG. 1, the delay locked loop circuit DLL is applied at the time of entering the precharge power down mode. Since it is turned off, the internal clock of the delay locked loop circuit DLL is turned on / off by controlling the operation of the clock buffer on / off. When the internal clock of the delay locked loop (DLL) is turned off, all of the operations inside the delay locked loop (DLL) are suspended, and the operation is performed after the precharge power down mode exit. To get started. In this case, the following problem occurs.

First, according to the precharge power down entry timing, the precharge power down mode exit with the data compared before the precharge power down entry entry. After exiting, a phase update of the phase delay unit 40 may occur.

Second, after the precharge power down mode exit, the internal clock of the delay locked loop (DLL) is turned on, and the reference internal clock signal (refclk) and the compensated rising feedback clock that enter the phase comparator 80 are turned on. (fbclkr) and the compensated polling feedback clock (fbclkf) do not come in at the same time and the reference internal clock signal (refclk) comes in earlier, resulting in erroneous information and a phase update with this information. Can be.

Accordingly, the present invention has been proposed to solve the above-described problem, and a clock buffer of a delay locked loop circuit (DLL) in a power down mode entry in a normal mode performing phase update is Even when it is off, that is, even when the clock buffer of the delay locked loop DLL is turned off during the phase update operation, the phase update being performed is performed. An object of the present invention is to provide a delay locked loop (DLL) device and a method of a semiconductor memory device in which a clock buffer of a delay locked loop (DLL) is turned off after an update is completed.

A synchronous memory device having a normal mode and a power down mode, wherein the power down mode does not perform a phase update and exits the power down mode. (power down mode exit) a delay locked loop for generating a DLL clock by frozen locking information; A clock generator configured to generate a clock for indicating a start (pulse2) and an end (pulse8_11) of a phase update period in the normal mode; And after a clock pulse 11_11 indicating the end of the phase update period is input to obtain a margin of a phase update time when the power down mode entry is entered in the normal mode. A synchronous memory device is provided that includes control means for turning off a phase update operation of a delay lock loop (DLL).

According to another aspect of the present invention for achieving the above technical problem, a power down mode control unit for generating a first control signal (buf_enb) for determining to enter or exit the power down mode (power down mode entry) power down mode controller; A clock generator configured to generate a first clock pulse2 indicating a start of a phase update period and a second clock pulse8_11 indicating an end of the phase update period; receiving the first control signal buf_enb; A clock buffer controller for outputting a second control signal clkbuf_enb in response to a toggle of the clock pulse8_11; A clock buffer unit configured to generate an internal clock refclk by buffering an external clock in response to the second control signal clkbuf_enb; And a phase update unit configured to perform phase update based on the internal clock refclk. In addition, the DLL control unit (DLL CTRL) for outputting a reset signal for controlling the operation of the delay lock loop (DLL) in response to the DLL reset signal (dll_resetb) and the DLL deactivation signal (dis_dll) applied from the outside of the memory A delay locked loop circuit is further provided.

In the present invention, even when the clock buffer of the delay locked loop circuit DLL is turned off in the power down mode entry in the normal mode during the phase update, that is, Even if the clock buffer of the delay locked loop (DLL) is turned off during the phase update operation, the delay locked loop is completed after the phase update being performed. By delaying the off time of the clock buffer so that the clock buffer of the circuit DLL is turned off, it can be prevented from terminating abruptly during the phase update. have. To this end, in the present invention, the clock buffer control unit uses a scheme for delaying the off time of the clock buffer until the signal is activated using the last signal pulse8_11 of the pulse update period. (DLL buffer control) lets you do that.

Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.

2 is a block diagram for explaining the configuration of the delay locked loop circuit of the present invention.

Referring to FIG. 2, a delay locked loop (DLL) according to an embodiment of the present invention is a power-down mode in a synchronous memory device having a normal mode and a power down mode. A delay locked loop (DLL) for generating a DLL clock by locking information frozen in the power down mode exit without performing a phase update in a power down mode. A clock generator 400 generating a clock indicating a delay locked loop, a start (pulse2) and an end (pulse8_11) of a phase update period in the normal mode, and the normal Phase update operation of the delay locked loop after a clock pulse 11 indicating the end of the phase update period is input in order to obtain a margin of the phase update time when the power down mode entry is entered in a normal mode. To turn off The fishing means 200 is provided.

More specifically, the control means 200 generates a first control signal buf_enb for determining to enter or exit a power down mode entry, the power down mode control unit 220, the first A clock buffer controller 240 receives a first control signal buf_enb and outputs a second control signal clkbuf_enb in response to a toggle of the second clock pulse8_11.

The delay lock loop 300 is based on a clock buffer 310 which buffers an external clock in response to the second control signal clkbuf_enb to generate an internal clock refclk, and the internal clock refclk. Phase update unit 320, 330, 340, 350, 360, 370 to perform a phase update (pulse update).

3 is a circuit diagram illustrating an embodiment of a power down controller and a clock buffer controller of the present invention.

Referring to FIG. 3, the clock buffer controller 240 receives the first control signal buf_enb and delays the first control signal buf_enb for a predetermined time in response to a toggle of the second clock pulse8_11. A signal delay unit 242 for outputting the signal and a logic unit for receiving the output signal buf_enb8_11 and the first control signal buf_enb of the signal delay unit 242 and outputting the second control signal clkbuf_enb. 244 and a reset unit 246 for receiving the reset signal reset and the inverted signal buf_en of the first control signal to control the operation of the signal delay unit 242.

Among the components of the clock buffer controller 240, the signal delay unit 242 includes a data input D for the first control signal buf_enb and a clock input C for the second clock pulse8_11. And a D flip-flop that receives an output signal of the reset unit as a reset input. In addition, the D flip-flop is provided with a plurality of series connection. The logic unit 244 may include a first NAND gate NAND1 that receives an output signal buf_enb8_11 and the first control signal buf_enb of the signal delay unit 242 and performs a negative logic multiplication and outputs the first NAND gate NAND1 and the first signal. The first inverter INV1 outputs the second control signal clkbuf_enb by inverting the output of the NAND gate NAND1. The reset unit 246 may receive a second inverter INV2 for inverting and outputting the reset signal reset and a delay line for delaying a predetermined time by receiving an inversion signal buf_en of the first control signal. And the third inverter INV3 for inverting the output of the delay line and the output signal of the third inverter INV3 and the negative signal buf_en of the first control signal are negatively multiplied. Controlling the operation of the signal delay unit 242 by negatively multiplying the output signal of the second NAND gate NAND2 and the output signal of the second inverter INV2 and the output signal of the second NAND gate NAND2. A third NAND gate NAND3 for outputting the internal reset signal tmp_reset is provided.

The power down mode controller 246 receives the inversion signal ckeb_com of the clock enable signal and power down mode information sapd and PRE CHARGE information rassle of the mode register setting MSR. A NAND gate NAND4 outputted by performing a logical multiplication is provided, and the inverter INV4 outputs the first control signal buf_enb by inverting the output signal buf_en of the NAND gate.

Referring to the flow of the signal of the controller, when the clock enable signal CKE is the second logical value in the power down mode controller 220, the inverted signal ckeb_com is the first logical value and the mode register setting. The first control signal buf_enb of the first logical value when the PD mode information sapd of the MRS is the first logical value and the precharge information rasidle is the first logical value. )

The signal delay unit 242 may perform an operation without being reset when the inversion signal buf_en of the first control signal is the second logic value and the reset signal reset of the reset unit 246 is the second logic value. have.

Even if the first control signal buf_enb of the first logical value is input to the data input of the D flip-flop by the signal delay unit 242, the second clock Pulse8_11 input to the clock input of the D flip-flop is set at the second logical value. The first control signal buf_enb is delayed until the first logic value is reached, and at this time, a sufficient time for pulse update is obtained.

When the phase update operation is completed, the locking information of the delay locked loop circuit DLL is determined, and at the same time, the second clock Pulse8_11 also transitions to the first logic value. When the second clock pulse8_11 becomes the first logic value, the first control signal buf_enb, which is delayed by the D flip-flop, becomes the output signal buf_enb8_11 of the signal delay unit 242, and the signal delay unit 242. The output signal buf_enb8_11 and the first control signal buf_enb are received as inputs, and the logic unit 244 outputs the second control signal clkbuf_enb having the first logical value. The operation of the clock buffer unit 20 is turned off by the second control signal clkbuf_enb having the first logical value. Since the operation of the clock buffer unit is turned off, the internal clock of the delay locked loop circuit DLL is turned off. Therefore, the delay locked loop DLL enters the power down mode entry. .

FIG. 4 is a circuit diagram illustrating another embodiment of a clock buffer control unit according to the present invention.

Referring to FIG. 4, after the clock enable signal CKE becomes the second logical value, the second clock pulse 11_11 occurs after n times (n is a natural number of 1 or more). By making the signal buf_enb_11 the first logical value, after the n phase update, the second control signal clkbuf_enb is made the first logical value, thereby providing a clock buffer of the delay locked loop circuit DLL. By turning off the buffer, n phase update operations can be compensated for.

In the above description, the present invention is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented in different positions and types depending on the polarity of the input signal.

By applying the technique of the present invention, the phase update operation which is in progress when the clock buffer of the delay locked loop (DLL) is turned off at the time of entering the power down mode is performed. As a result, phase update was performed immediately with the current information, and the clock buffer of the delay locked loop circuit (DLL) was turned on, and the internal clock signal (refclk) and the phase detector were turned on. It is possible to prevent phase update with incorrect information due to the time difference of the feedback clock signal fbclk.

Claims (13)

In a synchronous memory device having a normal mode and a power down mode, A delay locked loop for generating a DLL clock by locking information frozen when the power-down mode exits without performing a phase update in the power-down mode; A clock generator for generating a clock for indicating a start and an end of a phase update period in the normal mode; And Control means for turning off the phase update operation of the delay lock loop after a clock indicating the end of the phase update period is input to obtain a margin of phase update time when the power-down mode is entered in the normal mode. Synchronous memory device comprising a. The method of claim 1, The delay lock loop includes a clock buffer that buffers an external clock to generate an internal clock, and performs phase update based on the internal clock. The method of claim 2, And the control means controls the driving of the clock buffer on / off. A power down mode controller configured to generate a first control signal for determining to enter or exit the power down mode; A clock generator configured to generate a first clock for notifying the start of the phase update period and a second clock for notifying the end; A clock buffer controller which receives the first control signal and outputs a second control signal in response to a toggle of the second clock; A clock buffer unit which buffers an external clock in response to the second control signal to generate an internal clock; And A phase updater performing phase update based on the internal clock; Delay fixed loop circuit comprising a. The method of claim 4, wherein And a DLL control unit outputting a reset signal for controlling the operation of the delay locked loop circuit in response to the DLL reset signal and the DLL deactivation signal applied from the outside of the memory. The method of claim 5, The clock buffer control unit, A delay lock loop, characterized in that reset by the reset signal The method according to claim 5 or 6, The clock buffer control unit, A signal delay unit configured to receive the first control signal and output a signal obtained by delaying the first control signal for a predetermined time in response to a toggle of the second clock; A logic unit configured to receive an output signal of the signal delay unit and the first control signal and output the second control signal; And A reset unit which receives the reset signal and the inverted signal of the first control signal and controls the operation of the signal delay unit; Delay fixed loop comprising a. The method of claim 7, wherein The signal delay unit, And a D flip-flop for receiving the first control signal as a data input, a second clock as a clock input, and an output signal of the reset unit as a reset input. The method of claim 8, The D flip-flop is a delay fixed loop circuit, characterized in that provided in plurality in series. The method of claim 7, wherein The logic unit, A first NAND gate that receives an output signal of the signal delay unit and the first control signal and outputs a negative logic multiplication result; And A first inverter outputting the second control signal by inverting the output of the first NAND gate A delay locked loop circuit comprising: a. The method of claim 7, wherein The reset unit, A second inverter for inverting and outputting the reset signal; A delay line which receives a reversal signal of the control signal and delays the predetermined time; A third inverter for inverting and outputting the output of the delay line; A second NAND gate receiving an output signal of the third inverter and an inverted signal of the first control signal and performing a negative logic multiplication to output the third signal; And A third NAND gate that receives an output signal of the second inverter and an output signal of the second NAND gate and performs a negative logic multiplication to output an internal reset signal for controlling an operation of the signal delay unit; A delay locked loop circuit comprising: a. The method of claim 4, wherein The power down mode control unit, A NAND gate that receives an inverted signal of a clock enable signal, power down mode information of a mode register setting, and precharge (PRE CHARGE) information, and outputs a negative logic multiplication; And An inverter outputting the first control signal by inverting an output signal of the NAND gate A delay locked loop circuit comprising: a. The method of claim 4, wherein The phase update unit, A phase delay unit which receives the internal clock signal and delays the phase and outputs the phase delay unit; A duty cycle correction unit for correcting a duty cycle in response to the locking information generated when the power down mode is entered; A delay replication model unit which models the output signal of the phase delay unit as delay elements of a clock signal in a memory and outputs the feedback clock signal as a feedback clock signal; A phase comparator configured to receive the internal clock signal and the feedback clock signal and detect a difference between phases of two signals; A mode generator configured to generate a phase update mode in response to an output signal of the phase comparator; And A delay control unit for determining a phase delay degree of the phase delay unit in response to an output signal of the mode generator; Delay fixed loop circuit comprising a.

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