KR100734024B1 - Input voltage independent current mode full wave rectifier - Google Patents

Abstract

An independent current mode full wave rectifier for an input voltage is provided to stabilize movement of a current source through a uniformly stabilized rectifier current. An input voltage independent current mode full wave rectifier includes a first operational amplifying unit(10), a second operational amplifying unit(20), a first NMOS, a second NMOS, a third PMOS, a fourth PMOS, and a current adding unit(30). The first operational amplifying unit(10) operation-amplifies input current. The second operational amplifying unit(20) reversion-amplifies the current from the first operational amplifying unit(10). The first NMOS has a gate connected to a negative output terminal of the first operational amplifying unit(10), a source connected to a ground of the current adding unit(30), and a drain connected to the input current and a drain of the third PMOS. The second NMOS has a gate connected to the negative output terminal of the first operational amplifying unit(10), a source connected to the ground of the current adding unit(30), and a drain connected to the current adding unit(30). The third PMOS has a gate connected to an output terminal of the second operational amplifying unit(20), a source connected to power voltage of the current adding unit(30), and a drain connected to the input current and the drain of the first NMOS. The fourth PMOS has a gate connected to the output terminal of the second operational amplifying unit(20), a source connected to the power voltage of the current adding unit(30), and a drain connected to the current adding unit(30). The current adding unit(30) adds the current output from the first NMOS, the second NMOS, the third PMOS, and the fourth PMOS.

Description

Input Voltage Independent Current Mode Full Wave Rectifier

1 is a conceptual diagram of a general current type full-wave rectifier.

2 is a circuit diagram of a conventional current type full-wave rectifier.

3 is a circuit diagram of an input voltage independent current full-wave rectifier according to an embodiment of the present invention.

4 is a waveform diagram of FIGS. 1 to 3, wherein (a) is a power supply voltage waveform, (b) is a rectifier input voltage waveform, (c) is a current waveform applied to a current source or rectifier, and (d) is A rectifier applied current waveform, (e) is a rectifier applied current waveform, (f) is an ideal rectified waveform, (g) is a rectifier output waveform, and (h) is a rectifier output waveform.

Explanation of symbols on the main parts of the drawings

10: first operational amplifier

20: second operational amplifier

30: current adding unit

M1 ~ M10: MOS

The present invention relates to a current-type full-wave rectifier, and more particularly, to an input voltage independent current-type full-wave rectifier suitable for realizing current propagation regardless of the type and size of the current source and the load connected to the current source.

Accordingly, the present invention relates to a rectifier of sinusoidal currents, and is used to obtain a DC current value by full-wave rectifying and smoothing sinusoidal currents. By rectifying the sinusoidal current and adding an application circuit such as a smoothing circuit, the root mean square of the sinusoidal current can be obtained. Such rectifiers include full-wave rectifiers and half-wave rectifiers. A full-wave rectifier, which is approximately twice as efficient as a half-wave rectifier, is a field of technology to be improved in the present invention.

On the other hand, as a requirement of the current-type full-wave rectifier for obtaining the effective value of the current in the rectifier, it is possible to obtain a more accurate effective value only by rectifying without the distortion of the magnitude and waveform of the current applied to the rectifier. Therefore, the rectifier itself must be a circuit configuration of high reliability, and the input dynamic range of the rectifier circuit must be larger than the current applied to obtain the propagated current regardless of the magnitude of the current applied to the rectifier.

Another requirement for current full-wave rectifiers is that the rectifier must not affect the magnitude of the input current or the waveform itself. This is because all current sources generate magnitude and waveform distortion depending on the type of load and the circuit configuration of the rectifier connected to the current source, unless it is an ideal current source (a current source that always emits a constant magnitude and waveform regardless of load conditions).

However, since it is impossible to actually make or configure an ideal current source irrespective of the type of load, another alternative is to use a circuit configuration in which the current source and the load and the full-wave rectifier connected to the load are not sensitive to the type or size of the load of the current source. In addition, there is a need for the development of a current type full-wave rectifier that meets these requirements.

Accordingly, the present invention has been proposed to solve the above conventional problems, and an object of the present invention is an input voltage independent current type full-wave rectifier capable of realizing current propagation regardless of the type and size of the current source and the load connected to the current source. To provide.

In order to achieve the above object, the input voltage independent current full-wave rectifier according to an embodiment of the present invention,

Receive input current as (-) input terminal, Vbias as (+) input terminal, (+) output terminal is connected to the second operational amplifier, and (-) output terminal to the gate of the first NMOS and the second NMOS A first operational amplifier connected to the first operational amplifier to amplify the input current; (-) Input terminal is connected to the (+) output terminal of the first operational amplifier, (+) input terminal is connected to the ground, the output is connected to the gate of the third and fourth PMOS, the first A second operational amplifier for inverting and amplifying the current from the operational amplifier; A first NMOS connected to a gate of a negative output terminal of the first operational amplifier, a source connected to a ground of a current adding unit, and a drain connected to an input current and a drain of the third PMOS; A second NMOS having a gate connected to the negative output terminal of the first operational amplifier, a source connected to the ground of the current adding unit, and a drain connected to the current adding unit; A third PMOS gate connected to an output terminal of the second operational amplifier, a source connected to a power supply voltage of the current adding unit, and a drain connected to an input current and a drain of the first NMOS; A fourth PMOS having a gate connected to the output terminal of the second operational amplifier, a source connected to a power supply voltage of the current adding unit, and a drain connected to the current adding unit; And a current summing unit for adding a current output from the first NMOS, the second NMOS, the third PMOS, and the fourth PMOS.

Hereinafter, an embodiment according to the present invention as described above, the technical spirit of the input voltage independent current type full-wave rectifier with reference to the drawings as follows.

3 is a circuit diagram of an input voltage independent current full-wave rectifier according to an embodiment of the present invention.

As shown in the drawing, an input current is received as a negative input terminal, Vbias is received as a positive input terminal, and a positive output terminal is connected to the second operational amplifier Amp2 20. An output terminal connected to the gates of the first NMOS M1 and the second NMOS M2, the first operational amplifier part Amp1 10 for operational amplifying the input current; (-) Input terminal is connected to the (+) output terminal of the first operational amplifier 10, (+) input terminal is connected to the ground (GND), the output is the third PMOS (M3) and fourth A second operational amplifier (Amp2) 20 connected to the gate of the PMOS M4 and inverting and amplifying the current from the first operational amplifier 10; A gate is connected to the (−) output terminal of the first operational amplifier 10, a source is connected to the ground (GND) of the current summing unit 30, the drain is the input current and the third PMOS (M3) A first NMOS M1 connected to the drain of the first NMOS M1; A gate is connected to the negative output terminal of the first operational amplifier 10, a source is connected to the ground GND of the current adding unit 30, and a drain is connected to the current adding unit 30. A second NMOS M2; A gate is connected to an output terminal of the second operational amplifier 20, a source is connected to a power supply voltage VDD of the current summing unit 30, and a drain is connected to an input current and the first NMOS M1. A third PMOS M3 connected to the drain; A gate is connected to an output terminal of the second operational amplifier 20, a source is connected to a power supply voltage VDD of the current summing unit 30, and a drain is connected to the current summing unit 30. 4 PMOS (M4); And a current summing unit 30 for adding currents output from the first NMOS M1, the second NMOS M2, the third PMOS M3, and the fourth PMOS M4. It is done.

The first operational amplifier 10 may be configured as a full differential op amp.

The current summing unit 30 has a gate connected to a drain and simultaneously connected to a sixth NMOS M6, a source connected to a ground GND, and a drain connected to a drain of the fourth PMOS M4. A fifth NMOS M5; A sixth NMOS M6 having a gate connected to the fifth NMOS M5, a source connected to a ground GND, and a drain connected to a gate and a drain of the tenth PMOS M10; A seventh PMOS M7 connected to a drain and simultaneously to an eighth PMOS M8, a source connected to a power supply voltage VDD, and a drain connected to a drain of the second NMOS M2; A gate is connected to the seventh PMOS M7, a source is connected to a power supply voltage VDD, and a drain is connected to a drain of the ninth PMOS M9 to output an output current Io. Wow; A gate is connected to the tenth PMOS M10, a source is connected to a power supply voltage VDD, and a drain is connected to the drain of the eighth PMOS M8 to output an output current Io. )Wow; A tenth PMOS M10 connected to a drain and simultaneously connected to a sixth NMOS M6, a source connected to a power supply voltage VDD, and a drain connected to a drain of the sixth NMOS M6; Characterized in that configured to include.

Referring to the preferred embodiment of the input voltage independent current-type full-wave rectifier according to the present invention configured as described above in detail with reference to the accompanying drawings as follows. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to intention or precedent of a user or an operator, and accordingly, the meaning of each term should be interpreted based on the contents throughout the present specification. something to do.

First, the present invention is intended to realize current propagation regardless of the type and size of the current source and the load connected to the current source. That is, in the case of the ideal current type full-wave rectifier, the applied current is full-wave rectified regardless of the magnitude of the input voltage accompanying the current applied to the rectifier. However, in the case of general current rectifiers, the magnitude of the applied voltage changes according to the magnitude of the current and the load conditions. Therefore, most current sources in which the current rectifier itself does not perform the desired rectification operation or the current source is not ideal, depending on the load conditions. The size of will change. Therefore, the present invention is intended to implement a current-type full-wave rectifier that does not change the current magnitude of the current source even in the case of a general current source by avoiding the variation of the magnitude of the current applied from the current source and the voltage of the load condition.

Therefore, the current-type full-wave rectifier of the present invention inverts and amplifies the current from the positive (+) output terminal of the first operational amplifier (Op-Amp1) 10 and the first operational amplifier 10 that receives the input current. Four transistors (M1 to M2) that receive and amplify the outputs of the second operational amplifier (Op-Amp2) 20, the negative (-) output terminal of the first operational amplifier 10, and the second operational amplifier 20. M4) and a current summing unit 30 that adds the output current of the transistors M1 to M4, and the like, and a connection line for feeding back the input of the operational amplifier to the output side.

The first operational amplifier (Op-Amp1) 10 is composed of a full differential op amp, which is differentially amplified to maintain a constant voltage regardless of the magnitude of the input current or the type of the input load. It is configured to apply any DC voltage appropriate to the negative positive input terminal.

In addition, the negative (-) output terminal of the first operational amplifier (Op-Amp1) 10 is connected to the gates of the NMOS transistors M1 and M2, and the positive (+) output terminal is connected to the negative input terminal of the second operational amplifier unit 20. The output terminal of the second operational amplifier 20 is connected to the gates of the PMOS transistors M3 and M4, and the drains of the NMOS and the PMOS are connected to the current summing unit 30 for obtaining the sum of the currents.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Looking at the overall circuit configuration including the current-type rectifier to be proposed in the present invention, as shown in the current-type full-wave rectifier concept of Figure 1 is a current source Is and the power supply current resistance Rs inherent in the current source itself is connected in series, in the current source Is The exiting current Is enters the load via Rs.

A voltage Vs (see Fig. 4A) is applied between the load input terminal and the power terminal negative voltage GND, and then the input current Ii, which is the current passing through the load, is subsequently applied to the current type full-wave rectifier. Assuming there is no leakage current at the load (Is = Ii), the magnitude of the supply current Is is applied to the current-type full-wave rectifier without changing the size, and this voltage is the voltage between the supply voltage Vs and the input voltage Vi between both ends of the load. A difference (= Vs-Vi) is generated. In addition, the input voltage Vi of the current wave rectifier (see (b) of FIG. 4) affects the operating point of the current wave rectifier and also affects the operation of the current source itself. This is because the operating point of the current source Is can be changed by the load and the supply current resistance Rs because Is itself is not an ideal current source (see (c) of FIG. 4).

Taking the conventional current type propagation circuit diagram shown in FIG. 2 as an example, the current Ii (see FIG. 4C) passing through the load in FIG. 1 is applied to the drain of NMOS M1 of FIG. 2, and the drain and gate of NMOS M1 are shown. As the gate of NMOS M2 is connected to form a current mirror, the incoming current Ii flows to GND through the drain and source of NMOS M1, and the same current flows from the source of NMOS M2 to ground (GND).

Meanwhile, in FIG. 2, current flows and stops repeatedly in the NMOS transistor M3 source connected in series with the drain of the transistor NMOS M1 according to the magnitude of the drain of the transistor M1 and the source voltage Vi. That is, when the sinusoidal current is positive, the current flowing through the transistor M1 is mostly taken by the current Ii drawn from the current source, so that less current flows in the M3. This is because Vi increases due to Ii, and the difference between bias voltages Vbias and Vi applied to the gate of M3 decreases, so that the current flowing in M3 decreases. On the contrary, when Ii is negative (Ii decreases), drain to M2 by the current mirror. Instead of decreasing the current flowing from the source to the source, the difference between the bias voltage of M3 and Vi (the less Vi, the less Vi) increases, resulting in a larger current in M3, which eventually drains transistor M4 when Ii is both positive and negative. Since the current flowing through is represented by the sum of the drain currents of M3 and M2, the full-wave rectified current flows.

However, this problem in the conventional circuit is a full rectification operation under the assumption that Vi in Fig. 2 is determined only by the size of Ii, in a practical situation, as in Fig. 1, in the actual current conventional full-wave full-wave rectifier of Fig. Since Vi is introduced into the current-type full-wave rectifier through the load before the current Ii is applied to the circuit of, the Vi actually changes depending on the load connected to the current source Is and the input condition (state) of the current-type full-wave rectifier. Full current propagation will fail.

For example, if Ii has a large current and a large load as shown in Fig. 1, the voltage drop at the load will be large, so that the gate voltage of transistor M3 in Fig. 2 is fixed, and the DC voltage level of Vi is low. M3 is in a state capable of normal operation, but when the gate voltage of M1 is lowered so that M1 cannot operate normally, and the input current Ii is applied, the waveform appears in Ii as shown in (e) of FIG. 4. Clamping occurs near the negative polarity, and the output current Io at this time becomes a waveform with a high distortion as shown in FIG.

On the other hand, when Ii is large and the load is low, or when the M3 gate voltage Vbias voltage of FIG. 2 is low, Ii is clamped in the vicinity of the positive polarity as shown in the waveform diagram of FIG. 4, and the output waveform thereof is shown in FIG. A distortion current rectifying waveform, as in g), appears.

Therefore, as shown in FIG. 3 of the circuit diagram of the present invention, the current Ii is applied to the negative input terminal of the first operational amplifier (Op-Amp1) 10, which is a fully differential operational amplifier, and the positive terminal is connected such that Vbias is applied and Op- The positive output of Amp1 is connected to the negative input terminal of the second operational amplifier (Op-Amp2) 20, and the negative output terminal of the Op-Amp1 is connected to the common gate of the NMOS transistors M1 and M2. The positive input terminal of the second operational amplifier 20 is stored.

On the other hand, the output terminal of Op-Amp2 is commonly connected to the gates of the PMOS transistors M3 and M4. In addition, the drain of the NMOS M1 is connected to the drain of the PMOS M3, and the common drain of M1 and M3 is connected to the negative input terminal of Op-Amp1 to complete the negative feedback circuit. In addition, the gate of PMOS M3 and the gate of PMOS M4 are connected, the gate of NMOS M1 and the gate of NMOS M2 are connected, the sources of M1 and M2 are connected to GND, and the sources of PMOS M3 and M4 are connected to VDD.

The drain of the PMOS M4 is connected to the drain of the NMOS M5, the drain and the gate of the M5 is directly connected to each other to the gate of M6, the sources of M5 and M6 are connected to GND to form a current mirror.

In addition, the drain of the NMOS M2 is connected to the drain of the PMOS M7 and at the same time directly connected to the gate of the M7 is connected to the gate of the PMOS M8 to form a current mirror. The sources of M7 and M8 connect to VDD. The drain of the PMOS M10 is connected to the drain of the NMOS M6, the drain of the M10 is directly connected to the gate of the M10, and constitutes a current mirror by connecting to the gate of the PMOS M9. The sources of M9 and M10 are connected to the supply voltage VDD.

Finally, M8 and M9 bundle the drains and directly connect the drains to complete the current adding unit 30.

Referring to the operation of the present invention, first, the sine wave current Ii is applied to the negative terminal of Op-Amp1, and when the applied current is positive polarity (or a large period), the Vbias voltage difference connected to the positive input terminal of Op-Amp1 is large. This decreases the positive output terminal voltage of Op-Amp1 and increases the output terminal voltage of Op-Amp2. As a result, the gate voltages of the PMOS M3 and M4 are increased to decrease the current flowing in the drains of the M3 and M4. At the same time, since the voltage at the negative output terminal of Op-Amp1 increases, the gate voltage of M1 and M2 increases, and the drain current of M1 and M2 increases.

On the contrary, when the input current Ii is negative (or a section in which the current decreases), the drain current of M3 and M4 increases and the drain current of M1 and M2 decreases. As the drain current of M2 decreases, the drain current of M7 and M8 decreases. At this time, since the drain current of M4 increases, the drain current of M5, M6, M10, M9 continues to increase by the current mirror operation.

Since the drains of M8 and M9 are directly connected to each other, when the drain current of M8 decreases, the drain current of M9 increases, so if the input current Ii decreases to negative polarity, the drain current of M9 increases, and conversely, Ii increases to positive polarity. When the drain current of M8 increases (or increases), the output current Io becomes larger in both positive and negative polarities as the drain current of M8 becomes larger and the M9 drain current becomes smaller, resulting in full wave rectification (Fig. 4 (f) ) Reference).

As described above, if the input current Ii increases positively and the negative input terminal voltage of Op-Amp1 increases, the drain voltage of M3 decreases and this voltage is connected to the negative input terminal of Op-Amp1. The negative voltage is kept constant by the negative feedback operation. This means that the negative input terminal voltage of Op-Amp1 is always the same as Vbias voltage which is the voltage of the input terminal.

Through this operation, the operation of the current-type full-wave rectifier is fully realized, and at the same time, the stable operation is independent of the magnitude of the input current Ii and the voltage of Ii, that is, the voltage change caused by passing the load in FIG. 1.

As described above, the input voltage independent current full-wave rectifier according to the present invention can be full-wave rectified regardless of the voltage fluctuation that can occur when the sine wave current coming from the utility power current source, not the ideal current source through the load. The constant rectifier voltage also stabilizes the operation of the utility current source.

Although the above has been described as being limited to the preferred embodiment of the present invention, the present invention is not limited thereto and various changes, modifications, and equivalents may be used. Therefore, the present invention can be applied by appropriately modifying the above embodiments, it will be obvious that such application also belongs to the scope of the present invention based on the technical idea described in the claims below.

Claims (3)

Receive input current as (-) input terminal, Vbias as (+) input terminal, (+) output terminal is connected to the second operational amplifier, and (-) output terminal to the gate of the first NMOS and the second NMOS A first operational amplifier connected to the first operational amplifier to amplify the input current; (-) Input terminal is connected to the (+) output terminal of the first operational amplifier, (+) input terminal is connected to the ground, the output is connected to the gate of the third and fourth PMOS, the first A second operational amplifier for inverting and amplifying the current from the operational amplifier; A first NMOS connected to a gate of a negative output terminal of the first operational amplifier, a source connected to a ground of a current adding unit, and a drain connected to an input current and a drain of the third PMOS; A second NMOS having a gate connected to the negative output terminal of the first operational amplifier, a source connected to the ground of the current adding unit, and a drain connected to the current adding unit; A third PMOS gate connected to an output terminal of the second operational amplifier, a source connected to a power supply voltage of the current adding unit, and a drain connected to an input current and a drain of the first NMOS; A fourth PMOS having a gate connected to the output terminal of the second operational amplifier, a source connected to a power supply voltage of the current adding unit, and a drain connected to the current adding unit; A current adder configured to add currents output from the first NMOS, the second NMOS, the third PMOS, and the fourth PMOS; Input voltage independent current type full-wave rectifier, characterized in that comprises a. The method according to claim 1, The first operational amplifier, Input voltage independent current full-wave rectifier, characterized in that consisting of a fully differential amplifier. The method according to claim 1 or 2, The current adding unit, A fifth NMOS gate connected to a drain and simultaneously connected to a sixth NMOS, a source connected to ground, and a drain connected to the drain of the fourth PMOS; A sixth NMOS having a gate connected to the fifth NMOS, a source connected to ground, and a drain connected to the gate and the drain of the tenth PMOS; A seventh PMOS connected to a drain and simultaneously to an eighth PMOS, a source connected to a power supply voltage, and a drain connected to a drain of the second NMOS; An eighth PMOS having a gate connected to the seventh PMOS, a source connected to a power supply voltage, and a drain connected to a drain of the ninth PMOS connected to output an output current; A ninth PMOS having a gate connected to the tenth PMOS, a source connected to a power supply voltage, and a drain connected to a drain of the eighth PMOS to output an output current; A tenth PMOS connected to a drain and simultaneously connected to a sixth NMOS, a source connected to a power supply voltage, and a drain connected to a drain of the sixth NMOS; Input voltage independent current type full-wave rectifier, characterized in that comprises a.

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