KR100726662B1 - Driving device of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel which switches the set-down method according to the panel margin. The present invention includes a drive integrated circuit unit for supplying a driving voltage to the panel; An energy recovery circuit unit for supplying and recovering a sustain voltage to the drive integrated circuit unit; A setup supply unit for supplying a sustain driving and setup voltage to the drive integrated circuit unit; A set down supply unit supplying a set down voltage to the drive integrated circuit unit; And a set down controller for selectively adjusting the set down voltage. The set down control unit; And a switching switch (SW) for selectively switching the setdown voltage to ground (GND) or write scan voltage (-Vy) according to the panel margin. Therefore, in order to improve the panel margin, the set-down voltage drops from Vs to -Vy during the initialization period, and if the panel margin is a little worse, the set-down voltage is lowered from GND to -Vy to improve heat generation. By switching the set-down method, the PDP can be driven more efficiently.

Plasma, Panel, Margin, PDP, Drive, Scan, Drive, Setup, Setdown

Description

Driving device for plasma display panel {Driving Apparatus for Plasma Display Panel}

1 is a waveform diagram showing a driving process of a general plasma display panel.

2 is a block diagram showing a driving apparatus of a conventional plasma display panel.

3 is a timing diagram illustrating a switching operation of FIG. 2.

4 is a block diagram showing a driving device of the plasma display panel according to the present invention;

5 and 6 are waveform diagrams showing the driving process of the plasma display panel according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: energy recovery circuit unit 110: the setup supply unit

120: scan reference voltage supply unit 130: drive integrated circuit unit

140: scan voltage supply unit 150: set-down supply unit

160: set-down control unit Q1 to Q15: FET switch

SW: selector switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma display panel, and more particularly, to a driving apparatus for a plasma display panel which switches a set down method according to a panel margin.

In general, a plasma display panel (hereinafter referred to as "PDP") refers to a device for displaying an image including text or graphics by emitting phosphors by ultraviolet rays generated when the inert gas is discharged.

1 is a waveform diagram illustrating a driving process of a general PDP as described above.

As shown, the PDP is divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period (reset period), the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the set-down period SD, after the rising ramp waveform is supplied, the positive voltage lower than the peak voltage of the rising ramp waveform begins to drop, and the falling ramp waveform Ramp- falls to the base voltage GND or a specific voltage level of the negative polarity. down) causes a slight erase discharge in the cells, thereby partially canceling the overcharged wall charge. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied. The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so that an erroneous discharge with the scan electrode Y does not occur.

In the sustain period, a sustain pulse Su is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied.

After the sustain discharge is completed, a ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode (Z) to erase the wall charge remaining in the cells of the full screen.

2 is a block diagram illustrating a driving apparatus of a conventional plasma display panel, and FIG. 3 is a timing diagram illustrating a switching operation of FIG. 2.

As shown in FIG. 2, the driving apparatus of the conventional PDP includes an energy recovery circuit 40, a setup supply 42, a set-down supply 44, a scan voltage supply 46, a scan reference voltage supply 50, The drive integrated circuit unit 52 is provided. In addition, a seventh switch Q7 connected between the setup supply unit 42 and the drive integrated circuit unit 52 and a sixth switch Q6 connected between the setup supply unit 42 and the energy recovery circuit unit 40 are provided. .

The drive integrated circuit unit 52 is connected in a push-pull form, and voltage signals from the energy recovery circuit unit 40, the setup supply unit 42, the set-down supply unit 44, the scan voltage supply unit 46, and the scan reference voltage supply unit 50 are applied. The fourteenth and fifteenth switches Q14 and Q15 are inputted. The output line between the fourteenth and fifteenth switches Q14 and Q15 is connected to one of the scan electrode lines.

The energy recovery circuit unit 40 includes an external capacitor C1 for charging energy recovered from the scan electrode lines Y1 to Ym, and an inductor L1 connected between the external capacitor C1 and the drive integrated circuit unit 52. And a first switch Q1, a first diode D1, a second diode D2, and a second switch Q2 connected in parallel between the inductor L1 and the external capacitor C1.

Referring to the operation of the energy recovery circuit unit 40 as follows.

First, it is assumed that the external capacitor C1 is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor C1 is the first switch Q1, the first diode D1, the inductor L, the internal diode of the sixth switch Q6, and The drive integrated circuit unit 52 is supplied to the drive integrated circuit unit 52 via the seventh switch Q7, and the drive integrated circuit unit 52 supplies the voltage supplied thereto to the panel Cp. At this time, since the inductor L1 forms a series LC resonant circuit together with the capacitance C of the PDP discharge cell, a voltage of Vs is supplied to a scan electrode line (not shown) of the panel Cp.

Thereafter, the third switch Q3 is turned on. When the third switch Q3 is turned on, the sustain voltage Vs is supplied to the drive integrated circuit 52 via the internal diode of the sixth switch Q6 and the seventh switch Q7. The drive integrated circuit unit 52 supplies the sustain voltage supplied thereto to the panel Cp. Due to the sustain voltage Vs, the voltage level on the scan electrode lines Y1 to Ym maintains the sustain voltage Vs, thereby causing sustain discharge in the discharge cells.

After the sustain discharge occurs in the discharge cells, the second switch Q2 is turned on. When the second switch Q2 is turned on, the panel Cp, the drive integrated circuit 52, the internal diode of the seventh switch Q7, the sixth switch Q6, the inductor L1, and the second diode D2. ) And the second capacitor Q2 are recovered to the external capacitor C1 in addition to the reactive power. That is, energy from the PDP is recovered to the external capacitor C1. Subsequently, the fourth switch Q4 is turned on to maintain the voltage of the panel Cp at ground GND.

In this way, the energy recovery circuit unit 40 recovers energy from the PDP, and then supplies voltage to the panel Cp using the recovered energy to reduce excessive power consumption during the discharge during the setup period and the sustain period.

The scan voltage supply unit 46 includes an eleventh switch Q11 connected between the second node n2 and the write scan voltage -Vy. The eleventh switch Q11 is switched in response to a control signal supplied from a timing controller (not shown) during the address period of the selective write subfield WSF, thereby supplying the write scan voltage (-Vy) to the drive integrated circuit unit 52. do.

The scan reference voltage supply unit 50 is a third capacitor C3 connected between the reference voltage source Vsc and the second node n2, and an eighth connected between the reference voltage source Vsc and the second node n2. A switch Q8 and a ninth switch Q9 are provided. The eighth switch Q8 and the ninth switch Q9 are supplied by the control signal supplied from the timing controller during the selective write and erase address periods to supply the voltage of the reference voltage source Vsc to the drive integrated circuit unit 52. The third capacitor C3 adds the voltage applied to the second node n2 and the voltage value of the reference voltage source Vsc to the eighth switch Q8.

The set-down supply unit 44 includes a tenth switch Q10 connected between the second node n2 and the write scan voltage −Vy. The set-down supply unit 44 gradually lowers the voltage supplied to the drive integrated circuit unit 52 during the set-down period included in the reset period of the selective write subfield WSF with a slope to the write scan voltage -Vy. , Write scan voltage (-Vy) is used as the set-down voltage source.)

The setup supply unit 42 includes a fifth switch Q5 and a first variable resistor VR1 connected between the setup voltage source Vsetup and the first node n1, the setup voltage source Vsetup and the energy recovery circuit unit 40. And a second capacitor C2 provided therebetween. The second capacitor C2 adds the sustain voltage Vs supplied from the energy recovery circuit unit 40 and the voltage value of the setup voltage source Vsetup to the fifth switch Q5. The fifth switch Q5 is switched in response to a control signal (not shown) during the reset period of the selective write subfield WSF to supply the setup voltage to the first node n1.

Next, a process of generating setup and set-down voltages during the reset period will be described with reference to FIG. 3.

Here, it is assumed that the voltage of the setup voltage source Vsetup is charged in the second capacitor C2. It is assumed that the sustain voltage Vs is supplied from the energy recovery circuit unit 40 to the first node n1 at the turn-on time of the fifth switch Q5.

As shown in FIG. 3, first, the fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit unit 40. The sustain voltage Vs supplied from the energy recovery circuit unit 40 is supplied to the panel Cp via the internal diode of the sixth switch Q6, the seventh switch Q7, and the drive integrated circuit unit 52. Thus, the voltage of the scan electrode lines of the panel Cp rises rapidly to Vs.

On the other hand, since the voltage of Vs is supplied to the negative terminal of the second capacitor C2, the second capacitor C2 supplies the voltage of Vs + Vsetup to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. . The voltage applied with the predetermined slope to the first node n1 is supplied to the panel Cp via the seventh switch Q7 and the drive integrated circuit unit 52. At this time, the rising ramp waveform Ramp-up is supplied to the scan electrode lines of the panel Cp.

After the rising ramp waveform Ramp-up is supplied to the scan electrode line, the fifth switch Q5 is turned off. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 40 is applied to the first node n1, so that the voltage of the panel Cp drops rapidly to Vs.

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period. The tenth switch Q10 adjusts the voltage of the second node n2 to the write scan voltage -Vy (or setdown voltage) while the channel width is adjusted by the second variable resistor VR2 provided at the front end thereof. Descend with a slope. At this time, the falling ramp waveform Ramp-down is supplied to the panel Cp.

The setup supply unit 42 and the set-down supply unit 44 supply the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the panel Cp during the reset period while repeating the above process.

At this time, since the voltage difference between the voltages applied to the first node n1 and the second node n2 is large, a seventh switch Q7 having a high breakdown voltage is used. Here, the seventh switch Q7 includes an internal diode in a different direction from that of the sixth switch Q6, and the voltage applied to the second node n2 is applied to the internal diode and the fourth switch Q4 of the sixth switch Q6. It is prevented from being supplied to the ground (GND) via the internal diode of the).

Meanwhile, a voltage of Vs is applied to the first node n1 and a write scan voltage (-Vy) is applied to the second node n2 during the set down period. Here, if the voltage of Vs is set to approximately 180V and the write scan voltage (-Vy) is set to -70V, the seventh switch Q7 should have a breakdown voltage of approximately 250V (300V in consideration of the actual driving voltage margin).

However, since such a conventional PDP driving device operates only with one preset driving method, for example, when the setdown voltage drops from the sustain voltage Vs to the setdown voltage (-Vy) during the initialization period, the panel margin Improves, while the set-up heats up the circuit. On the other hand, when the set-down voltage is lowered from the ground (GND) to the set-down voltage (-Vy) as another driving method to solve this problem, there is a problem that the heat generation of the circuit is improved, but the panel margin is worse.

Accordingly, an object of the present invention is to provide a driving apparatus for a plasma display panel which improves the panel margin and heat generation problems by switching the set-down method according to the panel margin. .

According to another aspect of the present invention, there is provided a driving apparatus of a plasma display panel, including: a drive integrated circuit unit configured to supply a driving voltage to the panel; An energy recovery circuit unit for supplying and recovering a sustain voltage to the drive integrated circuit unit; A setup supply unit for supplying a sustain driving and setup voltage to the drive integrated circuit unit; A set down supply unit supplying a set down voltage to the drive integrated circuit unit; And a set down controller for selectively adjusting the set down voltage.

The set down control unit; And a switching switch (SW) for selectively switching the setdown voltage to ground (GND) or write scan voltage (-Vy) according to the panel margin.

The set down control unit; During the initialization period, the setdown voltage is lowered from the sustain voltage (Vs) to the write scan voltage (-Vy).

The set down control unit; The set down voltage is lowered from the ground (GND) to the write scan voltage (-Vy) during the initialization period.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram illustrating a driving apparatus of a plasma display panel according to the present invention, and FIGS. 5 and 6 are waveform diagrams illustrating a driving process of the plasma display panel according to the present invention.

As shown, the present invention includes an energy recovery circuit unit 100, a setup supply unit 110, a scan reference voltage supply unit 120, a drive integrated circuit unit 130, a scan voltage supply unit 140, a setdown supply unit 150, and a setdown unit. The control unit 160 is configured.

The energy recovery circuit unit 100 supplies and recovers the sustain voltage Vs to the drive integrated circuit unit 130, and the setup supply unit 110 supplies the sustain driving and setup voltage Vsetup to the drive integrated circuit unit 130 during an initialization period. Supply.

The energy recovery circuit unit 100 may reduce power consumption by recovering, storing, and reusing energy consumed during charging and discharging of the panel Cp.

The setup supply unit 110 supplies a sustain drive and rising ramp waveform to the drive integrated circuit unit 130 during the setup period. Accordingly, the setup supply unit 110 includes a switch Q5 for forming a ramp pulse having a Vsc voltage level and supplying the ramp pulse to the drive integrated circuit unit 130.

The scan reference voltage supply unit 120 supplies a scan reference voltage Vsc to the drive integrated circuit unit 130, and the drive integrated circuit unit 130 supplies a driving voltage to the panel Cp.

The scan reference voltage supply unit 120 supplies the scan reference voltage required for the address driving to the drive integrated circuit unit 130. To this end, the scan reference voltage supply unit 120 includes an eighth switch Q8 and a ninth switch Q9 for supplying a reference voltage Vsc to the drive integrated circuit unit 130.

The scan voltage supply unit 140 and the setdown supply unit 150 supply a setdown voltage to the drive integrated circuit unit 130 during an initialization period.

The scan voltage supply unit 140 and the setdown supply unit 150 may include a tenth switch Q10 for lowering a voltage supplied to the drive integrated circuit unit 130 to a write scan voltage (−Vy) during a setdown period with a predetermined slope. An eleventh switch Q11 is provided.

The setdown controller 160 selectively adjusts the setdown voltage during the initialization period. To this end, the set-down control unit 160; And a switching switch (SW) for selectively switching the setdown voltage to ground (GND) or write scan voltage (-Vy) during the initialization period according to the panel margin.

In addition, the set-down control unit 160; During the initialization period, the setdown voltage is lowered from the sustain voltage Vs to the write scan voltage (-Vy), or during the initialization period, the setdown voltage is lowered from the ground (GND) to the write scan voltage (-Vy).

Referring to the operation of the present invention configured in this way in more detail as follows.

First, the sustain voltage Vs is supplied as the third switch Q3 and the seventh switch Q7 of the energy recovery circuit unit 100 are turned on during the setup period. The sustain voltage Vs supplied from the energy recovery circuit unit 100 is supplied to the panel Cp via the internal diode of the sixth switch Q6, the seventh switch Q7, and the drive integrated circuit unit 130. Thus, the voltage of the scan electrode lines of the panel Cp rises rapidly to Vs.

On the other hand, since the voltage of Vsetup is supplied to the negative terminal of the second capacitor C2 of the setup supply unit 110, the second capacitor C2 supplies the voltage of Vs + Vsetup to the fifth switch Q5.

The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. .

The voltage applied to the first node n1 with a predetermined slope is supplied to the panel Cp via the seventh switch Q7 and the drive integrated circuit unit 130. At this time, the rising ramp waveform Ramp-up is supplied to the scan electrode lines (not shown) of the panel Cp.

After the rising ramp waveform Ramp-up is supplied to the scan electrode line, the fifth switch Q5 is turned off. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit unit 100 is applied to the first node n1. Accordingly, the voltage of the panel Cp drops rapidly to Vs.

Thereafter, the seventh switch Q7 is turned off in the set down period, and the scan voltage supply unit 140 and the tenth switch Q10 of the set down supply unit 150 are turned on. The tenth switch Q10 determines the voltage of the second node n2 as the write scan voltage (-Vy) (or the setdown voltage) while the channel width is adjusted by the second variable resistor VR2 provided at the front end thereof. Descend with the slope of. At this time, the ramp ramp down (ramp-down) is supplied to the scan electrode lines of the panel (Cp).

The setup supply unit 110 and the set-down supply unit 150 supply the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the panel Cp during the reset period while repeating the above process.

At this time, since the conventional PDP operates only in one preset driving method, the PDP cannot be efficiently driven. However, the present invention drives the PDP more efficiently by selectively adjusting the setdown voltage during the initialization period from the setdown controller 160.

To this end, the set-down control unit 160; And a switching switch (SW) for selectively switching the setdown voltage to ground (GND) or write scan voltage (-Vy) during the initialization period according to the panel margin.

The set-down control unit 160 connects to the b terminal by turning down the switch SW in order to improve the panel margin. Therefore, the panel margin can be improved by causing the setdown voltage to fall from the sustain voltage Vs to the write scan voltage -Vy during the initialization period.

In addition, even if the panel margin is a little bad, when the heat generation is improved, the switching switch SW is connected to the terminal a. Therefore, the set-down voltage is lowered from the ground GND to the write scan voltage -Vy during the initialization period, thereby improving heat generation.

Meanwhile, the change of the setdown start voltage of the setdown pulse according to the embodiment of the present invention may be applied to one or more subfields SF or one or more frames. That is, the change of the setdown start voltage may be made in correspondence to the weight of the subfield, and may be made in correspondence to the gray level of the frame. For example, in a grayscale or gray level subfield or frame where the margin of the panel should be good, the setdown start voltage is preferably a sustain voltage (Vs), and in a grayscale or gray level subfield or frame where the heat generation characteristics of the setdown circuit should be good. It would be desirable for the three start voltages to be at ground level.

Accordingly, all subfields in one frame may have a setdown start voltage of ground level or sustain voltage (Vs) level, whereas at least one subfield may have a setdown start voltage different from other subfields.

In addition, the panel margin mentioned in the embodiment of the present invention is meant to include the driving voltage margin of the panel.

Although the above has been illustrated and described with respect to preferred embodiments of the present invention, the present invention is not limited to the above-described embodiments, and the general knowledge in the field to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Anyone with a variety of variations will be possible.

As described above, according to the driving apparatus of the plasma display panel according to the present invention, in order to improve the panel margin, the set-down voltage is lowered from Vs to -Vy during the initialization period, and heat generation is improved even though the panel margin is slightly bad. In this case, by lowering the setdown voltage from -GND to -Vy, the PDP can be driven more efficiently by switching the setdown method according to the panel margin.

Claims (9)

panel; A drive integrated circuit unit supplying a driving voltage to the panel; An energy recovery circuit unit for supplying and recovering a sustain voltage to the drive integrated circuit unit; A setup supply unit for supplying a sustain driving and setup voltage to the drive integrated circuit unit; A set down supply unit supplying a set down voltage to the drive integrated circuit unit; A set down controller configured to adjust the set down voltage, And the set down voltage controlled by the set down controller is a set down start voltage. delete delete The method of claim 1, The set down control unit; And a set down voltage is lowered from the sustain voltage (Vs) to the write scan voltage (-Vy) during the initialization period. The method of claim 1, The set down control unit; And a set down voltage is lowered from the ground (GND) to the write scan voltage (-Vy) during the initialization period. The method of claim 1, And the set down voltage is different from a set down voltage of another subfield in at least one of the plurality of subfields. The method of claim 6, And the setdown voltage is changed in correspondence to a weight of the subfield. The method of claim 1, And the set down voltage is different from a set down voltage of another frame in at least one of a plurality of frames. The method of claim 8, And the set down voltage is changed in correspondence to the gray level of the frame.

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