KR100703562B1 - Silicon controlled rectifier for electrostatic discharge protection and its manufacturing method - Google Patents

Abstract

The present invention relates to an electrostatic discharge protection circuit for reducing the triggering voltage by improving the structure and connection structure of the semiconductor region and maximizing the latch-up phenomenon to operate as a stable ESD protection circuit. The silicon controlled rectifier for electrostatic discharge protection according to the present invention. The substrate; A P-type well region formed on the substrate; An N-type well region formed in a portion of the P-type well region; A first P + region formed on the N well region and connected to an anode, a first N + region and a second N + region formed between the P type well region and the N type well region and connected to the anode; A first doped region; A second doped region formed on the P-type well region and including a third N + region and a second P + region connected to a cathode; And a gate electrode connected to the cathode and formed between the second N + region and the third N + region.

According to the present invention, ESD can be extinguished in a single product due to the high latch-up characteristic, so that the ESD protection circuit can be minimized, and the ESD can be immediately reacted / isolated through the lower triggering voltage characteristic. This minimizes the amount of ESD stress delivered to the devices.

Description

Silicon controlled rectifier for electrostatic discharge protection and its manufacturing method {Silicon Controlled Rectifier for electrostatic discharge protection and method

1 is a side cross-sectional view illustratively showing the internal structure of a typical GGNMOS.

Figure 2 is a side cross-sectional view illustrating the internal structure of a typical GGSCR by way of example.

Figure 3 is a side cross-sectional view illustratively showing the semiconductor structure of the silicon controlled rectifier for electrostatic discharge protection according to an embodiment of the present invention.

Figure 4 is a flow chart illustrating a method of manufacturing a silicon controlled rectifier for electrostatic discharge protection according to an embodiment of the present invention.

5 is a circuit diagram illustrating a connection configuration between semiconductor elements constituting a silicon controlled rectifier for electrostatic discharge protection according to an embodiment of the present invention.

6 is a graph showing operation characteristics when a reverse bias voltage is applied to a general GGNMOS and a GGSCR.

7 is a graph showing the operation characteristics when the reverse bias voltage is applied to the silicon control rectifier for electrostatic discharge protection according to an embodiment of the present invention.

FIG. 8 is a top view exemplarily comparing shapes of an electrostatic discharge protection silicon controlled rectifier and a general GGNMOS according to an embodiment of the present invention when implemented on a substrate; FIG.

<Explanation of symbols for main parts of drawing>

100: silicon controlled rectifier for electrostatic discharge protection

105: P type well region 110: N type well region

115: first P + region 120: first N + region

125: second N + area 130: third N + area

135: second P + region 140, 145, 150, 155, 160: oxide film

170: gate electrode 171: spacer

172: capping film 173: gate insulating film

185: anode 190: cathode

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to improve the structure of the semiconductor region and the connection structure between the semiconductor regions to lower the triggering voltage, maximize the latch-up phenomenon (Eletro) Static Discharge (SCR) A Sillicon Controlled Rectifier (SCR) for protection against static discharges, which is operated by a protection circuit.

Currently, mobile communication terminals such as mobile phones, smart phones, PDAs (Personal Digital Assistants), music phones, etc. are widely used. These mobile communication terminals have a built-in communication module for performing wireless communication, and the communication modules are usually front-end. Implemented in the form of modules.

A front end module (FEM) refers to a complex component in which various electronic components are serially implemented on a single substrate and the integration space thereof is minimized. For example, a diplexer, a duplexer (FLEX) For example, components such as a duplexer, a transmitter (Tx) filter, and a receiver (Rx) filter may be configured as a single module to minimize the size of the chip.

Such integrated devices may be damaged or unstable by internal circuitry when exposed to an ESD (electrostatic discharge) phenomenon, which means that when an electronic device comes into contact with an object capable of transferring charges, the static electricity is discharged to the circuit. It refers to the phenomenon that affects.

For example, an ESD phenomenon may occur even when a human body contacts an antenna or an external connector of a mobile communication terminal.

In order to protect the internal devices from such an ESD phenomenon, an electronic circuit is provided with an ESD protection circuit, which is implemented with components such as an inductor, a diode, and a transistor.

In general, GGNMOS (Grounded Gate NMOS) is widely used in ESD protection circuits. The GGNMOS is briefly described as follows.

1 is a side cross-sectional view illustrating the internal structure of a general GGNMOS 10 by way of example.

According to FIG. 1, the general GGNMOS 10 sequentially has a P + region 12, an N + region 13, a polysilicon 16, an N + region 14, and a P + region 15 in the P type well region 11. Is formed and the first P + region 12 is connected to the first ground terminal 17.

The first N + region 13 is connected to the drain terminal 18, and the polysilicon 16, the second N + region 14, and the second P + region 15 are connected to the second ground terminal 19. The polysilicon 16 is operated at the gate end and the second N + region 14 is operated at the source end.

In the GGNMOS 10 having such a structure, the N + region 13 as the drain terminal, the P type well region 11, and the N + region 14 as the source terminal are operated as NPN type bipolar transistors to ground the ESD generated on the circuit. The triggering voltage is determined by reverse breakdown voltage between the N + region 13 and the P-type well region 11 as the drain stage.

The GGNMOS 10 has a low triggering voltage, and since the operation of the ESD protection circuit is performed after the actual triggering voltage, the GGNMOS 10 exhibits excellent characteristics as an ESD protection circuit in this respect, whereas the latch-up phenomenon does not occur rapidly. There is a lack of protection for internal circuits from instantaneous ESD.

This will be described later with reference to FIG. 6.

In addition, the SCR, which is one of the semiconductor devices, has a latch-up characteristic of which current flow is almost infinite after being triggered, and thus, an ESD protection circuit can be configured with a small size.

For this reason, there have been attempts to implement ESD protection circuits using SCR, but there is a limit to overcome the problem of high triggering voltage.

For example, in order to overcome the problems of the conventional SCR, a grounded gate SCR (GGSCR) has been proposed, which will be briefly described with reference to FIG. 2.

2 is a side cross-sectional view illustrating the internal structure of a general GGSCR 20 by way of example.

According to FIG. 2, in the general GGSCR 20, an N-type well region 22 is formed in a P-type well region 21, and a first P + region 23 and a first N + are formed in the N-type well region 22. Region 24 is formed.

In addition, the second N + region 25 is formed over the P-type well region 21 and the N-type well region 22, and in turn, the polysilicon 28, the third N + region 26, and the second A P + region 27 is formed, wherein the first P + region 23 and the first N + region 24 are connected to the anode electrode 29a, and the polysilicon 28, the third N + region 26, and the first P + region 27 are formed. The 2 P + region 27 is connected to the cathode electrode 29b.

In the above configuration, in the latch-up operation, the first P + region 23, the N-type well region 22, and the P-type well region 21 connected to the anode electrode 29a are operated as PNP bipolar transistors, and the cathode electrode ( The third N + region 26, the P-type well region 21, and the N-type well region 22 connected to 29b) are operated as NPN bipolar transistors, so that a loop formed between the two transistors assists with mutual amplification.

In order to lower the trigger voltage of the GGNMOS 20 having excellent latch-up characteristics, a second N + region is formed between the N type well layer 22 and the P type well layer 21 in the structure of the conventional MSCR as shown in FIG. (25) is further formed and the structure is improved to connect the polysilicon gate (28) to the ground terminal (29b (cathode electrode)), but the triggering voltage is lower than the conventional MSCR, but to the GGNMOS 10 In comparison, the triggering voltage is still high, which is insufficient to operate as an ESD protection circuit.

This high triggering voltage indicates that the operating point where the NP reverse breakdown occurs during the first PNP operation is the second N + region 25 and P between the N-type well region 22 and the P-type well region 10. This is because between the type well regions 10, that is, since current must pass through the first P + region 23 and the N type well region 22 to reach the second N + region 25, the triggering voltage increases. Is generated.

Accordingly, the present invention is stably operated as an ESD protection circuit by presenting a new structure based on a structure corresponding to a high latch-up characteristic GGSCR and a low triggering voltage characteristic GGNMOS. It is an object of the present invention to provide a silicon controlled rectifier for electrostatic discharge protection and a method thereof.

In order to achieve the above object, the electrostatic discharge protection silicon controlled rectifier according to the present invention includes a substrate; A P-type well region formed on the substrate; An N-type well region formed in a portion of the P-type well region; A first P + region formed on the N well region and connected to an anode, a first N + region and a second N + region formed between the P type well region and the N type well region and connected to the anode; A first doped region; A second doped region formed on the P-type well region and including a third N + region and a second P + region connected to a cathode; And a gate electrode connected to the cathode and formed between the second N + region and the third N + region.

The second N + region of the silicon controlled rectifier for electrostatic discharge protection according to the present invention is operated as a drain terminal, and the third N + region is operated as a source terminal.

Further, a salicide block is formed in the second N + region of the silicon controlled rectifier for electrostatic discharge protection according to the present invention.

The first P + region, the N-type well region and the P-type well region of the silicon controlled rectifier for electrostatic discharge protection according to the present invention form a PNP transistor, and the N-type well region, the P-type well region and the The third N + region forms an NPN transistor to perform a latch-up operation, and the second N + region, the P-type well region, and the third N + region form an NPN transistor to control triggering voltage.

In order to achieve the above another object, the electrostatic discharge protection silicon controlled rectifier manufacturing method according to the present invention comprises the steps of forming a substrate; Forming a P-type well region on the substrate; Forming an N-type well region in a portion of the P-type well region; A first P + region and a first N + region are formed in the N-type well region, and a second N + region is formed over the P-type well region and the N-type well region, and a third N + region is formed in the P-type well region; Forming a second P + region; Forming a silicide block in the second N + region; Forming a gate electrode between the second N + region and the third N + region; And an anode is formed on the first P + region, the first N + region, and the second N + region, and a cathode is formed on the gate electrode, the third N + region, and the second P + region.

In addition, the step of forming the anode and the cathode of the method for fabricating a silicon controlled rectifier for electrostatic discharge protection according to the present invention may include the first P + region, the second P + region, the first N + region, the second N + region, and the third N +. Forming an oxide film region over each of the doped regions of the region; Forming an insulating film layer; Processing a via hole process over the doped region and the gate electrode; And forming the anode and the cathode.

Hereinafter, a silicon controlled rectifier (SCR) for electrostatic discharge protection according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a side cross-sectional view illustrating a semiconductor structure of an electrostatic discharge protection silicon controlled rectifier according to an embodiment of the present invention, and FIG. 4 is a method of manufacturing a silicon controlled rectifier for electrostatic discharge protection according to an embodiment of the present invention. It is a flow chart.

Hereinafter, a semiconductor structure and a fabrication method of a silicon controlled rectifier for electrostatic discharge protection according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

According to FIG. 3, in the electrostatic discharge protection silicon controlled rectifier 100 according to the embodiment of the present invention, a P type well region 105 is formed on a substrate (S100), and a portion of the P type well region 105 is N type. The well region 110 is formed (S105).

A first P + region 115 and a first N + region 120 are formed in the N-type well region 110, and a third N + region 130 and a second P + region 135 are formed in the P-type well region 105. ) Is formed. Further, a second N + region 125 is formed over the P-type well region 105 and the N-type well region 110 (S110).

On the surface of the P-type well region 105 between the second N + region 125 and the third N + region 130, a gate electrode 170 (a detailed description of the gate electrode will be described later) is formed (S115). ).

Above the first P + region 115, the second P + region 135, the first N + region 120, the second N + region 125, and the third N + region 130, the oxide film regions 140, 145, 150, 155, and 160 are formed respectively (S120), and the oxide layer regions 140, 145, 150, 155, and 160 may increase the bonding force with the via holes 175, 176, 177, 179, and 180, and increase current supply efficiency. As a role, for example, it may be formed of an oxide film material such as SiO ₂ or Si ₃ N ₄ .

Subsequently, an insulating layer 138 is formed to include the oxide regions 140, 145, 150, 155 and 160 and the gate electrode 170. The insulating layer 138 is a layer belonging to an intermetal dielectric (IMD) dielectric. It may be made of FSG (FxSiOy; Fluorinated Silicate Glass) or USG (Undoped silicated Galss) material (S125).

When the insulating layer 138 is formed, the via holes 175, 176, 177, 178, 179, from the surface of the insulating layer 138 to the oxide layer regions 140, 145, 150, 155, 160 and the gate electrode 170 are formed. 180 is processed (S130), the anode (185) and the cathode (Cathode 190) is formed thereon (S135).

Accordingly, the first P + region 115, the first N + region 120, and the second N + region 125 are connected to the anode 185 through the via holes 175, 176, 177, 178, 179, and 180. The gate electrode 170, the third N + region 130, and the second P + region 135 have a structure in which electricity is supplied to the cathode 190.

In this configuration, the second N + region 125 has a terminal connected to the anode 185 as a drain, and the third N + region 130 has a source connected to the cathode 190 as a source. It will be operated as a source.

In addition, the cathode 190 may be connected to the ground terminal. Each component of the electrostatic discharge protection type silicon controlled rectifier 100 according to the present invention may operate in the forward direction of the N-diode when an ESD negative stress is generated. Because of the characteristics, the operation will be described only when an ESD positive stress occurs that causes a problem of the ESD protection operation.

Usually, the N + regions 120, 125, and 130 are formed by implanting Group 5 impurities such as P ⁻ , As ^−, and the P + regions 115, 135 are formed by implanting Group 3 impurities such as B ^+, and the gate The electrode 170 is made of polysilicon.

The gate electrode 170 is formed of a capping layer 172 of Si ₃ N _{4 on} the polysilicon 174, and an oxide pad layer (gate insulating layer) 173 of SIO ₂ is disposed below the gate electrode 170.

The capping layer 172 prevents the polysilicon 174 from being oxidized or physically damaged, improves contact with the via hole, and the gate insulating layer 173 has a small stress on the surface of the polysilicon 174. It acts as a buffer to inhibit the oxidized family from seeping into the active region underneath the nitride film.

In addition, a spacer (sider or side wall) 171 is formed on the side surface of the polysilicon 174, which prevents contact with the gate electrode 170 when the via hole is formed and prevents the gate electrode 170 during the etching process. ) To protect the device.

A salicide block is formed in the second N + region 125, which may correspond to a structure corresponding to the drain region of the GGNMOS 10 described above, and further includes a second N + region 125. Is a structure corresponding to the GGSCR 20.

That is, the silicon controlled rectifier 100 for electrostatic discharge protection according to the embodiment of the present invention has a structure corresponding to the GGSCR 20 as a basic skeleton, and the GGNMOS 10 as shown by a block A indicated by a dotted line in FIG. 3. It can be seen that the structure corresponding to.

When manufacturing a device such as a MOSFET, the gate and drain-source contact patterns are simultaneously made through a single metal process (polysilicon for the gate is formed and ion and implantation are used to form the drain and source without gate overlap). When they are in electrical contact with the semiconductor surface (a CVD-oxide layer is formed to form a spacer, then a metal layer is deposited and heated to form a silicide layer simultaneously in the gate poly and drain-source), between the drain-source and the gate The parasitic capacitance caused by the overlap of the chip may be eliminated, and the contact area between the pattern and the drain-source may be increased, thereby reducing the contact resistance and the drain-source internal resistance.

The structure formed through such a process is called a salicide block, and the silicide material includes silicide-CoSi ₂ , NiSi ₂ , PtSi, Pt ₂ Si, group 4 metal silicide-TiSi ₂ , Silicides made of melting point metals-MoSi ₂ , TaSi ₂ , WSi _2, and the like.

In the conventional GGSCR 20, the current from the P + region 23 on the anode side passes through the N-type well region 22 and is located between the N-type well region 22 and the P-type well region 21. While the triggering voltage is increased because the N + region 26 is to be transmitted, the structure of the silicon-controlled rectifier 100 for electrostatic discharge protection according to the present invention provides that the second N + region 125 is connected to the anode 185. Direct energization and the formation of salicide blocks significantly reduce the triggering voltage.

That is, according to the present invention, the structure of forming the second N + region 125, the structure of connecting the anode 185, the structure of forming the salicide block, the structure of connecting the gate electrode 170 and the cathode 190, etc. The silicon controlled rectifier 100 for electrostatic discharge protection has a triggering voltage characteristic that is higher than that of the conventional GGNMOS 10.

Thus, ESD protection can be quickly achieved after a low triggering voltage and maximized latchup after triggering to isolate fast and high discharged ESD.

On the other hand, in the conventional GGNMOS 10, since the latch-up phenomenon occurs at a low rate, it was necessary to provide a large number to process a predetermined ESD in a short time.

5 is a circuit diagram illustrating a connection configuration between semiconductor devices constituting the silicon controlled rectifier 100 for electrostatic discharge protection according to an embodiment of the present invention.

Referring to FIG. 5, a circuit form of each element constituting the semiconductor structure shown in FIG. 3 is illustrated. A “B” element includes a first P + region 115, an N-type well region 110, and a P-type well region. The PNP transistor of 105 is shown in the figure, and the " D " element is a diagram of the PNP transistor of the P type well region 105, the second N + region 125, and the first P + region 115. FIG.

4 shows the NPN transistors of the second N + region 125, the P-type well region 105 and the third N + region 130, and the "C" element represents the third N +. NPN transistors of the region 130, the P-type well region 105 and the N-type well region 110 are illustrated.

In this way, the NPN transistor and the PNP transistor form a loop to cause a cyclical operation to promote the amplification of the other transistors, and excessive current flows from the power supply Vdd to the ground power supply GND ( Latchup phenomenon occurs).

Therefore, the hybrid SCR 130 according to the present invention can handle almost infinite ESD current.

FIG. 6 is a graph illustrating an operation characteristic when a reverse bias voltage is applied to a general GGNMOS 10 and a GGSCR 20. FIG. 7 is a reverse direction to a silicon controlled rectifier 100 for electrostatic discharge protection according to an embodiment of the present invention. It is a graph showing the operating characteristics when the bias voltage is applied.

First, according to FIG. 6, the reference line "F" represents a reference value of the triggering voltage for operating with the ESD protection element, and the measurement line "H" is a display line illustrating the operating characteristics of the GGNMOS 10. In addition, the measurement line "G" is a graph which plots the operating characteristics of the GGSCR 20.

In the graphs of FIGS. 6 and 7, the x axis represents voltage and the y axis represents current.

As shown in Fig. 6, the GGNMOS 10 shows an excellent side because the triggering voltage is located within the reference line "F", but since the latch-up phenomenon occurs slowly (the current increase rate after the brake down phenomenon is low (slope of the rising curve) Low), the GGSCR 20 exhibits an excellent aspect of the latch-up phenomenon (high current increase rate after the break-down phenomenon (high slope of the rising curve)). As a result, the triggering voltage is located outside of the baseline "F", which is also lacking as an ESD protection circuit.

However, when the operation characteristic (I) of the electrostatic discharge protection silicon control rectifier 100 according to the present invention shown in FIG. 7 is seen, the latching phenomenon is rapidly made even though the triggering voltage is located inside the reference line "F" (the rising Since the slope of the straight section maintains a sharp state), it can be seen that the ESD protection is faithfully performed.

FIG. 8 is a top view exemplarily comparing shapes of an electrostatic discharge protection silicon controlled rectifier 100 and a general GGNMOS 10 according to an exemplary embodiment of the present invention when implemented on a substrate.

Figure 8 (a) is a top view showing a form that is implemented on a substrate, when the general GGNMOS 10 is used in an ESD protection circuit, Figure 8 (b) is for electrostatic discharge protection according to the present invention When the silicon control rectifier 100 is used in an ESD protection circuit, it is a top view showing a form implemented on a substrate. As described above with reference to FIGS. 6 and 7, the GGNMOS 10 is gradually latched up. As it progresses, it must be provided in plurality in order to handle the sudden ESD current.

For example, since the GGNMOS 10 can safely isolate an ESD current of about 20 mA, in a situation where an ESD current of about 200 mA is generated, the GGNMOS 10 should be implemented in 8 to 10 numbers, as shown in FIG. .

On the other hand, the silicon controlled rectifier 100 for electrostatic discharge protection according to the present invention has a low triggering voltage, thereby not only satisfying the initial condition of the ESD protection circuit, but also rapidly causing a latchup phenomenon, as shown in FIG. One component can isolate ESD currents of about 200mA.

Therefore, the silicon controlled rectifier 100 for electrostatic discharge protection according to the present invention can be formed as a single product and can contribute to reducing the size of the ESD protection circuit and further, the overall size of the communication module.

The present invention has been described above with reference to the preferred embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not possible that are not illustrated above. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

According to the silicon-controlled rectifier for electrostatic discharge protection according to the present invention, ESD can be extinguished in a single unit due to its high latch-up characteristic, thereby minimizing ESD protection circuits and generating ESD through a lower triggering voltage characteristic. If possible, it is possible to immediately react / isolate, thus minimizing the amount of ESD stress delivered to the devices.

Claims (8)

Board; A P-type well region formed on the substrate; An N-type well region formed in a portion of the P-type well region; A first P + region formed on the N well region and connected to an anode, a first N + region and a second N + region formed between the P type well region and the N type well region and connected to the anode; A first doped region; A second doped region formed on the P-type well region and including a third N + region and a second P + region connected to a cathode; And And a gate electrode connected to the cathode and formed between the second N + region and the third N + region. The method of claim 1, wherein the cathode Silicon controlled rectifier for electrostatic discharge protection, characterized in that connected to the ground terminal. The method of claim 1, wherein the gate electrode Silicon controlled rectifier for electrostatic discharge protection, characterized in that the polysilicon. The method of claim 1, The second N + region is operated as a drain terminal, And the third N + region is operated as a source terminal. The method of claim 1, wherein the second N + region is A silicon controlled rectifier for electrostatic discharge protection, characterized in that a salicide block is formed. The method of claim 1, The first P + region, the N-type well region and the P-type well region form a PNP transistor, and the N-type well region, the P-type well region and the third N + region form an NPN transistor to latch up operation. Make up, And the second N + region, the P-type well region and the third N + region form NPN transistors so that the triggering voltage is controlled. Forming a substrate; Forming a P-type well region on the substrate; Forming an N-type well region in a portion of the P-type well region; A first P + region and a first N + region are formed in the N-type well region, and a second N + region is formed over the P-type well region and the N-type well region, and a third N + region is formed in the P-type well region; Forming a second P + region; Forming a silicide block in the second N + region; Forming a gate electrode between the second N + region and the third N + region; And And an anode is formed on the first P + region, the first N + region, and the second N + region, and a cathode is formed on the gate electrode, the third N + region, and the second P + region. Method of manufacturing silicon controlled rectifier for discharge protection. The method of claim 7, wherein the anode and the cathode is formed Forming an oxide film region over the doped regions of the first P + region, the second P + region, the first N + region, the second N + region, and the third N + region; Forming an insulating film layer; Processing a via hole process over the doped region and the gate electrode; And The anode and the cathode is formed, comprising the step of forming a silicon controlled rectifier for electrostatic discharge protection, characterized in that it comprises.

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