KR100699915B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to reduce the bridge between storage node contacts by forming an etch blocking pattern of bar shape. A first interlayer dielectric having contact pads(110a,110b) is formed on a substrate(100). Bit line structures are elongated to a first direction on the first interlayer dielectric. Insulating spacers are formed both sidewalls of the bit line structures. An etch blocking pattern of bar shape is formed between the bit line structures and elongated to a second direction. A second interlayer dielectric(122) is covered on the bit line structures. Storage node contacts(142) are formed between the bit line structures having the insulating spacer to connect the contact pad, wherein the upper part is wider than the lower part, and the upper part is contacted with the etch blocking pattern to the first direction and contacted with the insulating spacer to the second direction.

Description

Semiconductor device and method for manufacturing the same

1A and 1B are cross-sectional views of a DRAM device according to an embodiment of the present invention.

2A to 10B are cross-sectional views illustrating a method of manufacturing a DRAM device according to the present embodiment.

11 is a plan view at steps 4a and 4b.

12 is a plan view at steps 6a and 6b.

The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device including a contact having a wide top surface and a method of manufacturing the same.

Recent semiconductor devices require high speed operation while having a high storage capacity in terms of functionality. To this end, the semiconductor devices have been developed with manufacturing techniques in order to improve the degree of integration, response speed and reliability.

As the semiconductor device, a DRAM device having free input and output of information and having a high capacity is used for general purposes. Each memory cell of the DRAM device includes one access transistor and one storage capacitor.

As the degree of integration of the memory cells is increased, the horizontal area in which each cell is formed is further reduced. Therefore, the formation of a capacitor having a high capacitance in the reduced area is a more important problem.

In order to increase the effective area of the electrode included in the capacitor is changed from the initial planar capacitor structure to the stack (stack) or trench (trench) capacitor structure, the stack capacitor structure is also changed to the cylindrical capacitor structure. .

In the case of the DRAM device, the cylindrical capacitors should be formed without being in contact with each other in a narrow area. However, since the capacitor must be electrically connected to any one region of the source / drain of the access transistor, the region in which the capacitor is formed is defined according to the position of the lower source / drain. As a result, the margin between neighboring capacitors is so narrow that frequent contact between the capacitors occurs.

Recently, a process has been developed to allow the capacitors to be widely disposed between neighboring capacitors regardless of the position of the underlying source / drain. Specifically, the contact margin of the storage node contact is increased by forming a top surface of the storage node contact connecting to the capacitor to have a relatively wide shape or by forming a landing pad on the top surface of the storage node contact. .

However, when the upper surface of the storage node contacts is formed relatively wide, bridge failures between the storage node contacts may easily occur because the storage node contacts are too close to each other. In addition, when the landing pad is formed on the upper surface of the storage node contact, a deposition and a photographing process must be additionally performed, and when the landing pad is misaligned, a defect may occur.

Therefore, there is a need for a contact and a method of forming the same that have a sufficiently large area of the upper contact surface but do not cause bridge failure between neighboring contacts.

Accordingly, a first object of the present invention is to provide a semiconductor device including a contact having a large area of an upper contact surface and reducing bridge defects between contacts.

A second object of the present invention is to provide a method of manufacturing the semiconductor device.

A semiconductor device of the present invention for achieving the first object described above comprises a first interlayer insulating film provided on a substrate and including contact pads therein, and a bit line structure extending in a first direction on the first interlayer insulating film. And insulating layer spacers partially surrounding both sidewalls of the bit line structures, and a bar-type etching blocking pattern provided between the bit line structures and extending in a second direction perpendicular to the first direction. And a second interlayer insulating film covering the bit line structures and the bit line structures having the insulating film spacers electrically connected to the contact pads, the upper portion having a wider shape than the lower portion. Stokes having a shape in contact with the etch blocking pattern in the first direction and in contact with the insulating film spacer in the second direction Ridge node contacts and capacitors provided on an upper surface of the storage node contacts.

The etch blocking pattern is formed of silicon nitride.

In the method of manufacturing a semiconductor device of the present invention for achieving the above-described second object, a first interlayer insulating film including contact pads is formed on the substrate. Bit line structures extending in a first direction are formed on the first interlayer insulating layer. A second interlayer insulating layer having bar openings extending in a second direction perpendicular to the first direction while covering the bit line is formed. Etch blocking patterns are formed by filling an etch blocking layer in the openings. An upper contact partially etching the second interlayer insulating layer between the bit line structures having the insulating layer spacer to contact the etch blocking pattern in the first direction and to contact the sidewall of the bit line structure in the second direction Form a hole. An insulating layer spacer is formed on an upper sidewall of the bit line structure exposed by the upper contact hole. The second interlayer insulating layer and the first interlayer insulating layer positioned under the upper contact hole are partially etched to form a lower contact hole having a narrower inner width than the upper contact hole and exposing an upper surface of the contact pad. A conductive material is filled in the upper contact hole and the lower contact hole to form a storage node contact having a shape in contact with the etch blocking pattern in the first direction and in contact with the insulating layer spacer in the second direction. Next, capacitors are formed on upper surfaces of the storage node contacts.

The etch blocking pattern is formed using silicon nitride.

In order to form the upper contact hole, a line-shaped mask pattern extending in the second direction is formed on the second interlayer insulating layer, the bit line structure, and the etch blocking pattern. The preliminary upper contact hole may be formed by anisotropically etching the bit line structure and the region defined by the mask pattern using the mask pattern as an etch mask. The preliminary upper contact hole is isotropically etched to form an upper contact hole exposing the etch blocking pattern.

By forming an etch blocking pattern as described above, bridge failures between neighboring storage node contacts may be reduced. In addition, since the upper surface of the storage node contact is formed to be relatively wider than the lower surface of the storage node contact, the contact margin with the capacitor is increased, and the capacitors may be arranged to be spaced apart from each other as much as possible.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are cross-sectional views of a DRAM device according to an embodiment of the present invention.

1A is a cross-sectional view cut in the word line direction (second direction), and FIG. 1B is a cross-sectional view cut in the bit line direction (first direction).

1A and 1B, a gate 104 is provided on a substrate 100 having an isolated active region. The isolated active region has a shape extending in a first direction and the gate 104 has a line shape extending in a second direction perpendicular to the first direction. Two gates are provided in the isolated active region.

Specifically, the gate 104 has a shape in which a gate insulating layer pattern, a gate electrode pattern, and a hard mask pattern are stacked. That is, the gate 104 is provided as a word line of the DRAM device.

Both side walls of the gate 104 are provided with a first spacer 106 made of silicon nitride.

Impurity regions (not shown) are provided below the substrate surfaces on both sides of the gate 104 to serve as a source and a drain. The first impurity region corresponding to the center portion of the isolated active region becomes a region for connecting with the bit line, and the second impurity regions corresponding to both sides of the active region becomes a region for connecting with the capacitor.

A lower first interlayer insulating layer 108 filling the gate 104 is provided. Contact pads 110a and 110b are provided in the lower first interlayer insulating layer 108 to connect the first impurity region and the second impurity region, respectively.

An upper first interlayer insulating layer 112 is further provided on the lower first interlayer insulating layer 108 including the contact pads 110a and 110b. A bit line contact (not shown) connected to the first contact pad 110a connected to the first impurity region is provided in the upper first interlayer insulating layer 112. The bit line contact may be formed of, for example, a barrier metal layer pattern and a tungsten pattern.

The lower and upper first interlayer insulating layers 108 and 112 are made of silicon oxide.

Bit line structures 120 extending in the first direction are provided on the first upper interlayer insulating layer 112. The bit line structure 120 has a shape in which conductive line patterns 114 and 116 and a capping layer pattern 118 in a line shape are stacked. In this case, the conductive layer patterns 114 and 116 may have a metal pattern, a polysilicon pattern, a metal silicide pattern, or a structure in which the patterns are stacked. For example, the conductive layer patterns 114 and 116 may have a structure in which the barrier metal layer pattern 114 and the tungsten pattern 116 are stacked as illustrated. A portion of the lower surface of the conductive layer patterns 114 and 116 is in contact with the bit line contact (not shown). Therefore, the conductive layer patterns 114 and 116 are electrically connected to the first impurity region through the bit line contact.

Second spacers 136 are provided to surround both sidewalls of the bit line structures 120. The second spacer 136 may be formed on sidewalls of the capping layer pattern 118 included in the bit line structure 120. The second spacer 136 may be made of silicon nitride. That is, the second spacer 136 made of silicon nitride having a higher dielectric constant than silicon oxide is not formed on sidewalls of the conductive layer patterns 114 and 116 included in the bit line structure 120.

Etch blocking patterns 128 provided between the bit line structures 120 and extending in a second direction perpendicular to the first direction are provided. The etch blocking pattern 128 is provided at a portion where the storage node contact 142 is not formed, that is, at a portion corresponding to the storage node contacts 142.

The etch blocking pattern 128 is provided to prevent neighboring contacts from being connected to each other by excessively etching the interlayer insulating layer in a process of forming a contact hole by etching the interlayer insulating layer. Therefore, the etching selectivity with respect to the interlayer insulating layer is preferably formed of a material, specifically, the etching blocking pattern 128 may be formed of silicon nitride.

A second interlayer insulating layer 122 covering the bit line structure 120 is provided on the upper first interlayer insulating layer 112. The second interlayer insulating layer 122 may be made of silicon oxide. The second interlayer insulating layer 122 has a shape in which a portion of the etch blocking pattern 128 and a portion of the storage node contact 142 are removed. That is, the etch blocking pattern 128 and the storage node contact 142 are formed to fill the inside of the portion opened in the second interlayer insulating layer 122.

A storage node contact 142 is formed to penetrate the second interlayer insulating layer 122 and the upper first interlayer insulating layer 112 and to be connected to the second contact pad 110b connecting to the second impurity region. The storage node contact 142 has a shape in which the upper portion is wider than the lower portion.

In detail, an upper portion of the storage node contact 142 is in contact with the etch blocking pattern 128 in the first direction and in contact with the second spacer 136 in the second direction.

An upper portion of the storage node contact 142 has a shape wider in the first direction than in the second direction. The storage node contact 142 may extend from the lower portion of the storage node contact 142 to the same size on both sides of the first direction.

A silicon nitride film is formed along the surface of the upper portion of the storage node contact 142.

The storage node contact 142 may be made of polysilicon.

Capacitors including a storage electrode 144, a dielectric layer (not shown), and a plate electrode (not shown) are provided on upper surfaces of the storage node contacts 142. The capacitor is disposed at a position oriented in one side of the first direction from a center of an upper surface of the storage node contacts 142. In total, the capacitors are arranged diagonally to each other. This widens the spacing between neighboring capacitors.

In a DRAM device according to an exemplary embodiment, upper surfaces of storage node contacts extend to both sides in a first direction. Therefore, the spacing between the capacitors connecting to the storage node contacts can be wider. In addition, an etch blocking pattern is provided on one side wall of the upper portion of the storage node contact. Therefore, the bridge failure of the storage node contacts can be reduced.

In addition, a second spacer made of silicon nitride is not formed between the conductive layer pattern included in the bit line structure and the storage node contact. That is, a second interlayer insulating layer having a lower dielectric constant than that of silicon nitride is formed between the conductive layer pattern included in the bit line structure and the storage node contact. Therefore, parasitic capacitance generated between the conductive layer pattern and the storage node contact is reduced.

Hereinafter, a method suitable for manufacturing the DRAM device described above will be described.

2A to 10B are cross-sectional views illustrating a method of manufacturing a DRAM device according to the present embodiment.

2A to 10B, each a diagram is a cross-sectional view of the DRAM device in the word line direction (second direction), and each b diagram is a cross-sectional view taken in the bit line direction (first direction).

FIG. 11 is a plan view in steps 4a and 4b, and FIG. 12 is a plan view in steps 6a and 6b.

2A and 2B, a conventional shallow trench device isolation process is performed on the silicon substrate 100 to separate the isolated active region and the device isolation region 102 having the first direction in the longitudinal direction.

Specifically, a buffer oxide film (not shown) is formed on the silicon substrate 100. The buffer oxide film is a film for relieving stress when forming a silicon nitride film later. Subsequently, a silicon nitride film (not shown) is formed on the buffer oxide film. Subsequently, a part of the nitride film is removed by a normal photolithography process to form a nitride film pattern. The buffer oxide layer is dry-etched using the nitride layer pattern as an etching mask to form a buffer oxide layer pattern. Subsequently, the exposed substrate is etched to a predetermined depth using the nitride film pattern as an etching mask to form a trench. In this case, an anti-reflection layer (ALR) (not shown) may be formed on the nitride layer to increase the margin of the photolithography process for the active pattern. A silicon oxide film is embedded in the trench and planarized to expose the silicon nitride film pattern. The silicon isolation layer pattern and the buffer oxide layer pattern are removed by a wet etching process to separate the device isolation region 102 and the active region.

After the thin gate oxide film (not shown) is grown on the surface of the active region by thermal oxidation, a gate electrode film (not shown) and a hard mask film (not shown) made of a conductive material are formed. Next, the hard mask film and the gate electrode film are patterned to form a gate 104 in which a gate electrode pattern and a hard mask pattern are stacked.

The gate 104 has a line shape extending in a second direction perpendicular to the first direction. The gate 104 is used in common with the word line. In the isolated active region, two gates 104 are formed side by side.

First spacers 106 formed of silicon nitride are formed on both sides of the gate 104. Thereafter, by implanting impurities using the gate 104 as a mask, first and second impurity regions (not shown) to be provided as a source / drain under the substrate on both sides of the gate 104 are formed. do. An impurity region formed at a center portion of the isolated active region is a first impurity region connected to a bit line, and an impurity region formed at both edges of the isolated active region is a second impurity region connected to a storage electrode of a capacitor. to be.

Thereafter, a lower first interlayer insulating film 108 is formed to sufficiently fill the gate, and the lower first interlayer insulating film 108 is partially etched by a conventional photolithography process to expose the source / drain regions, respectively. A self-aligned contact hole (not shown) is formed. The lower first interlayer insulating layer 108 may be formed using silicon oxide.

Next, after the doped polysilicon is deposited in the contact hole, a planarization process is performed to form first and second contact pads 110a and 110b connecting to the first and second impurity regions. In the following description, a contact pad connected to the first impurity region is referred to as a first contact pad 110a and a second contact pad 110b connected to the second impurity region.

3A and 3B, an upper first interlayer insulating layer 112 is formed on the lower first interlayer insulating layer 110 including the first and second contact pads 110.

Subsequently, a predetermined portion of the upper first interlayer insulating layer 112 is etched to form a bit line contact hole (not shown) for selectively exposing only the first contact pad 110a. Subsequently, a barrier metal layer (not shown) is formed on the bit line contact hole and the first upper interlayer insulating layer 112. The barrier metal film is formed of a titanium, a titanium nitride film, a tantalum, a tantalum nitride film, or a film in which at least two of them are stacked. Subsequently, a tungsten film (not shown) is formed on the barrier metal film.

A silicon nitride film is formed on the tungsten film as a capping film (not shown). The capping film serves as a hard mask when the tungsten film is etched, and then serves to protect the tungsten film during the self-aligned contact forming process. Therefore, the capping film should be thick enough to remain above a predetermined thickness until the patterning process and the contact forming process of the tungsten film are completely performed.

A first photoresist pattern (not shown) is formed on the capping layer to form a bit line structure. Subsequently, the capping layer is etched using the first photoresist pattern to form a capping layer pattern 118. Thereafter, the first photoresist pattern is removed by a conventional ashing and stripping process.

The tungsten film and the barrier film are etched anisotropically using the capping film pattern 118 as an etching mask. Through the etching process, the bit line structure 120 and the bit line contact (not shown) including the barrier layer pattern 114, the tungsten pattern 116, and the capping layer pattern 118 are simultaneously formed. The bit line structure 120 is formed to have a line shape extending in the first direction. The bit line structure 120 is electrically connected to the first impurity region by being connected to the first contact pad 110a through the bit line contact (not shown).

4A, 4B, and 11, a second interlayer insulating layer 122 is formed to completely bury the bit line structure 120. The second interlayer insulating layer 122 may be formed by depositing silicon oxide by chemical vapor deposition. Next, the capping layer pattern 118 is planarized to be exposed on the upper surface. The planarization process may be performed by a chemical mechanical polishing process. When the second interlayer insulating layer 122 is planarized to expose the capping layer pattern 118, the height of the second interlayer insulating layer 122 may be relatively accurate.

A line etch mask pattern 124 extending in the second direction is formed on the second interlayer insulating layer 122. The etching mask pattern 124 includes a photoresist pattern formed by a photo process. The etching mask pattern 124 is formed to selectively expose a portion where a storage node contact is not formed, that is, a portion corresponding to the storage node contacts.

Thereafter, the openings 126 are formed by partially etching the exposed second interlayer insulating layer 122 using the etching mask pattern 124. In the etching process, only the second interlayer insulating layer 122 defined by the etch mask pattern 124 and the bit line structure 120 is removed, so that the opening 126 extends in the second direction. It will have a bar shape.

Referring to FIG. 5, an etch blocking layer (not shown) is formed on the second interlayer insulating layer 122 while filling the inside of the opening 126. The etch blocking layer is provided to prevent the second interlayer insulating layer 122 from being excessively etched laterally when the second interlayer insulating layer 122 is partially etched to form an upper contact hole in a subsequent process. . Therefore, the etch blocking layer may be formed using a material that is hardly etched under the condition of etching the second interlayer insulating layer 122. Specifically, the etch blocking layer may be formed using silicon nitride.

Next, the etching blocking pattern 128 is formed inside the opening 126 by grinding the etching blocking layer to expose the top surface of the second interlayer insulating layer 122.

6A, 6B, and 12, after forming a hard mask film on the second interlayer insulating film 122, the hard mask provided as an etch mask for forming a storage node contact hole by patterning the hard mask film. The pattern 130 is formed. The hard mask pattern 130 has a line shape extending in the second direction.

The hard mask pattern 130 may be formed of a material which is hardly etched under the condition of etching the capping layer pattern 118 and the condition of etching the second interlayer insulating layer 122. Therefore, the hard mask pattern 130 is preferably formed of polysilicon.

Thereafter, the preliminary upper contact hole 132 is formed by partially anisotropically etching the second interlayer insulating layer 122 using the hard mask pattern 130. In this case, only the second interlayer insulating layer 122 defined by the bit line structure 120 and the hard mask pattern 130 is removed to have a shape of a contact hole. The preliminary upper contact hole 132 is formed to expose an upper portion of the capping layer pattern 118 of the bit line structure.

7A and 7B, the preliminary upper contact hole 132 is isotropically etched to form an upper contact hole 134 having a larger inner width than the preliminary upper contact hole 132. The isotropic etching includes a wet etching process.

The upper contact hole 134 formed through the isotropic etching process may have a shape in contact with the etch blocking pattern 128 in a first direction and in contact with a sidewall of the bit line structure 120 in the second direction. do. In this case, the conductive layer patterns 114 and 116 of the bit line structure 120 may not be exposed to the surface of the upper contact hole 134.

Since the etch blocking pattern 128 is formed, a problem such that adjacent upper contact holes 134 are connected to each other by excessive etching in the process of expanding the inside of the preliminary upper contact hole 132 is hardly generated. Do not. Therefore, the defects caused by the upper contact holes 134 are connected to each other is reduced.

8A and 8B, an insulating film for a spacer is formed along surface surfaces of the second interlayer insulating film 122, the hard mask pattern 130, and the bit line structure 120 on which the upper contact hole 134 is formed. Not shown). The spacer insulating layer may be formed of silicon nitride.

By anisotropically etching the spacer insulating film, a second spacer 136 is formed on the upper sidewall of the bit line structure 120. When forming the second spacer 136, an insulating film for the spacer remains on the surface portion of the upper contact hole 134 that is covered by the hard mask pattern 130.

9A and 9B, the upper contact hole is etched by etching the second interlayer insulating layer 122 exposed by the hard mask pattern 130 and subsequently etching the upper first interlayer insulating layer 112 anisotropically. A lower contact hole 138 is formed in communication with 134 and exposing an upper surface of the second contact pad 110b. The lower contact hole 138 has a narrower inner width than the upper contact hole 134.

The upper contact hole 134 and the lower contact hole 138 are provided to the storage node contact hole 140 to be connected to the storage electrode.

10A and 10B, a conductive material is embedded in the storage node contact hole 140, and the conductive material and the hard mask pattern 130 are polished to expose the top surface of the capping layer pattern 118. To form storage node contacts 142.

The storage node contacts 142 are provided between the bit line structures 120 having the second spacers 136 to electrically connect with the second contact pads 110b and have a shape wider than an upper portion thereof. The upper portion has a shape in contact with the etch blocking pattern 128 in the first direction and in contact with the second spacer 136 in the second direction.

Referring back to FIGS. 1A and 1B, cylindrical storage electrodes 144 contacting predetermined regions on the storage node contacts 142 are formed.

Briefly describing the method of forming the storage electrode, first, a BPSG, TEOS, or a mold film (not shown) formed thereon is formed on the second interlayer insulating layer 122 on which the storage node contacts 142 are formed. do. A predetermined region of the mold layer is etched to form an opening (not shown) that exposes an upper surface of the storage node contact. Next, a doped polysilicon film is deposited on the surface of the opening and the mold film surface, and a sacrificial film (not shown) is formed as a material such as USG to bury the opening in which the polysilicon film is deposited. Next, the polysilicon film formed on the mold film is removed to perform a chemical mechanical polishing process so that each node is separated. Next, the sacrificial film and the mold film are removed by an isotropic etching process to form the cylindrical storage electrode 144. However, since the upper surface of the storage node contact 142 connecting to the storage electrode 144 is widened, it is possible to minimize the limitation on the position of the storage electrode 144.

In this case, the storage electrode 144 may be formed on a position biased in one of the first directions with respect to the center of the upper surface of the storage node contact 142. Specifically, the entire storage electrodes 144 are arranged diagonally with each other, thereby increasing the distance between neighboring storage electrodes 144.

Next, although not shown, a dielectric film is deposited on the inner surface and the outer surface of the storage electrode 144. Subsequently, a plate electrode is formed on the dielectric layer.

As described above, according to the present invention,

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (5)

A first interlayer insulating layer provided on the substrate and including contact pads therein; Bit line structures extending in a first direction on the first interlayer insulating film; Insulating layer spacers partially surrounding both sidewalls of the bit line structures; Etch blocking patterns provided between the bit line structures and extending in a second direction perpendicular to the first direction; A second interlayer insulating layer covering the bit line structures; The insulating film spacers are formed between the bit line structures on which the insulating layer spacers are formed, and are electrically connected to the contact pads. Storage node contacts having a shape in contact with the insulating layer spacer; And And capacitors on upper surfaces of the storage node contacts. The semiconductor device of claim 1, wherein the etch blocking pattern is formed of silicon nitride. Forming a first interlayer insulating film on the substrate, the first interlayer insulating film including contact pads therein; Forming bit line structures extending in a first direction on the first interlayer insulating film; Forming a second interlayer insulating film covering the bit line and having a bar-shaped opening extending in a second direction perpendicular to the first direction; Forming etch blocking patterns by filling an etch blocking layer in the openings; An upper contact partially etching the second interlayer insulating layer between the bit line structures having the insulating layer spacer to contact the etch blocking pattern in the first direction and to contact the sidewall of the bit line structure in the second direction Forming a hole; Forming an insulating film spacer on an upper sidewall of the bit line structure exposed by the upper contact hole; Partially etching the second interlayer insulating layer and the first interlayer insulating layer positioned below the upper contact hole to form a lower contact hole having a smaller inner width than the upper contact hole and exposing an upper surface of the contact pad; Filling a conductive material in the upper contact hole and the lower contact hole to form a storage node contact having a shape in contact with the etch blocking pattern in the first direction and in contact with the insulating layer spacer in the second direction; And And forming capacitors on upper surfaces of the storage node contacts. The method of claim 3, wherein the etching blocking pattern is formed using silicon nitride. The method of claim 1, wherein the forming of the upper contact hole comprises: Forming a line-shaped mask pattern extending in the second direction on the second interlayer insulating layer, the bit line structure, and the etch blocking pattern; Anisotropically etching the bit line structure and the region defined by the mask pattern using the mask pattern as an etch mask to form a preliminary upper contact hole; And Isotropically etching the preliminary upper contact hole to form an upper contact hole exposing the etch blocking pattern.

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