KR100697891B1 - Method for driving a plasma diplay panel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel. In the present invention, waveforms of discharge erasing pulses input during a series of erasing periods are formed differently according to each subfield SF1, SF2, SF3 ... SF8. .

For example, in the present invention, the rising time or voltage width of the above-described discharge erasing pulse is gradually increased for each subfield so that the waveform of the discharge erasing pulse has a different shape for each subfield. In this case, the discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8 according to each subfield, for example. As a result, the longer the subfield between the sustain discharges, the larger the pulse for erasing the discharge. Will be input. As described above, when each discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8, the wall charges remaining in the individual display cells, although SF1 <SF2 <SF3 ... Even if the SF8 has been formed, after the erasing pulse of the present invention is input, the relationship of SF1 = SF2 = SF3 ... = SF8 is applied to each of the subfields SF1, SF2, SF3 ... SF8. Can be achieved.

As a result, when the present invention is achieved, the control circuit block can achieve stable image operation even when the same driving voltage is input. As a result, the effect of greatly improving the overall driving margin can be easily obtained.

Description

Method for driving a plasma diplay panel

1 is an exemplary view showing a plasma display panel to which the present invention is applied.

2 is an exemplary view conceptually showing a control circuit block of a plasma display panel to which the present invention is applied.

3 is a driving waveform diagram of a plasma display panel according to a first driving method of the present invention;

4 is a driving waveform diagram of a plasma display panel according to a second driving method of the present invention;

5 is a driving waveform diagram of a plasma display panel according to a third driving method of the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel (hereinafter referred to as " PDP "), and more particularly, after the sustain discharge period of each subfield SF1, SF2, SF3 ... SF8. Significantly improves the shape of the erase pulse input to the display device, thereby allowing the wall charges remaining in the individual display cells to achieve a relationship of, for example, SF1 = SF2 = SF3 ... It relates to a driving method of the PDP to improve the margin.

Recently, various problems regarding the function of the CRT (Cathod Ray Tube) have been raised, and various kinds of display apparatuses that can overcome the disadvantages of the CRT have been developed.

Among such various display devices, in particular, interest in PDP is increasing because PDP has an excellent advantage of displaying a large screen more clearly than conventional CRT.

PDP according to the prior art is, for example, US Patent No. 6078139 "Front panel for plasma display", US Patent No. 6075319 "Plasma display panel device and a method of manufacturing the same (Plasma display panel device) and method for fabricating the same ", US Patent No. 6069446" Plasma display panel with ring-shaped loop electrodes, US Patent No. 6066917 "Plasma display panel display panel, US Pat. No. 6034656, "Plasma display panel and method of controlling brightness of the same."

In addition, various driving methods of the PDP in this conventional technique are described, for example, in US Patent Publication No. 6054970 "Method for driving an AC-driven PDP, US Patent Publication No. 5952986" Driving method and display device (Driving method of an AC-type PDP and the display device).

Typically, such a conventional PDP is composed of a combination of front and rear base plates that are integrally sealed and coupled to each other while facing each other. In this case, a plurality of X and Y sustain electrodes are stripped on one surface of the front base plate. ) Are arranged to form a separate tip, and similarly, a plurality of address electrodes are arranged to form a separate tip of a stripe shape on one surface of the rear base plate.

The X and Y sustain electrodes and the address electrodes receive a predetermined voltage pulse from the control circuit block, thereby rapidly discharging the gas sealed between the front base plate and the rear base plate.

On the other hand, various researches for smoothly driving the conventional PDP have been actively conducted, so-called PDP driving, which is called an address-display separation method (hereinafter referred to as an "ADS" method). The method has been in the spotlight recently.

In the case of this ADS method, since the display period and the address period are strictly separated, when this method is actually applied to the driving of the PDP, the production line can obtain the advantage that the multi-gradation of 256 or more gradations can be driven at high speed. .

In general, in the conventional ADS scheme, a time for displaying and maintaining one image on the entire screen, that is, a frame is displayed in several sub-fields, for example, eight subfields SF1 and SF2. Each subfield SF1, SF2, SF3 ... SF8 is divided into a reset period, an address discharge period, a sustain discharge period, and an erase operation. It is run again by dividing into era period. In this case, the reset period, the address discharge period, the sustain discharge period, and the erase period are performed once for each subfield.

In this case, the control circuit block may measure the length of the above-mentioned sustain discharges according to each subfield SF1, SF2, SF3 ... SF8, for example, about 1: 2: 4: 8: 16: 32: 64: 128. By gradually increasing the ratio, the PDP can achieve 256 gray levels of color smoothly.

In general, when such a conventional sustain discharge period arrives, the control circuit block generates sustain discharge by alternately applying a sustain voltage for X · Y to a constant voltage to the X · Y sustain electrodes, and thereby, the address advanced above. The wall charges of the specific display cells selected by the discharge period can be maintained continuously.

However, as mentioned above, the control circuit block determines the length between the sustain discharges according to each subfield SF1, SF2, SF3 ... SF8, for example, 1: 2: 4: 8: 16: 32: 64: Since it is gradually increased and managed at a rate of about 128, after a series of erasing steps, the wall charges remaining in the individual display cells must be different for each subfield, and eventually, the wall charges remaining in the individual display cells are, for example, SF1 <SF2 <SF3 ... SF8. That is, the longer the subfield between the sustaining discharges, the greater the amount of wall charges remaining in the individual display cells.                         

As such, when the amount of wall charge remaining in the individual display cells is different for each subfield, the control circuit block consumes a small driving voltage, for example, in the case of the subfield SF8 in which the wall charge is sufficiently left in the individual display cells. In addition, the subsequent discharge periods can be smoothly progressed, but in the case of the subfield SF1 in which the wall charges do not sufficiently remain in the individual display cells, a large driving voltage must be consumed to advance the subsequent discharge periods. As a result, the control circuit block is forced to take the problem that the magnitude of the driving voltage varies depending on each subfield.

As described above, when the driving voltage difference of the control circuit block continuously exists for each subfield, a serious problem occurs that the overall driving margin of the PDP is greatly reduced.

The conventional control circuit block has a separate reset period, i.e., SF1 reset period, SF2 reset period, ... SF8 in all the initial positions of each subfield SF1, SF2, SF3 ... SF8 in order to overcome such a driving margin drop. By setting the reset period and inputting the SF1 write pulse / erase pulse, SF2 write pulse / erase pulse, ... SF8 write pulse / erase pulse, etc. during this reset period, the wall charges remaining in the individual display cells are, for example, SF1 = SF2 = SF3 ... = SF8. In this case, since the magnitudes of the driving voltages corresponding to the respective subfields are the same, the control circuit block can easily obtain the effect of greatly improving the overall driving margin.

However, in this way, in case of inputting SF1 recording pulses / erase pulses, SF2 recording pulses / erase pulses, ... SF8 recording pulses / erase pulses, etc. for each subfield SF1, SF2, SF3 ... SF8. In this case, the effect of improving the driving margin can be easily obtained, but in this case, in proportion to the input time of each pulse, the overall discharge time of the other discharge periods, for example, between the sustaining dischargers, is greatly reduced, so that the control circuit block can reduce the overall contrast of the PDP. There is no other problem than to drastically reduce rain.

Recently, in order to overcome such a further problem, without setting a separate reset period at every start of each subfield (SF1, SF2, SF3 ... SF8), only the first entry of the subfield located in the first step is made. A method of setting the reset period only to the negative has been proposed.

In this case, however, a series of contrast ratio improvement effects can be easily secured. However, only the wall charge relationship of the aforementioned SF1 = SF2 = SF3 .. = SF8 cannot be satisfactorily secured, resulting in a reduction in driving margin. This causes another problem.

Accordingly, an object of the present invention is to significantly improve the shape of the erase pulses input after the sustain discharge period of each subfield SF1, SF2, SF3 ... SF8, whereby the wall charges remaining in the individual display cells For example, in order to induce a relationship of SF1 = SF2 = SF3 ... = SF8.

Another object of the present invention is to equalize the magnitude of the driving voltage according to each subfield by allowing the wall charges remaining in the individual display cells to form a relationship of SF1 = SF2 = SF3 .... To improve driving margin.

It is still another object of the present invention to provide an apparatus according to unnecessary progress of the reset period by allowing the wall charges remaining in the individual display cells to achieve a relationship of, for example, SF1 = SF2 = SF3 ... ... SF8 without a separate reset period. This is to suppress the decrease in contrast ratio.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

In order to achieve the above object, in the present invention, a plurality of subfields (Sub- field: The subfields SF1, SF2, SF3 ... SF8 are divided into SF1, SF2, SF3 ... SF8, and address discharge period, sustain discharge period and erase Subdivided into erasing periods, the address discharge period, sustain discharge period, and erase period are repeated at regular cycles by application of an external power source, thereby selectively controlling the light emission state of each display cell. The method is disclosed.

In the present invention, when the above-mentioned sustain discharge period ends and the erase period arrives, the control circuit block inputs a series of discharge erase pulses to the Y sustain electrodes, thereby causing light emission by progressing between sustain discharge cells. The wall charges of the specific display cells which are maintained to be lowered to a value similar to the wall charges of the remaining display cells that do not emit light.

At this time, in the present invention, the above-described waveforms of the pulses for discharge erasing are formed differently according to the respective subfields SF1, SF2, SF3 ... SF8.                     

For example, in the present invention, the rising time or voltage width of the above-mentioned discharge erasing pulse is gradually increased in accordance with each subfield SF1, SF2, SF3 ... SF8, whereby The subfields SF1, SF2, SF3 ... SF8 have different shapes. In this case, the discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8 according to each subfield SF1, SF2, SF3 ... SF8, for example. In the field, a larger value for the discharge erase pulse is received.

As described above, when each discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8, the wall charges remaining in the individual display cells, although SF1 <SF2 <SF3 ... Even if the SF8 has been formed, after the erasing pulse of the present invention is input, the relationship of SF1 = SF2 = SF3 ... = SF8 is applied to each of the subfields SF1, SF2, SF3 ... SF8. Can be achieved.

As a result, when the present invention is achieved, the control circuit block can achieve stable image operation even when the same driving voltage is input. As a result, the effect of greatly improving the overall driving margin can be easily obtained.

Of course, in the case of the present invention, since a separate reset period does not proceed, when the present invention is achieved, the final shipped PDP can maintain a contrast ratio of a certain level or more.

Hereinafter, a driving method of the PDP according to the present invention will be described in detail with reference to the accompanying drawings.                     

As shown in FIG. 1, the PDP 50 for implementing the present invention, for example, an indirect discharge type PDP, consists of a combination of a front substrate unit 10 and a rear substrate unit 30 facing each other.

In this case, a series of seal lines (not shown) are formed outside the front substrate unit 10 and the rear substrate unit 30 to seal the front substrate unit 10 and the rear substrate unit 30 smoothly. Assist in maintaining state.

A discharge gas, for example, a penning mixed gas, is accommodated between the front substrate unit 10 and the rear substrate unit 30 sealed by the seal line. The phenning gas has a configuration in which argon (Ar), xenon (Xe), and the like are mixed with neon gas, and have a characteristic of easily discharging even at a low voltage.

At this time, as shown in the figure, the front substrate unit 10 is, for example, a pair of the front base plate 11 of the glass material, and the one side of the rear substrate unit 30 side of the front base plate 11, For example, the X-Y sustain electrodes 12 and 14 and the front dielectric layer 13 formed of an indium tin oxide (ITO) material are formed.

In this case, the X and Y sustain electrodes 12 and 14 are spaced apart from each other by a front end of the front base plate 11 facing the rear substrate unit 30 to form a continuous structure in parallel. The front dielectric layer 13 has a structure in which a front surface of the front base plate 11 is coated with a predetermined thickness so that the front X and Y sustain electrodes 12 and 14 are covered.

At this time, the X sustain electrodes 12 receive a sustain pulse from the control circuit block 100 and then use the sustain pulse to discharge discharge gas contained in the individual display cells 36 to be described later. It is responsible for maintaining the state continuously.

In addition, the Y sustain electrodes 14 receive scan pulses, sustain pulses, and the like from the control circuit block 100, and then use the scan pulses, the sustain pulses, and the like, and output image data to individual display cells 36. In addition to scanning and similarly to the aforementioned X sustaining electrodes 12, the display device serves to continuously maintain the discharge state of the discharge gas contained in the individual display cells 36.

At this time, a protective film layer (not shown), for example, an MgO layer is further disposed on the outermost surface of the front dielectric layer 13, and the protective film layer serves to improve the discharge characteristics of the front dielectric layer 13 described above.

Meanwhile, the rear board unit 30 corresponding to the front board unit 10 mentioned above is similar to the front board unit 10 of the front, for example, the rear base plate 31 made of glass, and the rear base plate. And a combination of the address electrodes 32 and the rear dielectric layer 33 formed on the upper side of the front base plate 11.

In this case, the address electrodes 32 are disposed on one surface of the rear base plate 31 facing the front base plate 11 in a state perpendicular to the arrangement direction of the X and Y sustain electrodes 12 and 14 described above. Spaced apart in a stripe shape, a parallel continuous array is formed, and the rear dielectric layer 33 forms a structure in which a thickness is applied to one surface of the rear base plate 31 so that the address electrodes 32 are covered.

In this case, the address electrodes 32 serve to selectively designate the individual display cells 36 to be subjected to the actual display discharge by receiving, for example, an address pulse from the control circuit block 100.

Here, a plurality of partition walls 34 are erected on one surface of the rear dielectric layer 33 and arranged in a line.

These barrier ribs 34 are formed of the front substrate unit 10 and the rear substrate unit 30, if the aforementioned front substrate unit 10 and rear substrate unit 30 are integrally sealed by seal lines. By partitioning the interface space therebetween to a certain size, the plurality of display cells 36 corresponding to the above-described X and Y sustain electrodes 12 and 14 between the front substrate unit 10 and the rear substrate unit 30. ) Are defined individually. In this case, the above-described discharge gas is accommodated in the individual display cells 36.

In this case, R, G, and B phosphors 35 are further coated inside the individual display cells 36 covering the inner surfaces of the partition walls 34, and the R, G, and B phosphors 35 are described above. When the discharge gas contained in each of the display cells 36 is discharged by driving one of the X and Y sustain electrodes 12 and 14 and the address electrodes 32, the ultraviolet rays of a predetermined size are emitted. By colliding with the ultraviolet rays, R, G, and B colors serve to induce light to be emitted toward the front substrate unit 10, for example.

Here, the R, G, and B phosphors 35 are continuously arranged in the color order of, for example, "RGB, RGB, ...." along the transverse direction of each of the individual display cells 36. When the B phosphor 35 emits ultraviolet rays by the above-described discharge process of the discharge gas, the B phosphor 35 collides with the ultraviolet rays so that the R, G, and B colors of light are discharged to the front substrate unit 10. ) Will emit light. The color arrangement of the R, G and B phosphors 35 may be variously modified according to the situation of the production line.

In this case, when the front dielectric layer 13 is discharged in each of the display cells 36 to generate a plurality of discharge ions, each of the X and Y sustain electrodes 12 and 14 is discharged. Similarly, the rear dielectric layer 33 discharges each of the display cells 36 to generate a plurality of discharge ions, and thus, each of the address electrodes 32 is discharged. Play a role in protecting them.

Meanwhile, as shown in FIG. 2, the aforementioned control circuit block 100 includes an address driver 101, an X common driver 103, a Y scan driver 102, a Y common driver 104, and a control unit ( 109).

Here, the address driver 101 is configured to input an address pulse to the address electrodes 32 while being electrically connected to the address electrodes 32. The X common driver 103 ) Serves to input a sustain pulse to the X sustain electrodes 12 while being electrically connected to the X sustain electrodes 12.

In addition, the Y scan driver 102 serves to input a scan pulse to the Y sustain electrodes 14 while the Y scan electrodes 102 are electrically connected to the Y sustain electrodes 14. 104 serves to input a sustain pulse to the Y sustain electrodes 14 while being electrically connected to the Y sustain electrodes 14 via the Y scan driver 102.

In the meantime, the control unit 109 is connected to the address driver 101, the X-Y common drivers 103 and 104, and the Y scan driver 102, and is connected to an external electric device such as a computer (not shown). The address driver 101, the X-Y common drivers 103 and 104, and the Y scan driver 102 are simultaneously controlled by a series of clock signals, display data signals, and horizontal and vertical signals input from the same.

In this case, the control unit 109 is dedicated to the display data control unit 105 which exclusively controls the address driver 101, the Y scan driver 102, the X common driver 103, and the Y common driver 104. It consists of a combination of the panel drive control unit 106 to control, in this case, the panel drive control unit 106 is a scan driver control unit 107 and X common driver 103, Y dedicated to control the Y scan driver 102 It consists of a combination of the common driver control unit 108 which exclusively controls the common driver 104.

On the other hand, as mentioned above, the PDP 50 of the present invention has a plurality of display cells at the intersections of the X and Y sustain electrodes 12 and 14 and the address electrodes 32 respectively formed in directions perpendicular to each other. (36) For example, in a state where the display cell 36a is provided, a series of electrical connections are formed with the above-described control circuit block, thereby quickly displaying a series of image information.

In this case, as shown in FIG. 3, the present invention divides the display cells 36 once and emits light, i.e., divides the frame into a plurality of subfields SF1, SF2, SF3 ... SF8. At the same time, each subfield SF1, SF2, SF3 ... SF8 is further divided into an address discharge period, a sustain discharge period and an erase period, and the address discharge period, the sustain discharge period and the erase period are repeated in a predetermined cycle. A process of selectively controlling the light emitting states of the display cells 36 is performed.

First, when the address discharge period S1 of the subfield SF1 arrives, the scan driver control unit 107 controls the Y scan driver 102 so as to correspond to the first line among the display lines of the PDP 50. The scan pulse P4 is applied to the Y sustain electrodes 14.

In addition, the display data control unit 105 controls the address driver 101 to display specific display cells 36, for example, that require sustain discharge, among all the address electrodes 32 located on the first line. The address pulse P5 is applied to the address electrodes 32 corresponding to the display cells 36a.

In this case, so-called address discharge occurs between the Y sustain electrodes 14 located on the first line and the specific address electrodes 32, and thus, display cells located on the first first line. The wall charges of a predetermined size are generated on the surfaces of the specific display cells 36a of 36.

The wall charge generation process is sequentially performed on all display lines in the order of the Y sustain electrodes 14 located on the second line and the Y sustain electrodes 14 located on the third line according to the linear sequential method. Proceed.

At this time, the common driver controller 108 controls the X common driver 103 to input the X sustain electrodes 12, for example, the shelf pulse P3, so that the X sustain electrodes 12 are electrically charged. To maintain a steady state

On the other hand, when the above-described series of wall charge formation processes proceed, the trace electrons in the discharge gas are rapidly accelerated, and these electrons strongly collide with the neutral particles included in the discharge gas, thereby causing each neutral particle to be separated from the electrons. Ionize with discharge ion.

At this time, the ionized electrons are accelerated once again by the previous electric field to participate in collision with the neutral particles, and as a result, the discharge gas contained in the selected specific display cells 36 changes into a plasma state. Done. As described above, when the discharge gas is converted into plasma, at the same time, a certain amount of ultraviolet rays are generated from the discharge gas, and the ultraviolet rays collide with the R, G, and B phosphors 35 applied inside the display cells 36. For example, light of R color can be quickly emitted to the display surface of the PDP 50.

Subsequently, when the sustain discharge period S2 of the subfield SF1 arrives, the common driver control unit 108 alternately controls the X common driver 103 and the Y common driver 104 so that the X sustain electrodes 12 and For example, the Y and Y sustain pulses P6 and P7 of positive potential having a size of about 180 V are alternately applied to the Y sustain electrodes 14.

In this case, so-called sustain discharge occurs whenever the voltage changes between the X sustain electrodes 12 and the Y sustain electrodes 14, and the R, G, and B phosphors 35 are prevented by the ultraviolet rays generated at this time. It is possible to keep the light emitting state of.

Subsequently, when the series of sustain discharge periods S2 expire and the erasing period S3 of the subfield SF1 arrives, the common driver control unit 108 controls the Y common driver 103 so that the Y sustain electrodes ( 14), the process of applying the discharge erasing pulse P8 is performed.

In this case, so-called erasing discharge occurs in the specific display cells 36a during the sustain discharge, and thus, the charges that are attached to the inner wall of the specific display cells 36a during the sustain discharge are transferred to the corresponding display cells 36a. And the wall discharge of the specific display cells 36a during the sustain discharge is similar to the wall charge of the other display cells 36 without the sustain discharge. By lowering it to a value, thereafter, a condition in which address discharge S1 of another subfield that proceeds can proceed more stably is provided.

Thereafter, the control circuit block 100 sets the aforementioned address discharge period S1, sustain discharge period S2, and erase period S3 in predetermined cycles according to the respective subfields SF1, SF2, SF3 ... SF8. By repeating, the light emission state of each display cell 36 is selectively adjusted, and thus, the image information display operation of the PDP 50 can be smoothly performed.

At this time, as shown in the figure, in the present invention, the waveform of the above-mentioned discharge erasing pulse P8 is formed differently in accordance with each subfield SF1, SF2, SF3 ... SF8.

As an example of such a waveform deformation, in the present invention, the rising times A1, A2, and A3 of the discharge erasing pulses P8, P9, and P10 are different, so that the rising times A1, A2, and A3 of these pulses are the subfields SF1, SF2, Gradually increase according to SF3 ... SF8).

In this case, the discharge erasing pulses P8, P9, and P10 gradually increase in electrical magnitude, so that, for example, the relationship of SF1 < SF2 < SF2 &lt; SF3 &gt; SF8 in accordance with each subfield SF1, SF2, SF3 ... SF8 As a result, the longer the subfield of the sustain discharge period (S2), the larger the value of the discharge erase pulse is received.

In this way, the subfield with a long length of the sustain discharge period S2 receives a discharge erase pulse of a larger value, and each discharge erase pulse P8, P9, P10 is associated with SF1 <SF2 <SF3 ... SF8. In this case, the wall charges remaining in the individual display cells 36 are erased according to the present invention, even though they have formed a relationship of SF1 <SF2 <SF3 ... SF8 by the progress of the sustain discharge period S2. After the pulses P8, P9, and P10 are input, a relationship of SF1 = SF2 = SF3 ... = SF8 can be formed for each subfield SF1, SF2, SF3 ... SF8.

In other words, when the discharge erasing pulses P8, P9, and P10 of the present invention are input, the wall charges remaining in the individual display cells 36 are different for each subfield irrespective of the sustain discharge period S2 that has been previously performed. And SF1 = SF2 = SF3 ... = SF8, so that the control circuit block 100 can input the same driving voltage to each of the subfields SF1, SF2, SF3 ... SF8. In addition, stable image operation can be achieved, and in the end, when the present invention is achieved, the control circuit block 100 can easily obtain the effect of greatly improving the overall driving margin.

Of course, in the case of the present invention, since a separate reset period does not proceed, when the present invention is achieved, the final shipped PDP 50 can maintain a contrast ratio or more.

On the other hand, as shown in Figure 4, in another embodiment of the present invention by varying the voltage widths H1, H2, H3 of the discharge erasing pulses P11, P12, P13, each of the voltage widths H1, H2, H3 It gradually increases with the subfields SF1, SF2, SF3 ... SF8.

Also in this case, the discharge erase pulses P11, P12, and P13 gradually increase in electrical magnitude, and thus, for example, SF1 <SF2 <SF3 ... SF8 in accordance with each subfield SF1, SF2, SF3 ... SF8. As a result, the longer the subfield of the sustain discharge period S2, the larger the value of the discharge erase pulse is received.

As described above, when another embodiment of the present invention proceeds and each discharge erasing pulse P11, P12, P13 forms a relationship of SF1 < SF2 < SF3 &gt; SF8, like the above-described embodiment, the individual display cells 36 The remaining wall charges in the above) are obtained by inputting the erasing pulses P11, P12, and P13 of the present invention, even though the relationship between SF1 < SF2 &lt; Subsequently, for each subfield, for example, SF1 = SF2 = SF3 ... = SF8 can be formed, and in this case, the control circuit block 100 also controls each subfield (SF1, SF2, SF3 ... SF8). With respect to, even when the same driving voltage is input, stable image operation can be achieved, and as a result, the effect of greatly improving the overall driving margin can be easily obtained.

On the other hand, as shown in Fig. 5, in another embodiment of the present invention, the rising times A1, A2, A3 and the voltage widths H1, H2, H3 of the discharge erasing pulses P14, P15, P16 are different at once. The rising times A1, A2, A3 and the voltage widths H1, H2, H3 of the pulses are gradually increased with each subfield SF1, SF2, SF3 ... SF8.

Also in this case, the discharge erase pulses P14, P15, and P16 are gradually increased in electrical magnitude, and accordingly, for example, in accordance with each subfield SF1, SF2, SF3 ... SF8, SF1 <SF2 <SF3 ... SF8 As a result, the longer the subfield of the sustain discharge period S2, the larger the value of the discharge erase pulse is received.

As described above, when another embodiment of the present invention proceeds and each discharge erasing pulse P14, P15, P16 forms a relationship of SF1 < SF2 < SF3 ... SF8, like the above-described embodiments, the individual display cells The wall charges remaining at (36) are inputted by the erasing pulses P14, P15, and P16 of the present invention, even though the relationship between SF1 < SF2 < SF3 &gt; SF8 is formed by the progress of the sustain discharge period (S2). After this, for example, SF1 = SF2 = SF3 ... = SF8 can be formed for each subfield, and in this case, the control circuit block 100 also controls each subfield (SF1, SF2, SF3 ...). With respect to SF8), even when the same driving voltage is input, stable image operation can be achieved, and as a result, the effect of greatly improving the overall driving margin can be easily obtained.

As described above, in the present invention, the shape of the erase pulse inputted after the sustain discharge period of each subfield SF1, SF2, SF3 ... SF8 is greatly improved, whereby the wall remaining in the individual display cells is improved. By making the amount of charges, for example, SF1 = SF2 = SF3 ... = SF8, the magnitude of the driving voltage corresponding to each subfield can be equalized, and the overall driving margin of the finally shipped PDP device can be improved.

This invention shows the overall useful effect in the various types of PDP produced in the production line.

And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

As described in detail above, in the driving method of the PDP according to the present invention, the waveform of the discharge erasing pulse inputted during the series of erasing periods is formed differently according to each subfield SF1, SF2, SF3 ... SF8. .

For example, in the present invention, the rising time or voltage width of the above-described discharge erasing pulse is gradually increased for each subfield so that the waveform of the discharge erasing pulse has a different shape for each subfield. In this case, the discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8 according to each subfield, for example. As a result, the longer the subfield between the sustain discharges, the larger the pulse for erasing the discharge. Will be input.

As described above, when each discharge erasing pulse has a relationship of SF1 <SF2 <SF3 ... SF8, the wall charges remaining in the individual display cells, although SF1 <SF2 <SF3 ... Even if the SF8 has been formed, after the erasing pulse of the present invention is input, the relationship of SF1 = SF2 = SF3 ... = SF8 is applied to each of the subfields SF1, SF2, SF3 ... SF8. Can be achieved.

As a result, when the present invention is achieved, the control circuit block can achieve stable image operation even when the same driving voltage is input. As a result, the effect of greatly improving the overall driving margin can be easily obtained.

Claims (7)

In the state where a plurality of display cells are formed at the intersections of the X and Y sustain electrodes and the address electrodes respectively formed in directions perpendicular to each other, a time for emitting and maintaining the display cells once is provided in a number of sub-fields And subdividing each subfield into an address discharge period, a sustain discharge period, and an erase period, and the address discharge period, sustain discharge period, and the like. Repeating an erase period in a predetermined cycle to selectively control the light emission state of the display cells; When the address discharge period arrives, a plurality of scan pulses are sequentially input to the Y sustain electrodes according to a series of line sequential methods, and at a time similar to the input time of the scan pulses, Inputting a plurality of address pulses to address electrodes to selectively emit only specific display cells among the display cells, When the sustain discharge period arrives, a plurality of X and Y sustain pulses are alternately input to the X sustain electrodes and the Y sustain electrodes to maintain the light emission state of the specific display cells that are emitting light. Proceeding, When the erasing period arrives, a step of lowering the wall charges of the specific display cells that are emitting light to a value similar to the wall charges of the remaining display cells that do not emit light by inputting a discharge erase pulse to the Y sustain electrodes. Proceed, And the waveform of the discharge erasing pulse is formed differently according to the respective subfields. The method of claim 1, wherein the discharge erasing pulse has a rising time different according to each subfield. The method of claim 2, wherein the discharge erasing pulse gradually increases in rising time according to each of the subfields. The method of claim 1, wherein the voltage of the discharge erasing pulse varies according to the subfields. The method of driving a plasma display panel of claim 4, wherein a voltage width of the discharge erasing pulse gradually increases with each subfield. The method of claim 1, wherein the discharge erasing pulses have different rising times and voltage widths according to each of the subfields. 7. The method of driving a plasma display panel according to claim 6, wherein the discharge erasing pulse gradually increases at a time in response to each of the subfields.

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