KR100697772B1 - Optical disc device - Google Patents

Abstract

In the HD-DVD, the detection accuracy of the address information is improved. At the time of recording and reproducing the data on the HD-DVD optical disc 10, the address decoding circuit 28 demodulates the address information and supplies it to the system controller 32. FIG. The system controller 32 performs an error check with the CRC. When the CRCs do not match, the system controller 32 considers the bits other than four of the number of the common wave of the wobble as the error bits, and replaces the bits. Search for and correct errors.

HD-DVD Optical Disc, System Controller, Wobble

Description

Optical Disc Device {OPTICAL DISC DEVICE}

1 is an overall configuration diagram of an embodiment,

2 is a configuration diagram of an address decode circuit of an embodiment;

3 is a timing chart of a wobble signal,

4 is an error bit specifying processing flowchart of the embodiment;

5 is an error correction processing flowchart of the embodiment;

6 is a detailed processing flowchart of error correction;

7 is another processing flowchart of error correction.

※ Explanation of symbols about main part of drawing ※

10: optical disc (HD-DVD) 28: address decode circuit

32: system controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disc apparatus, and more particularly, to a high density optical disc apparatus for recording / reproducing data by using grooves.

Recently, HD (Hi-Definition) -DVD has been proposed as a next-generation DVD. In HD-DVD, following the disk structure of the current DVD, the compatibility with the DVD is ensured, and the density of the DVD is higher than that of the DVD.

One characteristic of the HD-DVD is that it adopts a land groove recording method for recording information in both land and groove. The land track and groove track are wobbled and address information is stored in this wobble. Specifically, the address information is expressed using four bits of zero degrees phase with bit "0" and four waves of 180 degrees phase with bit "1" using phase modulation. Placing four and plural waves in the same phase aims to improve the accuracy of address information detection due to redundancy. The address information is stored in the wobble after converting the binary data into a gray code. Here, the gray code is a code in which the inter-signal distance between adjacent binary data, that is, the number of inversion bits is set to one. Accordingly, the address "0" is "00000000", the address "1" is "00000001", the address "2" is "00000011", the address "3" is "00000010", the address "4" is "00000110", etc. Is expressed.

On the other hand, it is also possible to wobble the groove to store address information, and to record or reproduce data only in the groove. In this case, since it is not necessary to give address information to the land, it is not necessary to convert the address information into gray code and store it. It is also possible to add a check bit for a CRC (cyclic redundancy check) to the groove address information. Even when data is recorded only in the groove, address information is expressed using four bits of zero degree phase with bit "0" and four waves of 180 degree phase with bit "1" using phase modulation. As in the case of an optical disc for recording data in grooves and lands, one bit of four in-phase pars is expressed so that both optical discs can be driven by one optical disc device. When an optical disc that records data only in a groove is set to "HD DVD-R" (Light Once), and an optical disc which records data in a groove and land is set as "HD DVD-RW" (Rewritable), either R or RW It can also drive things.

[Patent document 1] "Nikei Electronics October 13 issue" Nikkei BP company, October 13, 2003 issuance, p126-134

In this way, the address information is expressed using four phase waves of zero degree phase and four bit waves of 180 degree phase using bit modulation "1" using phase modulation. Or "1" can be determined. That is, when only three waves of 0 degree phase and only one wave of 180 degree phase are detected, this can be determined as "0". However, even if there are three waves of zero degree phase, since it cannot be guaranteed whether it is "0", it is preferable if the detection accuracy can be improved more. In addition, when two waves of 0 degree phase and two waves of 180 degree phase are detected in half and respectively, it cannot be determined which data. Of course, it is possible to determine whether or not it is a read error by performing a CRC using the CRC check bit, but for example, even if a 9-bit check bit is added, an error of less than 3 bits can be detected. Because it stays there, it is not possible to correct the error and determine the correct address.

SUMMARY OF THE INVENTION An object of the present invention is to improve the detection (or demodulation) accuracy of address information for an optical disc that stores address information by expressing data "0" and "1" with four waves of the same phase using phase modulation. Is in providing.

The present invention provides an optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc in which address information is stored, wherein the wobble comprises one bit data of the same number of phases in the same phase. If a check bit for a predetermined CRC is added and the CRC result of the address information obtained by reproducing the wobble does not match, a bit having N / 2 waves of the same phase of the wobble is determined as a read error bit, and the CRC And address determination means for substituting the bit data to coincide with the check bit.

In addition, the present invention provides an optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc in which address information is stored, wherein the wobble comprises one bit data of the same number of phases in the same phase. When a check bit for a predetermined CRC is added and the CRC result of the address information obtained by reproducing the wobble does not match, the bit having the same phase wave of the wobble is N-1 or less is determined as a read error bit, and the CRC And address determination means for substituting the bit data so as to coincide with the check bit.

In addition, the present invention provides an optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc in which address information is stored, wherein the wobble comprises one bit data of the same number of phases in the same phase. If a check bit for a predetermined CRC is added and the CRC result of the address information obtained by reproducing the wobble does not match, the bit having the same phase wave of the wobble of N / 2 is determined as a read error bit. If the bit data is replaced to match the check bit for CRC, and even if the replacement does not match the check bit for CRC, the bit having the same phase wave of the wobble of N-1 or less is determined as a read error bit. And address determination means for replacing the bit data so as to match the check bit for the CRC.

In the present invention, when the CRC results do not coincide with each other, the number of in-phase waves of the wobble is taken into consideration. An error occurs in this bit and the CRC result is considered to be inconsistent, and error correction is performed by replacing this bit with an error bit.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing.

In Fig. 1, an overall configuration diagram of the optical disk device according to the present embodiment is shown. The optical disc 10 is rotationally driven by the spindle motor (SPM) 12. The spindle motor SPM 12 is driven by the driver 14, and the driver 14 is servo controlled by the servo processor 30 to achieve a desired rotational speed. In this embodiment, as an example, the driver 14 is divided into a plurality of zones between the inner circumference and the outer circumference of the optical disk 10, and is driven so as to have a constant linear velocity ZCLV in each zone. One example of the optical disc 10 is HD DVD-R.

The optical pickup 16 includes a laser diode LD for irradiating a laser light to the optical disk 10 or a photodector PD for receiving reflected light from the optical disk 10 and converting the light into an electrical signal. 10) is arranged opposite. The optical pickup 16 is driven in the radial direction of the optical disc 10 by the thread motor 18, and the thread motor 18 is driven by the driver 20. The driver 20 is servo controlled by the servo processor 30 similarly to the driver 14. The LD of the optical pickup 16 is driven by the driver 22, and the driver 22 is controlled by the auto power control circuit (APC) 24 so that the drive current becomes a desired value. The APC 24 controls the drive current of the driver 22 to be the optimum recording power selected by the OPC (Optimum Power Control) executed in the test area PCA of the optical disc 10. OPC is a process of recording test data by changing the recording power in multiple stages to the PCA of the optical disc 10, reproducing the test data to evaluate the signal quality, and selecting the recording power at which the desired signal quality is obtained. For signal quality, β values, γ values, modulation degrees, jitter, and the like are used.

When the data recorded on the optical disc 10 is reproduced, laser light of reproduction power is irradiated from the LD of the optical pickup 16, and the reflected light is converted into an electric signal by the PD and output. The reproduction signal from the optical pickup 16 is supplied to the RF circuit 26. The RF circuit 26 generates a focus error signal or tracking error signal from the reproduction signal and supplies it to the servo processor 30. The servo processor 30 servo-controls the optical pickup 16 based on these error signals, and maintains the optical pickup 16 in the on-focus state and the on-track state.

The optical pickup 16 records / reproduces the groove of the optical disc 10. The optical disc 10 has a groove formed in a spiral shape. The RF circuit 26 also supplies the address signal included in the reproduction signal to the address decode circuit 28. The address decode circuit 28 demodulates the address data of the optical disc 10 from the address signal and supplies it to the servo processor 30 or the system controller 32. The address data is stored as a wobble in the groove of the optical disc 10. The optical disc 10 includes segment addresses and track addresses as address data. The address data is phase-modulated and expresses the bit value "0" with four waves of 0 degree phase and the bit value "1" with four waves of 180 degree phase. The waves of these four statues make up the redundant system.

The RF circuit 26 supplies the reproduced RF signal to the binarization circuit 34. The binarization circuit 34 binarizes the reproduction signal and supplies the obtained signal to the encode / decode circuit 36. The encode / decode circuit 36 demodulates and error corrects the binarized signal to obtain reproduction data, and outputs the reproduction data to a host device such as a PC through the interface I / F 40. When the reproduction data is output to the host device, the encode / decode circuit 36 stores the reproduction data in the buffer memory 38 once and then outputs the reproduction data.

When recording data on the optical disc 10, data to be recorded from the host device is supplied to the encode / decode circuit 36 via the interface I / 40. The encode / decode circuit 36 stores the data to be written in the buffer memory 38, encodes the data to be written, and writes the data as modulation data (Eight to Twelve Modulation). To a write strategy 42. The write strategy circuit 42 converts the modulated data into multi-pulse (pulse strain) in accordance with a predetermined write strategy, and supplies it to the driver 22 as write data. The write strategy is composed of, for example, the pulse width of the leading pulse, the pulse width of the subsequent pulse, and the pulse duty in the multipulse. Since write strategy affects the recording quality, it is usually fixed at some optimum strategy. You may also arrange recording strategy at 0 PC. The laser light power-modulated by the recording data is irradiated from the LD of the optical pickup 16 and data is recorded on the optical disc 10. After recording the data, the optical pickup 16 irradiates the reproducing power laser beam to reproduce this recording data and supplies it to the RF circuit 26. The RF circuit 26 supplies a reproduction signal to the binarization circuit 34 and the binarized data is supplied to the encode / decode circuit 36. The encode / decode circuit 36 decodes the modulated data and checks it against the write data stored in the buffer memory 38. The result of the verification is supplied to the system controller 32. The system controller 32 determines whether to continue to record data or to execute the replacement process according to the result of Verify.

In such a configuration, in order to record / reproduce data in the groove, the groove track is traced and the address is decoded by the address decoding circuit 28 and supplied to the system controller 32. The in-phase wave can be detected, and in this case, the bit value can be determined as "0" or "1" depending on the phase. However, when only three in-phase waves are detected or only two in-phase waves are detected, there is a fear of a read error of address information. In the former case (three in-phase waves), the bit value can be determined as the phase by the majority vote principle, but the reliability thereof is relatively low. In the latter case (two in-phase waves), the bit value cannot be determined by the majority vote principle. In either case, it is read as either 0 or 1 to determine whether it matches the check bit for CRC, and if it does not match, the read address information is an error. CRC is a well-known technique. The data to be inspected is regarded as binary data, processed into a calculation formula called a generation polynomial, and a check bit of a certain number of bits is generated and added to the data to be inspected. On the demodulation side, the presence or absence of an error is determined by reproducing the data to be inspected and processing the generated polynomial to determine whether or not the data match the bit for inspection. The parity bit is a 1-bit CRC check bit and can detect an error of 1 bit. If the CRC check bit is set to 9 bits, an error of less than 3 bits can be detected. However, since it is unclear which bit is causing the error, the error cannot be corrected. In particular, when the address information is composed of 12 bits, it is not practical to search for all possible combinations of these 12 bits.

Thus, in the present embodiment, when it is determined that a read error has occurred because the result of the CRC of the read address information does not coincide with the check bit for the CRC, it is detected at which bit position of the address information an error has occurred. Therefore, error correction is possible. The bit position where an error has occurred is determined by whether there are four in-phase waves. In other words, if there are four in-phase waves, it is determined that they have been read correctly. If there are not four in-phase waves, it is determined that an error has occurred at this bit position.

2 shows a counting circuit for counting the number of in-phase waves in the address decode circuit 28. 3, the timing chart in each part of FIG. 2 is shown. The counting circuit includes a binarizer 28a, an exclusive OR gate 28b, and a counter 28c for binarizing the wobble signal extracted from the RF signal.

The binarizer 28a binarizes and inputs the input wobble signal. An input wobble signal is shown in FIG. 3 (a), and a binarized wobble signal is shown in FIG. 3 (b). The binarized wobble signal is supplied to the EOR gate 28b. On the other hand, the reference clock signal from the PLL circuit (not shown) is also supplied to the EOR gate 28b. 3 (c) shows a reference clock signal.

The EOR gate 28b calculates an exclusive theoretical sum of the binarized wobble signal and the reference clock signal and outputs it to the counter 28c. An output signal is shown in Fig. 3D. When both the binarized wobble signal and the reference clock signal are H or L, the output signal becomes L, and when one of the binarized wobble signal and the reference clock signal is H and the other is L, the output signal becomes H. Therefore, when the wobble is normally read in the period Ta (one bit data length of address information) in FIG. 3, four pulses of H are present in the binarized wobble signal, which is always the same as the reference clock signal. Therefore, the output signal is always L, and in the counter 28c, the number of pulses is 0, that is, the number of in-phase waves of 0 degrees is detected as four. Also, when the wobble is read normally even in the period Tb in FIG. 3, since the four pulses of L are present in the binarized wobble signal, the output signal is always H since the counter is always the same value as the reference clock signal. In 28c, the number of pulses is 0, that is, the number of waves in phase of 180 degrees is detected as four. By the way, when an error occurs while reading the wobble in the period Tc in FIG. 3 and the second wave 110 of the four waves cannot be detected, only three pulses of H are included in the binarized wobble signal. Since the value is different in this part from the reference clock signal, the output signal includes one pulse 200. Therefore, in the counter 28c, the number of pulses is detected as one, that is, the number of waves in phase of zero degrees is three. In this manner, the number of in-phase waves is counted and supplied to the system controller 32.

4, the address information decoding processing flowchart of this embodiment is shown. First, the counter 28c counts the number C of waves of phase 0 degrees (S101). Next, the system controller 32 determines whether C = 0 or 4, that is, whether the number of waves is zero or four (S10). If the number of waves is four, the bit value can be determined as "0". If the number of waves is zero (that is, the number of waves at 180 degrees is four), the bit value can be determined as "1". Therefore, no read error occurs.

On the other hand, when C = 0 or 4, that is, when C = 1, 2 or 3, the system controller 32 sets an error flag to this bit (S103). The bit in which the error flag is set is specified as the bit to be error corrected.

5, a flowchart of the CRC in the system controller 32 is shown. The address information reproduced by the address decode circuit 28 is input (S201). At this time, since the processing shown in Fig. 4 is also executed in parallel, the presence or absence of an error flag is also input together with the address information. For example, in the case of 12-bit address information, the address information is "000000000111", and an error flag is set in the 2nd and 3rd bits. Next, the system controller 32 considers the input address information as binary data, processes it using a generation polynomial, generates a CRC value, and determines whether or not it matches the check bit for the CRC previously added (S202). ). If the CRC coincides with OK, i.e., the check bit for the CRC, the address is determined as if the read was successful. On the other hand, if the CRC does not match the NG, that is, the CRC check bit, the system controller 32 corrects the error by replacing the bit position specified in the error flag (S203).

6 shows a detailed processing flowchart of S203 in FIG. First, the system controller 32 determines whether there are a plurality of bits (error bits) in which an error flag is set (S301). If there is only one error bit, error correction is completed by replacing the error bit with 0 or 1 (S302). On the other hand, when there are a plurality of error bits, the error bits are replaced to determine whether they match the check bits for the CRC, and when they do not match, the process of performing CRC by replacing the error bits again is repeated (S303, S304). The above iterative process is performed for all combinations of error bits possible. For example, if there are two error bits, all combinations of (0, 0), (0, 1), (1, 0), and (1, 1) are processed by the generation polynomial and the check bits for CRC Determine if it matches. Of these combinations, the combinations (phenomena combinations) inputted to the address decode circuit 28 are already performed in the CRC, and thus need not be performed again. Therefore, in the case of two error bits, it is sufficient to execute the CRC by executing the CRC for the remaining three combinations. Similarly, when the error bit is 3 bits, it is sufficient to execute the CRC for the remaining seven types of combinations. If the CRC is executed by substituting the error bits, and a combination is found in which the CRC is OK, the combination is correct address information and error correction is terminated (S305). Here, in the process of S303, when replacing the error bit, the error bit may not be executed for all possible combinations, but may be executed first (priority) for the combination that seems most certain. The most certain combination is a combination that becomes an address that is advanced one address from the address immediately before the address is completed, provided that the addresses are continuous. Among the possible combinations, a combination which becomes an address being advanced by one address from the immediately preceding address is first executed, and it is processed by the generation polynomial to determine whether or not it matches the check bit for CRC. If this process coincides, there is no need to execute another combination, and the correction process is high speed. If a combination that has been advanced one address from the previous address does not match the CRC check bit, another combination is executed.

As described above, in the present embodiment, the CRC is performed using the CRC check bit added to the address information. When the CRC is NG, an error occurs in a bit other than 0 or 4 in-phase waves. By specifying the error bit position and replacing the error bit with error correction, it is possible to reliably correct the error within the range of the error detection capability of the CRC to obtain correct address information.

In the present embodiment, CRC is performed at the same time as counting the number C of the in-phase wave, and if the number C of the in-phase wave is substituted for bits other than four when the result of the CRC is inconsistent, the result of the CRC is inconsistent. In this case, after that, the number of in-phase waves in this address information may be counted, and the number of in-phase waves may be substituted for four bits.

In addition, in the present embodiment, a bit other than the number of in-phase waves is regarded as an error bit. However, only two bits may be regarded as an error bit. In other words, when the number of in-phase waves is one or three, the bit values are determined by the majority vote principle. However, since they have a certain degree of reliability, they are treated as non-error bits. If there are no combinations that match the CRC even if the number of in-phase waves is regarded as two error bits and there is no matching CRC, then the processing algorithm that considers the number of in-phase waves as one or three bits as error bits and replaces them You may use.

7 shows a processing flowchart in this case. First, after reproducing and inputting address information, the system controller 32 determines whether or not the CRC value (value processed by the generated polynomial) of the address information matches the CRC check bit (S402). If the CRC does not match and is determined to be NG, it is determined whether the number C of the in-phase wave replaces two bits to match the CRC (S403, S404). When there are a plurality of bits of C = 2, all possible combinations are substituted and it is determined whether the CRCs coincide. As described above, a combination may be performed first (priority) from an address which has been advanced only once from the immediately preceding address, and it may be determined whether the CRCs coincide. If the CRCs match, the address information is determined by the combination (S408). On the other hand, if all the combinations of C = 2 bits do not match the CRC, then the bits of C = 1, 2, 3 are regarded as error bits and replaced (S405). Then, it is again determined whether the CRCs match (S406). If the CRCs match, the address information is determined by the combination (S408). If the CRCs do not match even if all the combinations are performed, it is finally determined as an error (S407). In this way, the error correction time can be shortened by first replacing only bits of C = 2 and then replacing bits of C = 1, 2, and 3.

In addition, if the CRC is NG and there are four or more bits (more than the CRC's detection capability) in the bit information, there are two phase zero degrees waves (two phase 180 degrees waves). It may determine and process as NG as it is.

In the present invention, when the CRC results do not coincide, the number of in-phase waves of the wobble is taken into consideration, and if this is N of the specified values, it is normal, and other than the prescribed values, that is, N / 2 or N-1 An error occurs in this bit and the CRC result is considered to be inconsistent, and error correction is performed by replacing this bit as an error bit.

Claims (5)

An optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc apparatus in which address information is stored, The wobble comprises one bit data with N waves in the same phase, A predetermined CRC check bit is added to the address information. When the CRC result of the address information obtained by reproducing the wobble does not match, the bit having the same phase wave of the wobble is N / 2 is determined as a read error bit, and the bit data is replaced to match the check bit for the CRC. And an address determination means. An optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc in which address information is stored, The wobble consists of one bit data with N waves in the same phase, A predetermined check bit for CRC is added to the address information. If the CRC result of the address information obtained by reproducing the wobble does not match, it is determined that a bit having N-1 or less waves of the same phase of the wobble is a read error bit and replaces bit data to match the check bit for the CRC. And an address determination means. An optical disc apparatus which wobbles a groove and records or reproduces data in a groove of an optical disc in which address information is stored, The wobble comprises one bit data with N waves in the same phase, A predetermined CRC check bit is added to the address information. If the CRC result of the address information obtained by reproducing the wobble does not match, the bit having the same phase wave of the wobble is N / 2 is determined as a read error bit, and the bit data is replaced to match the check bit for the CRC. If the replacement does not match the check bit for the CRC, a bit having N-1 or less waves in the same phase of the wobble is determined as a read error bit, and the bit data is replaced to match the check bit for the CRC. And an address determination means. The method according to any one of claims 1 to 3, And the address determining means selects and replaces a combination corresponding to the CRC check bit within a possible combination of bit values when there are a plurality of bits determined as the read error bits. The method according to any one of claims 1 to 3, The address determining means, when there are a plurality of bits determined as the read error bits, selects a combination that becomes an address that has been advanced only once from the previous address already determined within a possible combination of bit values, and selects the combination into the check bit for the CRC. It is determined whether or not there is a match, and when a match is made, the optical disk device is replaced with a combination thereof.

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