KR100670618B1 - Sequential sputter and reactive precleans of vias and contacts - Google Patents

Abstract

The present invention generally provides a method for improving the electrical performance and fill of a metal deposited on a patterned dielectric layer. Openings such as vias and trenches in the patterned dielectric layer are etched to enhance filling and are then cleaned in the same chamber to reduce metal oxides in the openings. The invention also consists in argon and cleans the patterned dielectric layer in the processing chamber with a first plasma generated by providing power to a coil surrounding the processing chamber and biasing the substrate support member supporting the substrate. Step, patterned in the processing chamber with a second plasma, consisting essentially of hydrogen and helium, produced by increasing power delivery to the coil surrounding the processing chamber and reducing bias provision to the substrate support member supporting the substrate. Cleaning the dielectric layer, exposing the dielectric layer to the first and second plasmas, and then depositing a barrier layer on the patterned dielectric layer, and depositing a metal on the barrier layer. In addition, sequential plasma processing may be performed in various plasma processing chambers of an integrated process sequence, including pre-clean chambers, physical vapor deposition chambers, etch chambers, and other plasma processing chambers.

Description

Sequential sputtering and reactive precleaning of vias and contacts {SEQUENTIAL SPUTTER AND REACTIVE PRECLEANS OF VIAS AND CONTACTS}

1 is a randomly oriented, fine-grained, granular deposition layer in a contact hole of a substrate having voids, discontinuities, and non-planar surfaces. A schematic partial cross-sectional view of a patterned substrate showing a.

2 is a schematic diagram of a cluster tool system with a multi-substrate processing chamber.

3 is a flow chart illustrating the sequential argon plasma cleaning and hydrogen plasma cleaning steps of the present invention, along with other process sequence steps occurring before and after the argon and hydrogen plasma steps.

4 is a cross-sectional view of a typical PVD chamber useful for depositing a barrier layer.

5 is a cross-sectional view of an exemplary preclean chamber useful in the present invention.

* Explanation of Codes on Major Parts of Drawings *

100: cluster tool system 105, 110: load lock chamber

125, 130, 150, 155, 160, 165: substrate processing chamber

310: PVD chamber 314: substrate support member                 

316: target 320: clamp ring

326: magnet assembly 328: RF plasma power source

In integrated circuits, low dielectric constant films have become of significant importance as structures become smaller in size and multilevel metallization is becoming more common. Low dielectric constant films are particularly desirable for reducing the RC time delay of the wire metallization being covered, especially for intermetal dielectric (IMD) layers, preventing crosstalk between different levels of metallization, and reducing device power consumption. Do.

Sub-half micron multilevel metallization is one of the key technologies for next generation ultra-scale integration ("VLSI"). Multilevel wiring at the heart of the present technology needs to planarize structures with high aspect ratios such as plugs and other wiring. Reliable formation of such wiring is critical to the success of VLSI and ongoing efforts to increase circuit density and quality for individual substrates and dies.

Conventional chemical vapor deposition (PVD) and physical vapor deposition (PVD) techniques for depositing electrically conductive materials into contact holes, vias, trenches, or other structures formed in a substrate. This is used. One problem with conventional processes arises because contact holes or other patterns often have a higher aspect ratio, that is, the ratio of the height of the hole to its width or diameter is often greater than one. As technology advances create spatially integrated characteristics, the aspect ratio of the holes increases.

Typically, the presence of inherent oxides and other contaminants in small features causes voids in the metal deposited in the structure, since the inherent oxides and other contaminants promote an uneven distribution of the deposited metal. The underlying oxide is formed as a result of exposing the exposed film layer / substrate to oxygen. Oxygen exposure occurs when the substrate is moved in the air between processing chambers in the atmospheric state, when a small amount of oxygen remaining in the vacuum chamber contacts the wafer / film layer, or the layer is projected by etching. Other contaminants in the structure may include sputtered material from oxide overetch, residual photoresist from a stripping process, residual hydrocarbon or fluorinated hydrocarbon polymer from a previous oxide etch step, or preclean sputter etch. redeposited material from the sputter etch process. Inherent oxides and other contaminants create regions on the substrate that interfere with film formation by creating regions that inhibit film growth. The increased growth region joins and blocks small structures before the limited growth region can be filled with the deposited metal.

The presence of inherent oxides and other contaminants may also increase via / contact resistance and reduce the electromigration resistance of small devices. Contaminants can diffuse into the dielectric layer, sublayer, or deposited metal to alter the performance of the device including small structures. Contamination may be limited to thin boundaries within the interface structure of the deposited metal and the conductive or semi-conductive structures underneath, but the thin boundaries are an important part of small structures. The acceptable level of contaminants in the structure decreases as the width of the structure becomes smaller.

Precleaning structures using a sputter etch process is effective for reducing contaminants in large structures or small structures with large structures or aspect ratios less than about 4: 1. However, the sputter etch process can damage the silicon layer by physical explosion, sputter deposition of Si / SiO ₂ on the sidewalls of the structures, and sputter deposition of a metal sublayer such as aluminum or copper on the sidewalls of the structures. . For large structures, the sputter etch process typically reduces the amount of contaminants in the structures to an acceptable level. For small structures with large aspect ratios, the sputter etch process is not as effective as removing contaminants within the structure, thus degrading the performance of the device formed.

Precleaning by the sputter etch process is not particularly suitable for structures with exposed copper. Copper easily diffuses through the dielectric, including the sidewalls of vias formed in the dielectric, destroying or degrading the integrity of the dielectric. This diffusion applies especially to TEOS, thermal oxides and any low K dielectric materials. Thus, a new preclean process is needed for copper preclean applications.

Referring to FIG. 1, a substrate 10 is shown that includes holes 11 formed in an electrically insulating or dielectric layer 12, such as, for example, silicon dioxide or silicon nitride layers. Since contaminants on the sidewalls 14 of the holes promote non-uniform deposition of the layer comprising the metal, it is difficult to deposit a layer containing the metal uniformly in the holes 11 of large aspect ratio. Eventually, the layer comprising metal converges over the width of the hole before it is completely filled, thereby forming voids and discontinuities in the hole. Thereafter, due to the high mobility of the metal atoms surrounding the pores, atoms diffuse and shrink the surface area of the circular pores as shown in FIG. These voids and discontinuities result in poor electrical contact and poor reliability.

Precleaning is primarily a sputter etch process where contaminants are sputtered from the substrate. It is preferably carried out by mixing an inert gas which is usually argon and a reaction gas which is usually hydrogen. A mixture of argon and hydrogen can be used to modify the shape of contact holes, vias, trenches and other patterns to remove both reactive and non-reactive contaminants and to improve subsequent metal deposition processes. By increasing the argon content in the preclean mixed gas, the etch rate of the preclean process is correspondingly increased and the etch uniformity of the preclean process is correspondingly reduced. To effectively remove reactive compounds or pollutants such as copper oxides and hydrocarbons, hydrogen must be included in the mixed gas. Precleaning the patterned substrate with a mixed gas of argon and any amount of hydrogen provides lower etch rate and increased etch nonuniformity compared to precleaning with argon.

A preclean process with both high concentrations of reactive gas and improved etch rate will substantially promote removal of contaminants by adding reactant gases.

U. S. Patent No. 5,660, 682 to Zhao et al. Describes an attempt to combine etching and reaction cleaning of a patterned dielectric layer using a plasma comprising hydrogen and argon. Argon etches deposits from the openings and hydrogen reacts with the remaining deposits to form gaseous byproducts. The combination of etching and cleaning improves subsequent metal deposition, but the combined plasma processing does not prevent the formation of voids in subsequent metal layers. Accordingly, what is needed is a method of improving the deposition of metal layers on patterned dielectric layers, openings such as vias and trenches with aspect ratios greater than about 1.0.

The present invention generally provides a method for improving the fill and electrical performance of metal deposited on a patterned dielectric layer. Openings such as vias and trenches in the patterned dielectric layer are etched and cleaned to enhance filling to reduce metal oxides in the openings. In one aspect, the present invention provides a method of cleaning a patterned dielectric layer in a processing chamber using a first plasma comprising predominantly argon, and a patterned dielectric layer in the processing chamber using a second plasma consisting essentially of hydrogen and helium. It provides a step of washing. After etching and cleaning, the openings are filled with metal, which may be deposited on the barrier / liner layer. It is preferred that both cleaning processes be carried out in the same chamber.

The present invention is also essentially argon produced by providing a patterned dielectric layer in a processing chamber by providing RF plasma power to an inductive coil surrounding the processing chamber and providing an RF bias to a substrate support member supporting the substrate. Provided is a method of cleaning using the first plasma. The patterned dielectric layer is created by increasing the supply of RF plasma power to the inductive coil surrounding the processing chamber consisting essentially of hydrogen and helium and reducing the supply of RF bias to the substrate support member supporting the substrate. Is cleaned in the processing chamber using a second plasma.

A barrier / liner layer may then be deposited on the patterned dielectric layer after exposing the dielectric layer to the first and second plasma, where a metal layer may be deposited over the barrier layer. In addition, sequential plasma processing may be performed in various plasma processing chambers of an integrated process sequence including preclean chambers, physical vapor deposition chambers, etch chambers, and other plasma processing chambers.

The present invention pre-cleans vias, contacts, and other structures etched in a dielectric layer, such as a silicon dioxide layer etched in a dry or wet etch chamber, to provide conductive or semiconducting (such as Ge, Si, Al, Cu, or TiN sublayers) A suitable method of exposing semi-conductive sublayers is provided. The etch exposes the sublayer so that the structure can be filled with a conductive or semiconductive material connecting the sublayer and subsequent metallization layers to be deposited on the dielectric layer. Etching the structure of the dielectric layer typically leaves contaminants that must be removed to improve the filling of the structure and ultimately improve the integrity and reliability of the formed device.

After etching the dielectric layer, the structures may have damaged silicon or metal residues in the structure from overetching the dielectric layer. The structures may also include residual photoresist on the surface of the structure from a photoresist stripping and / or ashing process, or may include residual hydrocarbons or fluorinated hydrocarbon polymers from the dielectric etch step. The structure surface may also include redeposited material produced by the sputter etch preclean process. Such contaminants can interfere with the selectivity of metallization by moving to the dielectric layer or by promoting a non-uniform distribution of the deposited metal. The presence of contaminants can also increase the resistance of the deposited metal by substantially narrowing the structure, creating narrow portions in the metal that form vias, contact lines, or other conductive structures.

Submicron structures cleaned and filled in accordance with the present invention are formed by conventional techniques for depositing a dielectric material over one surface on a semiconductor substrate. Any dielectric material now known or discovered, including low dielectric materials, such as organic polymers and aerogels, can be used within the scope of the present invention. The dielectric layer may include one or more separate layers and may be deposited on any suitable deposition enhancement sublayer. Preferred deposition enhancing sublayers include conductive metals such as Al, Cu, and barrier surfaces such as TiN, Ta, and TaN.

Once deposited, the dielectric layer is etched by the prior art to form vias, contacts, trenches or other submicron structures. Structures usually have a high aspect ratio with steep sidewalls. Etching the dielectric layer may be performed with any dielectric etch process, including plasma etching. Specific techniques for etching silicon dioxide include compounds such as C ₂ F ₆ , SF ₆ and NF ₃ . However, patterning may be performed in any layer using methods known in the art.

2 is a schematic diagram of a cluster tool system having multiple substrate processing chambers. The cluster tool system 100 includes vacuum load-lock chambers 105 and 110 attached to the first stage transfer chamber 115. The load lock chambers 105 and 110 remain vacuum in the first stage transfer chamber 115 while the substrate enters or exits the system 100. The first robot 120 transfers the substrates between the loadlock chambers 105, 110 and one or more substrate processing chambers 125, 130 attached to the first stage transfer chamber 115. Processing chambers 125 and 130 may be suitable for performing many substrate processing operations such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, preclean, degassing, orientation and other substrate processes. Can be. The first robot 120 also transfers the substrate to / from one or more transfer chambers 135 disposed between the first stage transfer chamber 115 and the second stage transfer chamber 140. Transfer chamber 135 is used to maintain a very high vacuum in the second stage transfer chamber 140 while allowing the substrate to be transferred between the first stage transfer chamber 115 and the second stage transfer chamber 140. do. The second robot 145 transfers the substrate between the transfer chamber 135 and the plurality of substrate processing chambers 150, 155, 160, and 165.

Similar to the processing chambers 125 and 130 described above, additional processing chambers 150 and 165 may be adapted to perform various substrate processing operations. For example, the processing chamber 150 is a CVD chamber suitable for depositing a silicon oxide film, the processing chamber 155 is an etching chamber suitable for etching openings or openings for wiring structures, and the processing chamber 160 is tantalum. And / or a PVD chamber suitable for reactive sputter deposition of barrier films such as tantalum nitride, and processing chamber 165 is a PVD chamber suitable for sputter deposition of conductive films such as copper. The above-described sequence arrangement of processing chambers is useful for practicing the present invention. Multiple cluster tool systems may be required to perform all the processes necessary to complete the interconnects of integrated circuit or chip fabrication.

During operation, the substrates are moved to the vacuum load lock chambers 105, 110 by a conveyor belt or a robotic system (not shown) operating under the control of a computer program executed by a microprocessor or computer (not shown). Robots 120 and 145 also operate under the control of a computer program to transfer the substrate between the various processing chambers of cluster tool system 100.

The cluster tool system described above is primarily for illustrative purposes. Other plasma processing devices, such as electron cyclotron resonance (ECR) plasma processing devices, inductively coupled RF high density plasma processing devices, and the like, can be used as part of the cluster tool system. In addition, the method for forming the silicon oxide layer and barrier layer of the present invention is not limited to any particular apparatus or specific plasma excitation method.

3 is a flow chart illustrating the argon preclean step and the hydrogen plasma preclean step of the present invention, along with other process sequence steps that occur before and after the hydrogen plasma preclean step. The steps shown in FIG. 3 may be performed in response to instructions of a computer program executed by a microprocessor or computer controller for the cluster tool system 100.

First, a dielectric layer is deposited on the substrate (step 200). Deposition of a dielectric layer, such as a silicon oxide film, can be accomplished through various methods known in the art. The dielectric layer is preferably deposited using, for example, a chemical vapor deposition process performed in the CVD chamber 150 shown in FIG. However, prior to depositing the dielectric layer, the substrate typically undergoes multiple processing steps to form active devices and other structures as will be understood by those skilled in the art.

Second, the dielectric layer may be planarized (step 205) in preparation for depositing the underlying layer. Planarization processes may include chemical mechanical polishing (CMP), etching, or other similar processes. Openings or openings for interconnect structures such as contacts and vias are etched in the dielectric layer (step 210). Sputter etching processes may be performed in a typical etch chamber, such as etch chamber 155, as shown in cluster tool system 100 of FIG. 2. Usually, the dielectric layer is about 0.5 to 3.0 microns thick, and the interconnect structure has a sub-quarter micron opening and an aspect ratio (a ratio of width to height) greater than 1: 1. Steps 205 and 210 produce a patterned substrate having wiring structures to be metallized or filled with a layer of material.

Third, argon plasma cleaning (step 212) in accordance with the present invention is performed on a patterned substrate to remove deposits from previous process steps. In the argon plasma step, deposits are sputtered by the argon plasma and removed from the openings. The argon sputter process can be performed in a variety of chambers, but is preferably performed in a preclean chamber. Fourth, the hydrogen plasma precleaning step according to the present invention is performed on a patterned substrate. The substrate is pre-cleaned (step 215) using hydrogen plasma to convert copper oxide to copper and to clean and stabilize the structure of the dielectric layer. Although the preclean step may be performed in any typical plasma processing chamber, the preclean step is preferably performed in the preclean chamber. The argon plasma etch and hydrogen plasma preclean steps according to the invention are discussed in more detail with reference to the preclean chamber shown in FIG. 5.

A diffusion barrier layer, preferably tantalum nitride, is then deposited (step 220) to prevent diffusion of silicon into the overlying metal layer. The diffusion barrier layer also improves film adhesion between different films such as metal films and silicon oxide films. Tantalum nitride layers are preferably deposited using PVD chambers suitable for reactive sputtering known in the art. The diffusion barrier layer preferably has a film having a thickness of about 50 kPa to 200 kPa.

4 is a cross-sectional view of a typical PVD chamber useful for depositing a barrier layer. The PVD chamber 310 generally includes a chamber enclosure 312, a substrate support 314, a target 316, a shield 318, a clamp ring 320, a gas inlet. inlet 322, gas exhaust 324, magnet assembly 326, RF plasma power source 328, and RF bias source 334. During processing, the substrate 330 is positioned on the substrate support member 314, and the processing gas passes through the gas inlet 322 disposed between the edge of the target and the upper portion of the shield, so that the target 316, the substrate ( 330, and a processing region 332 defined by shield 318. The RF plasma power source 328 provides RF power to the target to collide with and maintain a plasma of the processing gas within the processing region 332 during processing, while the RF bias source 334 is a substrate support member 314 ) Provides RF bias. Shield 318 is typically grounded during processing. During deposition, ions in the plasma collide with the target to sputter material from the target surface. The sputtered material reacts with the ions in the plasma and forms a film on the substrate surface. In order to deposit barrier films such as tantalum / tantalum nitride, the processing gas typically includes argon and nitrogen, argon serving primarily as a gas source for plasma ions that strike the target 316 and nitrogen primarily the target 316. Reacts with atoms sputtered from (tantalum) to form a tantalum / tantalum nitride film deposited on the substrate 330. After depositing the barrier film, the substrate is usually annealed at a temperature between about 300 to 500 ° C. to improve the material properties of the deposited film.

Recently, a metal layer, such as copper, is deposited on the diffusion barrier layer to complete the formation of the interconnect structure (step 225). The metal layer preferably has a thickness of about 6,000 to 10,000 kPa. Copper deposition can be performed in typical PVD chambers or typical CVD chambers known in the art. The process described above may be repeated for a multilevel integrated circuit structure.

According to the present invention, the patterned dielectric layer is pre-cleaned using an argon plasma before depositing a tantalum nitride barrier layer and then using a hydrogen plasma. The preclean process can be performed in a variety of processing chambers including PVD chambers, CVD chambers, etch chambers and preclean chambers. The preclean process is preferably performed using a preclean chamber before depositing the tantalum nitride barrier layer. Although the invention is described using a preclean chamber, the invention is applicable to a variety of processing chambers.

5 is a cross-sectional view of a typical preclean chamber useful in the present invention. An example of a preclean chamber useful in the present invention is a preclean II chamber of Applied Materials, Santa Clara, California. In general, the preclean chamber 510 has a substrate support member 512 disposed in the chamber enclosure 514 under a quartz dome 516. The substrate support member 512 usually includes a central pedestal plate 518 disposed in a recess 520 on the insulating plate 522, usually composed of quartz, ceramic, or the like. . During processing, the substrate 524 is placed on the central pedestal plate 518 and contained therein by a locating pin 532. An RF coil 526 is preferably disposed outside the crystal dome 516 and connected to the RF power source 524 in order to collide with the plasma of the process gas and maintain the plasma within the chamber. In general, an RF match network 530 is provided to match the RF power source 524 and the RF coil 526. The substrate support member 512 is connected with an RF bias source 528 that provides a bias to the substrate support member 512. The RF power source 524 preferably provides up to about 500 W of 2 MHz RF power to the coil 526 and the RF bias source 528 provides up to about 500 W of 13.56 MHz RF bias to the substrate support member 512. It is preferable.

According to the invention, the patterned or etched substrate is preferably precleaned using an argon plasma and then a hydrogen plasma in a preclean chamber before depositing the barrier layer. It is desirable that the substrate be transferred to a preclean chamber after the dielectric layer is planarized and the opening of the wiring structure is formed. Before the substrate is transferred to a system or processing platform with a preclean chamber, the pattern etch of the substrate may be processed in another processing platform or system. Once the substrate is positioned for processing in the preclean chamber, a processing gas containing primarily argon, ie at least about 50% in atomic number, is preferably introduced into the processing region at a pressure of about 0.8 mtorr. Plasma of argon gas is impinged in the processing region such that the substrate undergoes an argon sputter cleaning environment. The argon plasma applies about 50 to 500 W of RF power from the RF power source 524 to the RF coil 526 and applies about 50 to 500 W of RF bias from the RF bias source 528 to the substrate support member 512. It is desirable to produce. The argon plasma is maintained for about 10 to 300 seconds to provide sufficient cleaning time for deposits that are not easily removed by the reactive hydrogen plasma. The argon plasma is preferably generated by about 300 W RF power applied to the coil and about 300 W RF bias applied to the substrate support member, and is preferably maintained for about 60 seconds.

Following the argon plasma, the chamber pressure is increased to about 80 mtorr, consisting essentially of hydrogen and helium, and from about 5% to about 100% hydrogen and about 0% to 95% helium by atomic number The processing gas comprising is led to a processing region. The processing gas preferably comprises about 5% hydrogen and about 95% helium. The plasma of hydrogen / helium gas impinges in the processing region causing the substrate to undergo a reactive hydrogen plasma environment. The hydrogen plasma applies about 50W to 500W of power from the RF power source 524 to the RF coil 526 and applies an RF bias of about 5W to 300W from the RF bias source 528 to the substrate support member 512. Is generated. The hydrogen plasma is maintained for about 10 to 300 seconds to convert the copper oxide to copper and clean the substrate. The hydrogen plasma is preferably generated by an RF power of about 450 W applied to the coil and an RF bias of about 10 W applied to the substrate support member, and is preferably maintained for about 60 seconds. Once the preclean process is complete, the preclean chamber is evacuated of the processing gases and reaction byproducts from the preclean process. A barrier layer is then deposited on the cleaned substrate, after which the remaining process outlined in FIG. 3 is performed.

While the foregoing description has been described as preferred embodiments of the invention, other embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow.

The present invention generally provides a method for improving the electrical performance and filling of metal deposited on a patterned dielectric layer. Openings such as vias and trenches in the patterned dielectric layer are etched to enhance filling and are cleaned in the same chamber to reduce metal oxides in the openings. The invention also consists essentially of argon and is patterned in a processing chamber with a first plasma created by providing RF power to an inductive coil surrounding the processing chamber and providing an RF bias to a substrate support member supporting the substrate. Cleaning the dielectric layer, consisting essentially of hydrogen and helium, a second plasma generated by increasing the RF power supply of the inductive coil surrounding the processing chamber and reducing the RF bias provision to the substrate support member supporting the substrate Cleaning the patterned dielectric layer in a raw processing chamber, exposing the dielectric layer to the first and second plasma and then depositing a barrier layer on the patterned dielectric layer, and depositing a metal on the barrier layer To provide. In addition, sequential plasma processing may be performed in various plasma processing chambers of an integrated process sequence, including pre-clean chambers, physical vapor deposition chambers, etch chambers, and other plasma processing chambers.

Claims (13)

a) cleaning the patterned dielectric layer in the processing chamber using a first plasma comprising argon, and b) cleaning the patterned dielectric layer in the processing chamber using hydrogen and helium, and using a second plasma. The method of claim 1, Exposing the dielectric layer to the first plasma and the second plasma and then depositing a metal on the patterned dielectric layer. a) cleaning the patterned dielectric layer in the processing chamber with a first plasma comprising argon and providing RF power to a coil surrounding the processing chamber and providing an RF bias to a substrate support member supporting the substrate; ; b) the patterned within the processing chamber with a second plasma, comprising hydrogen and helium, the RF being applied to a coil surrounding the processing chamber and providing an RF bias to a substrate support member supporting the substrate. Cleaning the dielectric layer; And c) depositing a metal on the patterned dielectric layer after exposing the dielectric layer to the first plasma and the second plasma; And a metal deposition on the patterned dielectric layer on the substrate. The method according to claim 1 or 3, And the first plasma comprises argon. The method of claim 3, wherein Depositing a barrier layer on the patterned dielectric layer prior to depositing the metal. The method of claim 3, wherein Less RF bias is provided to the substrate support member to generate the second plasma than is provided to the substrate support member to generate the first plasma. a) cleaning the patterned dielectric layer in the processing chamber with a first plasma comprising argon and generated by providing RF power to a coil surrounding the processing chamber and providing an RF bias to a substrate support member supporting the substrate. ; b) within the processing chamber with a second plasma comprising hydrogen and helium, the RF plasma being provided by increasing the RF power provided to the coil surrounding the processing chamber and reducing the RF bias provided to the substrate support member supporting the substrate. Cleaning the patterned dielectric layer at; c) exposing the dielectric layer to the first plasma and the second plasma and then depositing a barrier layer on the patterned dielectric layer; And d) depositing a metal on the barrier layer And a metal deposition on the patterned dielectric layer on the substrate. The method according to any one of claims 1, 3 and 7, Said processing chamber is a preclean chamber. The method according to claim 1 or 7, Wherein the second plasma comprises at least 5% and less than 100% hydrogen in atomic number and more than 0% and 95% helium in atomic number. The method according to claim 3 or 7, Wherein the second plasma comprises 5% hydrogen in atomic number and 95% helium in atomic number. The method according to claim 3 or 7, The first plasma is generated by providing 300 W of RF power to the coil and 300 W of RF bias to the substrate support member, and the second plasma provides 450 W of RF power to the coil and the substrate support member. Generated by providing an RF bias of 10W. The method according to claim 3 or 7, Each of the first plasma and the second plasma for 60 seconds in the processing chamber. The method of claim 7, wherein The first plasma is generated at a pressure of 0.8 mtorr in the processing chamber and the second plasma is generated at a pressure of 80 mtorr in the processing chamber.

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