KR100662590B1 - Printing with a multi-segment printhead - Google Patents

Abstract

A method of preparing print data for a multi-segment printhead, comprising:

A method of preparing print data for a multi-segment printhead sets up a set of dither matrices for a multi-segment printhead consisting of a plurality of printhead chips with overlapping ends, the set leading-in in) a lead-in dither matrix associated with the overlap portion; A lead-out dither matrix associated with the lead-out overlap portion; It consists of a common dither matrix associated with the central portion of the printhead chip. Upon receiving the print data, dither values are synthesized from the set. The lead-in dither value sets the fade-in of one segment, and the lead-out dither value sets the fade-out of the preceding segment. In each of the two overlapping segments, the overlap is characterized in the condition of the misalignment, which is used to generate an offset leading to the common dither matrix.

Description

Printing with multi-segment printheads {PRINTING WITH A MULTI-SEGMENT PRINTHEAD}

The present invention relates to printing with a print having a multi-segment print head, and more particularly to the application of dither.

A range of printer types has evolved into images composed of ink that is selectively applied to pages in dot format. In US Pat. No. 6045710, 'Self-aligned construction and manufacturing process for monolithic printheads' by inventor Kia Silverbrook, a drop-on-demand printer. The evaluation of the prior art with regard to the manufacturing method is presented.

Various methods, systems, and apparatus related to the present invention are disclosed in the pending applications below filed May 24, 2000 by the applicant or assignee of the present invention concurrently with the present application.

PCT / AU00 / 00518, PCT / AU00 / 00519, PCT / AU00 / 00520, PCT / AU00 / 00521, PCT / AU00 / 00523, PCT / AU00 / 00524, PCT / AU00 / 00525, PCT / AU00 / 00526, PCT / AU00 / 00527, PCT / AU00 / 00528, PCT / AU00 / 00529, PCT / AU00 / 00530, PCT / AU00 / 00531, PCT / AU00 / 00532, PCT / AU00 / 00533, PCT / AU00 / 00534, PCT / AU00 / 00535, PCT / AU00 / 00536, PCT / AU00 / 00537, PCT / AU00 / 00538, PCT / AU00 / 00539, PCT / AU00 / 00540, PCT / AU00 / 00541, PCT / AU00 / 00542, PCT / AU00 / 00543, PCT / AU00 / 00544, PCT / AU00 / 00545, PCT / AU00 / 00547, PCT / AU00 / 00546, PCT / AU00 / 00554, PCT / AU00 / 00556, PCT / AU00 / 00557, PCT / AU00 / 00558, PCT / AU00 / 00559, PCT / AU00 / 00560, PCT / AU00 / 00561, PCT / AU00 / 00562, PCT / AU00 / 00563, PCT / AU00 / 00564, PCT / AU00 / 00566, PCT / AU00 / 00567, PCT / AU00 / 00568, PCT / AU00 / 00569, PCT / AU00 / 00570, PCT / AU00 / 00571, PCT / AU00 / 00572, PCT / AU00 / 00573, PCT / AU00 / 00574, PCT / AU00 / 00575, PCT / AU00 / 00576, PCT / AU00 / 00577, PCT / AU00 / 00578, PCT / AU00 / 00579, PCT / AU00 / 00581, PCT / AU00 / 00580, PCT / AU00 / 00582, PCT / AU00 / 00587, PCT / AU00 / 00588, PCT / AU00 / 00589, PCT / AU00 / 00583, PCT / AU00 / 00593, PCT / AU00 / 00590, PCT / AU0 0/00591, PCT / AU00 / 00592, PCT / AU00 / 00594, PCT / AU00 / 00595, PCT / AU00 / 00596, PCT / AU00 / 00597, PCT / AU00 / 00598, PCT / AU00 / 00516, PCT / AU00 / 00517, PCT / AU00 / 00511,

The above applications are referred to as cross-references in connection with the present application.

In addition, various methods, systems, and apparatus related to the present invention are disclosed in the following pending PCT applications filed by the applicant or the assignee of the present invention: PCT / AU00 / 00754, PCT / AU00 / 00755, PCT / AU00 / 00757.

The above applications are referenced as cross-references in connection with the present application.

Of particular interest are the PCT patent applications PCT / AU00 / 00591, PCT / AU00 / 00578, PCT / AU00 / 00579, PCT / AU00 / 00592 and PCT / AU00 / 00590, which are pending simultaneously with this application. It describes a microelectromechanical drop on demand printhead called a Memjet printhead.

Memjet printheads have been improved from, for example, printhead segments that can produce 1600 dpi bi-level dots of liquid ink over the entire width of the page. Dots are easily separated and generated, allowing distributed dot dithering to be utilized to the maximum. Color planes can be printed with perfect registration, allowing for ideal dot-on-dot printing. The printhead enables high speed printing using electromechanical ink drop technology.

In addition, pending PCT applications PCT / AU00 / 00516, PCT / AU00 / 00517, PCT / AU00 / 00511, PCT / AU00 / 00754,, PCT / AU00 / 00755 and PCT / AU00 / 00757 which are filed simultaneously with the present application A print engine / controller suitable for driving the referenced page width printhead is described.

The print engine / controller used to drive the printhead puts the received print data at the printhead nozzle. It is known to apply dither to data.

In particular, PCT / AU00 / 00754 describes a print engine / controller application useful for interfacing multiple print engine / controller chips to a multi-segment printhead. Reference may be made to the detailed description of the print engine / controller to which dither processes and characterization vectors may be added.

In such multi-segment printheads, there is a problem of maintaining brightness and average dot gain in overlapping pairs of printhead segments, which is further exacerbated by misalignment of the segments. . There is a need for a dither process that takes these issues into account.

[Overview of invention]

In one aspect, the present invention relates to a method of preparing print data for a multi-segment printhead, comprising a lead-in overlap for a multi-segment printhead consisting of a plurality of printhead chips with overlapping ends. a dither matrix consisting of a lead-in dither matrix associated with the (overlap) portion, a lead-out dither matrix associated with the lead-out overlap portion, and a common dither matrix associated with the central portion of the printhead chip Setting a set of;

Receiving print data;

Accessing the dither matrix set and applying dither to the received data when the received data is synthesized such that a nearly constant dot gain is maintained in the resulting image over an overlap portion.

The overlap for each set of two overlapping segments is characterized under the condition of misalignment. The misalignment is used to generate a lead-in read-out dither matrix and to generate an offset in the standard third dither matrix. Lead-in lead-out dither matrices are used in combination on the overlap area. One may be a fadeout dither matrix, then the other is a fade-in dither matrix. They are created so that the combination of the two dither matrices provides a constant dot gain on the overlap area.

The offset is required to determine where to go in the third dither matrix once the fade-in is complete. The third dither matrix can be considered a standard dither matrix and the other two matrices can be considered as providing cross-fade. One dither matrix of the other two matrices fades out and the other fades in.

Because of misalignment, it is not desirable to simply go straight to the standard dither matrix as soon as it passes through the overlap. Instead, it may be necessary to go to another column of the standard dither matrix depending on the misalignment.

Thus, at least three dither matrices are preferred. The standard dither matrix is common across all segments for non-overlapping bits, and there is a pair of dither matrices per overlap. One fades out from the common dither matrix and the other fades in into the common dither matrix. Unaligned information can be obtained from a characterization vector stored in each printhead segment. The characteristic vector can also store dead nozzle data. Contone CMYK layers are synthesized using a dither matrix selected by a dither matrix select map. The dither contone layer has appropriate Netpage tag data added to the contone layer with a black layer. The combination is sent to a multi-segment printhead. The datastream can be adjusted to make a smooth transition across the overlapping segments, to compensate for dead nozzles within the printhead with reference to the printhead characterization vector. The resolution of the dither matrix selection map should fit perfectly with the continuous tone resolution.

Each printhead segment can be queried over a slow serial bus to return the characterization vector of each segment. Characterization vectors from multiple printhead chips can be combined to construct a nozzle defect list for the entire multi-segment printhead, allowing the print engine to compensate for defective nozzles during printing. If the number of defective nozzles is small, this compensation can produce indistinguishable results from a printhead without a defective nozzle.

1 illustrates the functions performed by a print engine controller suitable for driving data flow and multi-segment printheads;

2 illustrates a print engine in an environment of an overall printer system architecture;

3 is a diagram illustrating a print engine controller architecture;

4 illustrates an external interface to the halftoner / compositor unit (HCU) of FIG. 3, FIG.

5 is a diagram illustrating an internal circuit of the HCU of FIG. 4;

6 is a block diagram illustrating a process within the dot merge unit of FIG. 5;

FIG. 7 illustrates a process within the dot reorganization unit of FIG. 5;

8 illustrates a process within the line loader / format unit (LLFU) of FIG. 5;

9 is a diagram showing an internal circuit which generates color data in the LLFU of FIG. 8;

10 and 11 illustrate the components of the LLFU shown in FIG. 9;

12 illustrates a method of segment overlap in a multi-segment printhead;

FIG. 13 is a diagram illustrating one line synthesis in a multi-segment dither matrix. FIG.

A typical 12 inch printhead width is controlled by one or more print engines / controllers (PECs) for full-bleed printing of A4 and letter size pages, as described below. The six channels of color ink are the maximum expected in current printing environments, these are:                 

CMY, for regular color printing

For K, black text and other black prints,

ㆍ for IR (infrared), taggable applications,

ㆍ F (fixing solution, fixative), for high speed printing.

PEC can be installed on a single chip that interfaces with the printhead. It includes four basic levels of functionality:

Receive compressed pages through a serial interface such as IEEE 1394

Print engine for generating pages from compressed form. The function of the print engine includes enlargement of the page image, dithering the continuous tone layer, compositing the black layer on the continuous tone layer, optionally adding an infrared tag, and sending the composite image to the printhead.

Print controller for controlling printheads and stepper motors.

Two standard low speed serial ports for communicating with two QA chips. There must be two ports, and there should not be only one port to ensure secure security during the authentication process.

Because of the page-width nature of the memjet printhead, each page must be printed at a constant rate so that no visible artifacts are produced. This means that the printing speed cannot change with the input data rate.

Thus document rasterization and document printing are separated to ensure that the printhead has a constant supply of data. The page does not print until it is completely rasterized. This can be done by storing a compressed page of each rasterized page image in memory. This separation also allows the RIP (s) to go to the front of the printer when rastering simple pages, gaining time to raster more complex pages.

Continent color images are reproduced by stochastic dithering, but because black text and line graphics are directly reproduced using dots, the compressed page image format is a foreground two-level black layer and background. ) Has a continuous tone color layer separately. The black layer is synthesized on the continuous tone layer after the continuous tone layer is dithered (although the continuous tone layer has an optional black element). The final layer of the netpage tag (in infrared or black ink) is optionally added to the page for printout.

RIP software / hardware rasterizes each page description and compresses the rasterized page image. Each compressed page image is transferred to memory.

In the page depiction, the dither matrix selection areas are rasterized into continuous tone-resolution two-level bitmaps, the bitmaps are compressed to a negligible size without loss, and form part of the compressed page image. The infrared (IR) layer of the printed page includes a netpage tag encoded at a density that can be optionally programmed.

In Fig. 1, the document is received at 11 and loaded into the memory buffer 12, a page layout is made and all the necessary objects can be added. Pages from memory 12 are rasterized at 13 and compressed at 14 before being sent to print engine controller 10. The pages are received into the memory buffer 15 as compressed page images in the print engine controller 10 and supplied from the memory buffer to the page enlarger 16 so that the page images are retrieved. Any necessary dither can be applied to any continuous tone layer at 17. Any black two-level layer may be synthesized over the continuous tone layer at 18 and may be synthesized with any infrared tag at 19. The synthesized page data is printed at 20 to produce page 21.

In the first stage of the pipeline, the JPEG-compressed continuous-tone CMYK layer (see below) is expanded and the Group 4 Fax-compressed bi-level dither matrix selection map ) (See below), and zoom in on a two-level black layer (see below) compressed with Group 4 fax in parallel. In parallel, the tag encoder encodes two-level IR tag data in the compressed page image. In the second step, dither the continuous tone CMYK layer using the dither matrix selected by the dither matrix selection map, and synthesize a 2-level black layer on the resulting 2-level K layer, Add an IR layer to the page. A fixative layer is also created at each dot position wherever needed in the C, M, Y, K or IR channels. The final step is to print the two-level CMYK + IR data through the printhead via the printhead interface (see below).

2 shows how the print engine / controller 10 fits into the overall printer system architecture. Various components of the printer system may include the following.

Print Engine / Controller (PEC). The PEC chip 10, or chips, is responsible for receiving a compressed page image for storage in the memory buffer 24, page magnification, black layer composition, and dot data transmission to the print head 23. It may also be in communication with the QA chips 25 and 26, and may provide a means for retrieving features of the print head to ensure optimal printing. PEC is the subject of this specification.

Memory buffer. The memory buffer 24 is for storing compressed page images and using scratches during printing of a given page. The construction and operation of the memory buffer is known to those skilled in the art, and a range of standard chips and their utilization techniques can be utilized for the use of the PEC of the present invention.

Master QA chip. The master chip 25 is matched to the replaceable ink cartridge QA chip 26. The construction and operation of the QA unit is known to those skilled in the art, and known QA processes within a certain range can be utilized for use of the print engine control furnace (PEC) of the present invention. For example, QA chips are described in the ongoing US patent application below.

USSN Our serial number Our name TBA AUTH01 Validation Protocol and System 09 / 112,763 AUTH02 Circuit for Protecting Chips Against IDD Fluctuation Attacks 09 / 112,737 AUTH04 Method for Protecting On-Chip Memory (Flash and RAM) 09 / 112,761 AUTH05 Method for Making a Chip Tamper-Resistant 09 / 113,223 AUTH06 A system for authenticating physical objects TBA AUTH07 Validation Protocol and System TBA AUTH08 Validation Protocol and System 09 / 505,003 AUTH09 Consumable Authentication Protocol and System 09 / 517,608 AUTH10 Consumable Authentication Protocol and System 09 / 505,147 AUTH11 Consumable Authentication Protocol and System 09 / 505,952 AUTH12 Unauthorized Modification of Values Stored in Flash Memory TBA AUTH13 A system form the Manipulation of Secure Data 09 / 516,874 AUTH14 An Authentication Chip with Protection from Power Supply Attacks TBA AUTH15 Shielding Manipulation of Secret Data

Since QA chip communication plays a role not only in the operation of the physical printhead but also in the image enlargement, it may be most desirable to be included in the overall function of the PEC chip. By placing QA chip communication, it is possible to ensure that there is enough ink to print the page. Preferably, a QA embedded in the printhead assembly (QA) may be implemented using an authentication chip. Because it is a master QA chip, it can only contain an authentication key, not user-data. However, it must be matched with the QA chip of the ink cartridge. The QA chip in the ink cartridge contains the necessary information to maintain the best print quality possible and is implemented using an authentication chip.

Preferably, the PEC chip will add a simple micro-controller CPU core 35 to perform the following functions:                 

Performing QA chip authentication protocol via serial interface 36 between print pages

Driving the stepper motor via the parallel interface 91 during printing (the stepper motor requires a 5KHz process).

Synchronizing various parts of the PEC chip during printing

Providing means for interfacing external data requests (such as programming registers)

Providing means for interfacing printhead segment slow data requests (such as reading a characterization vector and recording a pulse profile);

To provide a means for recording the portrait and landscape tag structures on an external DRAM.

3 is a diagram illustrating a print engine architecture. Print engine page magnification and printing pipelines include high speed serial interface 27 (such as standard IEEE 1394 interface), standard JPEG decoder 28, standard group 4 fax decoder, custom halftoner / synthesizer unit 29, custom tags It consists of an encoder 30, a line loader / formatter unit 31 and a custom interface 32 that follows the printhead 33. Decoder 28, 88 and encoder 30 are buffered in half toner / synthesizer 29. The tag encoder 30 installs an infrared tag or tags on the page according to a protocol that depends on the purpose of using the page, but the actual contents of the tag are not the subject of the present invention.

The print engine operates in a double buffer mode. While one page is loaded from the high speed serial interface 27 to the DRAM 34 via the DRAM interface 89 and the data bus 90, the previously loaded page is read from the DRAM 34 Pass through the print engine pipeline. Once the page has been printed, the just loaded page becomes the page to be printed, and a new page is loaded via the high speed serial interface 27. In the first stage, the pipeline enlarges the continuous tone (CMYK) layer compressed with any JPEG and expands the two-level data stream compressed with any two Group 4 faxes. Two rows are used for the black layer (although the PEC is actually color agnostic and this two-level layer can be indicated with any of the output inks) and for continuous tone dithering (see below). A matte for choosing from dither matrices. In the second step, in parallel with the first step, a predetermined tag for later rendering with infrared or black ink is encoded. Finally, in the third step, the continuous tone layer is dithered, and the location tag and the bi-level spot1 layer are synthesized on the resulting bi-level dithered layer. The data stream is ideally adjusted to create a smooth transition across the overlapping segments in the printhead, and ideally it is adjusted to compensate for dead nozzles in the printhead. . Up to six channels of two-level data can be generated at this stage. Note that not all six channels can exist on the printhead. For example, the printhead can only have CMY, K can be pushed to the CMY channel, and IR can be ignored. Or, if the IR ink is not available (or for testing purposes), the location tag may be printed as K. The resulting two-level CMYK-IR dot data is buffered and formatted to be printed on the print head 33 via a set of line buffers (see below). Most of these line buffers can ideally be stored on off-chip DRAM 34. In the final step, the six-channel two-level dot data is printed via the printhead interface 32.

In Fig. 4, the halftoner / synthesizer unit (HCU) 29 has the ability to halfton the continuous tone (generally CMKY) layer to the same two-level version and the halftone toned continuous tone layer (suitable for spot1 two-level layers). S) combine the functions of synthesis. If the printer has no K ink, the HCU 29 can map K to CMY dots as appropriate. It also selects from two dither matrices based on pixel by pixel, based on the corresponding values in the dither matrix selection map. Input to HCU 29 is an expanded contone layer (from JPEG decoder unit) through buffer 37, an enlarged two-level Spotl layer through buffer 38, generally a buffer ( 39 is an enlarged dither-matrix-select bitmap at the same resolution as the continuous tone layer through 39 and tag data at full dot resolution through the buffer 40. The HCU 29 uses up to two dither matrices that are read from the external DRAM 34. At 41, the output from the HCU 29 to the line loader / formatter unit (LLFU) is a set of printer resolution two-level image lines in up to six colors. Typically, the continuous tone layer is CMYK or CMY and the two-level Spot1 layer is K.

5 shows the HCU in more detail. Once started, the HCU proceeds until it detects a page of end condition or until it is explicitly stopped through its control register. The first task of the HCU is to scale all data received at the buffer side, such as 42, horizontally and vertically, at each resolution unit, such as scale unit 43, to the printer resolution.

The scale unit provides a means for scaling continuous tone or two-level data horizontally and vertically to printer resolution. Scaling is achieved by replicating data values an integer number of times in both dimensions. The process of scaling data will be familiar to those skilled in the art.

The margin unit 57 provides two control bits, that is, an advance dot and an advance line, to the scale unit 43. Advanced dot bits allow a state machine to generate multiple instances of the same dot data (useful for generating dot data for page margins and overlapping segments in the printhead). The advance line bit allows the state machine to control when a line of a particular dot is completed, thereby truncating the data according to the printer margin. It also saves the trouble that the scale unit requires special end-of-line logic. The input to the scale unit is a full-line buffer. The lines are used as scale factor times to achieve vertical up-scale via line replication, and within each line, each value is used as scale factor times to achieve horizontal up-scale via pixel replication. Once the input line has been used with scale factor times (advanced line bits are set to scale factor times), the input buffer select bits of the address are toggled (double buffering). The logic for the scale unit is the same as the 8-bit and 1-bit case, because the scale unit only generates addresses.

Since each continuous tone layer can be of different resolution, they are scaled independently. The two-level Spotl layer of buffer 45 and the dither matrix selection layer of buffer 46 also need to be scaled. The two-level tag data of the buffer 47 is arranged at the correct resolution and does not need to be scaled. The scale-up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bit value from the two dither matrices. The 8-bit value is output to four comparators 44 and 49-51, which simply compare it with a particular 8-bit contone value. The generation of the actual dither matrix depends on the structure of the printhead, and the general generation process will be familiar to those skilled in the art. If the continuous tone value is greater than the 8-bit dither matrix value, 1 is output. If not, 0 is printed. These bits are then ANDed from 52 to 56 together with the inPage bit from the margin unit 57 (whether or not a particular dot is within the printable area of the page). ). The final stage of the HCU is the composition stage. There is a single dot merger unit, such as unit 58, with six inputs for each of the six output layers. The single output bit from each dot merging unit is a combination of some or all of the input bits. This allows spot colors to be placed on any output color plane (including infrared for testing purposes), blacks merged into cyan, magenta, and yellow (if black ink is not in the printhead), and the tag dot data is visible. Make sure it's on a visible plane. Fixative color planes can also be easily generated. A dot reorg unit (DRU) 59 takes a sequence of dots generated for a given color plane, outputs in in segment order, and within a segment, a 32 bit amount (32). -bit quantity). Due to the fact that dots for overlapping segments are not generated in segment order, minimal reordering is required.

The margin unit 57 provides two control bits to the scale unit, namely, an advance dot and an advance line. Advanced dot bits allow a state machine to generate multiple instances of the same dot data (useful for generating dot data for page margins and overlapping segments in the printhead). The advance line bit allows the state machine to control when a line of a particular dot is completed, thereby truncating the data according to the printer margin. It also saves the trouble that the scale unit requires special end-of-line logic.                 

The comparator unit contains a simple 8 bit "greater-than" comparator. It is used to determine whether the 8-bit continuous tone value is greater than the 8-bit dither matrix value. As such, the comparator unit takes two 8-bit inputs and produces a single 1-bit output.

6 illustrates the dot merging unit in more detail. It provides a means to map dithered bi-level dithered data, Spot1 color and tag data from the actual printhead to the output ink. Each dot merging unit takes six 1-bit inputs and produces a single bit output that represents the output dot for that color plane. The output bit at 60 is a combination of some or all of the input bits. This allows the spot color to be located within any output color plane (including infrared for testing purposes), blacks merged into cyan, magenta, and yellow (if there is no black ink in the printhead), and if tag dot data is visible To be located at The output for the fixer can be easily generated by simply combining all the input bits. The dot merging unit includes a 6-bit ColorMask register 61 used as a mask for six input bits. Each input bit is ANDed with the corresponding colormask register bit, and the resulting six bits are ORed together to form the final output bit.

In Fig. 7, a dot reorg unit responsible for taking the generated dot sequence for a given color plane and organizing the dot sequence in 32-bit quantities so that the output is in the order of the segments and in the order of the dots within the segment ( DRU) is shown. Due to the fact that dots for overlapping segments are not generated in segment order, minimal reordering is necessary. The DRU includes a 32-bit shift register, a general 32 bit register and a general 16 bit register. A 5-bit counter counts the number of bits processed so far. A dot advance signal from a dither matrix access unit (DMAU) is used to indicate which bits should be output to the DRU.

In Fig. 7, register (A) 62 is clocked every cycle. It contains the 32 most recent dots generated by the dot merger unit (DMU). All 32-bit values are generated by the DRU state machine every 32 cycles and copied to register (B) 63 by a WriteEnable signal via a simple 5-bit counter. Sixteen odd bits (bits 1, 3, 5, 7, etc.) in register (B) 63 are copied to register (C) 65 by the same Write Enable pulse. The 32-bit multiplexer 66 then selects from the following three outputs based on the two bits from the state machine:

All 32 bits from register (B)

A 32-bit value made from 16 even bits (bits 0, 2, 4, 6, etc.) of register A and 16 even bits of register B. Sixteen even bits from register A form bits 0-15, while sixteen even bits from register B form bits 16-31.

A 32-bit value created from 16 odd bits (register bits 1, 3, 5, 7, etc.) of register B and 16 bits of register C. The bits in register C form bits 0-15, while the 16 odd bits from register B form bits 16-31.

State machines for DRUs are shown in Table 1. It is initiated in state zero. It changes state every 32 cycles. During 32 cycles, a single no-overlap bit collects the AND of all dot advance bits for that 32 cycles (noOverlap = dot advance in cycle 0, noOverlap in cycles 1 through 31). = noOverlap AND dot advance).

Table 1 State Machines for DRUs

condition Nooverlap Print outputValid Explanation Next status 0 x B 0 Initiation status One One One B One Common non-overlap One One 0 B One A contains the initial overlap 2 2 x Even A Even B One A contains the second overlap and B contains the first overlap 3 3 x C, odd B One C contains the first overlap, B contains the second overlap

In FIG. 5, a margin unit (MU) receives the advance dot and advance line signals from a dither matrix access unit (DMAU) 48, the current page. It is responsible for switching to a general control signal based on the page margin of. It is also responsible for creating an end of page condition. The margin unit MU maintains a counter of dots and lines throughout the page. Both are set to zero at the beginning of the page. The dot counter is incremented by one each time the MU receives a dot advance signal from the DMAU. When the margin unit receives the line advance signal from the DMAU, the line counter is incremented and the dot counter is reset to zero. For each cycle, the current line and dot values are compared to the margin of the page, and the appropriate output dot advance, line advance and within margin signals are given based on these margins. The DMAU only contains the actual memory request for the HCU.

8 shows a line loader / format unit (LLFU). It receives dot information from the HCU, loads the dots for a given print line into the appropriate buffer storage (some chips, some external DRAM 34), and formats them in the order required for the printheads. do. The high-level block diagram of the LLFU in terms of external interface is shown in FIG. 9. Input 67 to the LLFU is one set of six 32-bit words and DataValid bits, all generated by the HCU. The output 68 is a set of 90 bits representing up to 15 printhead segments in six colors. Depending on how many colors are actually used in the printhead, all output bits may not be valid.

The physical arrangement of the firing nozzles on the printhead referred to above, ie the nozzles in two different offset rows, means that the odd and even dots of the same color are for two different lines. Even dots are for line L and odd dots are for line L-2. In addition, many lines exist between dots of one color and dots of another color. Since six color planes for the same dot position are computed at once by the HCU, it is necessary to delay the dot data for each color plane until the same dot is located under the appropriate color nozzle.

The size of each buffer line depends on the width of the printhead. Because a single print engine / controller (PEC) generates dots for up to 15 printhead segments, a single odd or even buffer line is therefore 15 sets of 640 dots for a total of 9600 bits (1200 bytes). . For example, the buffer required a total of almost 45 KBytes for six odd dots of color.

FIG. 10 shows a block diagram for color N OESplit (see Oesplit 70 in FIG. 9), and a block diagram for each of the two buffers (E and F) 71, 72 in FIG. And in FIG. 11. The buffer EF transfers data to the printhead interface PHI 32 of FIG. 3 by a dual buffer mechanism. Thus, buffers E and F have the same structure. While processing a line of dots, one of the two buffers is written while the other is read. The two buffers are logically swapped upon receipt of a line-sync signal from the PHI. Both buffers E and F, like the color 1 sub-buffer 73 shown in Fig. 11, consist of one sub-buffer per color and all six sub-buffers. Each sub-buffer is 2400 bytes in size, enough to accommodate 15 segments at 1280 dots per segment. The memory is accessed 32 bits at a time, so there are 600 addresses for each sub-buffer (which requires an address of 10 bits). All even dots are located before the odd dots in each color sub-buffer. If there is any unused space (for printing on less than 15 segments), it is located at the end of each color sub-buffer. The total amount of memory actually used in each sub-buffer is directly related to the number of segments actually addressed by the print engine / controller (PEC). For a 15 segment print head, there are 1200 bytes of even dots and 1200 bytes of odd dots following without unused space. The number of sub-buffers used beneficially is directly related to the number of colors used in the printhead. The maximum number of colors supported is six.

The address decoding circuitry for each buffer E and F is as if a single 32-bit access could all be made, in a given cycle, in six sub-buffers, all in six, or in one of six. . For a total of six output bits, only one bit of the 32 bits read from each color buffer is selected. The process is shown in FIG. An address of 15 bits causes a specific bit to be read out by an address of 10 bits used to select 32 bits, and an address of 5 bits selects 1 bit from 32 bits. Because all color sub-buffers share this logic, a single 15-bit address produces a total of 6 bits of output, 1 bit per color. Each sub-buffer 73-78 has its own WriteEnable line that allows a single 32-bit value to be written to a particular color buffer in a given cycle. Each WriteEnable is generated by the AND of a single WriteEnable input and the decoded form of ColorSelect. Since only one buffer actually clocks the data, 32 bits of data (DataIn) on line 79 are shared.

Address generation for reading from the buffers E and F is simple. Each cycle produces a one-bit address that is used to allocate six bits representing one bit per color for a particular segment. By adding 640 to the current bit address, it proceeds to the equivalent dot of the next segment. Since odd and even dots are separated in the buffer, add 640 (not 1280). This is repeated NumSegment times to retrieve data representing even dots and send the bits to the printhead interface (PHI). If NumSegment = 15, the number of bits is 90 (15 x 60 bits). The process is then repeated for odd dots. The entire even / odd bit generation process is repeated 640 times, increasing the starting address each time. Thus, all dot values are sent to the PHI in the order required by the printhead in 640 x 2 x Num Segment cycles. If NumSegment = 15, the number of cycles is 19,200. Note that six bits are generated (one bit for each color buffer) in a given read cycle, regardless of the number of colors actually used in the printhead.

In addition, a TWriteEnable control signal for writing to the 90-bit transfer register in FIG. 9 is generated. Since the line loader / format unit (LLFU) is initiated in front of the printhead interface PHI, the first value must be transmitted before the advance pulse from the PHI. It also prepares for the first advance pulse and produces the next value. The solution is to send the first value to the transfer register after a NumSegment cycle, then stop the NumSegments cycle and wait for an advance pulse to start the NumSegment cycle group. Once the first advance pulse arrives, the line loader / format unit LLFU is synchronized to the printhead interface PHI.

The readout process for a single dotline is shown in pseudocode below.

DoneFirst = FALSE                 

WantToXfer = FALSE

For DontlnSegment 0 = 0 to 1279

    lf (DontlnSegment0: bit0 == 0)

         CurrAdr = DontlnSegment0 (high bits) (puts in range 0 to 639)

    Endlf

    XfersRemaining = NumSegments

Do

    WantToXfer = (XfersRemaining == 0)

    TWriteEnable = (WantToXfer AND NOT DoneFirst) OR PHI: ADVANCE

    DoneFirst = DoneFirst OR TWriteEnable

    Stall = WantToXfer AND (NOT TWriteEnable)

    SWriteEnable = NOT (Stall)

    lf (SWriteEnable)

        Shift Register = Fetch 6 bit from EFSense [ReadBuffer]: CurrAdr

        CurrAdr = CurrAdr + 640

        XfersRemaining = XfersRemaining-1

    Endlf

   Until (TWriteEnable)

Endfor

Wait until BufferEF Write process has finished                 

EFSense = NOT (EFSense)

While the read process transfers data from E or F to the printhead interface PHI, the write process prepares the next dot-line in another buffer.

The data written to E or F are color 1 data generated by the half-toner / synthesizer unit (HCU) and color 2-6 data from the buffer D (supplied from the DRAM). Color 1 data is written each time the OutputValid flag of the HCU is set, and color 2-6 data is written from the register C for another time.

In Figure 9, the buffer (OE ₁ , 81) is a 32-bit register used to maintain the set generated by a single 32-dot HCU for adjacent color 1. The dots are contiguous on the page, but odd and even dots are printed at different times.

The buffers AB and 82 are double buffer mechanisms that delay odd dot data for color 1 by 2 dot lines. Thus, the buffers A and B have the same structure. While processing one line of dots, one of the two buffers is read and then written. The two buffers are logically swapped after all the dot lines have been processed. The single bit flag ABSense determines which of the two buffers to read and write.

The half toner / synthesizer unit (HCU) provides 32 bits of color 1 data whenever the output valid control flag is set, which is done every 32 cycles after the first flag is sent to the line. The 32 bits define a contiguous set of 32 dots for a single dot line, that is, 16 even dots (bits 0, 2, 4, etc.) and 16 odd dots (bits 1, 3, 5, etc.). The output valid control flag is used as the WriteEnable control for the OE ₁ register 81. HCU data is processed for every two output valid signals. The 16 even bits of the HCU color 1 data are combined with the 16 even bits of the register OE ₁ to produce 32 bits of even color 1 data. Likewise, 16 odd bits of HCU color 1 data are combined with 16 odd bits of register OE ₁ to produce 32 bits of odd color 1 data. Upon receiving the first output valid signal of the two groups, the buffer AB is read and odd data is sent to color 1 (73 in FIG. 11) in the buffer EF. Upon receiving the second output valid signal in the two groups, 32 bits of odd data are written to the same position in the previously read buffer AB, and 32 bits of even data are written to color 1 in the buffer EF. .

The HCU provides 32 bits of data per color plane whenever the Output valid control flag is set. Every 32 cycles except during a specific start time. The 32 bits define a contiguous set of 32 dots for a single dot line, that is, 16 even dots (bits 0, 2, 4, etc.) and 16 odd dots (bits 1, 3, 5).

Buffers OE ₁ 83 in FIG. 10 are used to store a single 32-bit value for color 1, while buffers OE ₂ through OE ₆ are each used to store a single 32-bit value for colors 2 to 6. . The data for color 1 is divided into 32 bits representing color 1 odd dots and 32 bits representing color 1 even dots, every 64 cycles (once for every second output valid flag), and the remaining color planes are also even and odd. It is divided into dots.

However, instead of writing directly to the buffer EF, the dot data is delayed by the number of lines and written to the DRAM via the buffer CD (84 in FIG. 9). The dot for a given line is written to the DRAM, and the dot for the preceding line is read from the DRAM and written to the buffers EF, 71, 72. This process must be performed by interleaving in the process of writing color 1 to the buffer EF.

Each time an output valid flag is received from the HCU on a line (85 in FIG. 10), 32 bits of color N data are stored in a buffer (OE _N , 83). Once every two output valid flags, the combined 64-bit value is written to color buffer N86. This happens simultaneously for all color planes 2-6. Color buffer N 86 contains 40 sets of 64 bits (320 bytes), allowing dots for two complete segments to be stored. This allows the complete segment creation time (20 x 64 = 1280 cycles) for previous segment data (both odd and even) to be written to the DRAM. Generating an address for writing is simple. The ColorNWriteEnable signal on line 87 is given for every second output valid flag. The address starts at zero and increments every second output valid flag up to 39. Instead of proceeding to 40, the address is reset to zero, thus providing a double buffering structure. This is valid unless a read occurs during the output valid flag, and previous segment data can be written to the DRAM in the time it takes to generate single segment data. The process is shown in the pseudocode below.

adr = 0

firstEncountered = 0

While (NOT AdvanceLine)

   lf (HCU_OutputValid) AND (firstEncountered)

         ColorNWriteEnable = TRUE

         ColorNAdr = adr

         lf (adr == 39)

             adr = 0

          Else

             adr = adr + 1

          Endlf

      Else

         ColorNWriteEnable = FALSE

      Endlf

      lf (HCU_OutputValid)

          firstEncountered = NOT (firstEncountered)

      Endlf                 

EndWhile

Address generation for reading is more demanding because it depends on the timing for DRAM access (both read and write), buffer (EF) access, and color 1 generation. It will be described in more detail below.

Address generation for buffers C, D, E, F and color N all depend on the timing of the DRAM access and should not interfere with color 1 processing with respect to buffers E and F. The basic principle is that data for a single segment of color N (odd or even dots) is transferred from the DRAM to the buffer EF via the buffer CD. Once data is read from the DRAM, the dots are replaced according to the value of ColorBufferN. For each color in odd and even dots. After the full segment amount of dots has accumulated (20 sets of 64 cycles), the process starts again. Once data for all segments in a given print line is transferred from or to the DRAM, the current address for the color DRAM buffer is increased, so that the appropriate number of lines until specific data for the color line is read from the DRAM. Will be In this regard, the DRAM operates in the form of a FIFO. As a result, the color N (odd or even) is read from the DRAM into the buffer D, and at the same time copies the color N (same odd / even detection) into the buffer C. Copying data to buffer C takes 20 or 21 cycles depending on whether the valid output flag occurs during 20 transfers. Once both tasks are completed (usually a slower DRAM access), the second part of the process is initiated. The data in the buffer C is written to the DRAM (at the same position as the read position), and the data of the buffer D is copied to the buffer EF (and since the color 1 data is being transferred, the output valid flag Is set, there is no color N data transferred to the buffer EF). Once both tasks are completed, the same process takes place for another detection of color N (even or odd) and then the same process takes place for each detection of the remaining color. The full duplex process occurs 10 times. The address for each current line present in the DRAM is updated to start the process of the next line.

The address generation process can be considered as 10 sets of NumSegment quantities consisting of a 20x32 bit read followed by a 20x32 bit write, which is shown in the pseudocode below.

EFStartAdr = 0

Do NumSegments times:

 For CurrColor = 0 to MaxHalfColors

DRAMStartAddress = ColorCurrAdr [CurrColor]

     While reading 640 bits from DRAMStartAddress into D (> = 20 cycles)

       ColorNAdr = 0

       While (ColorNAdr! = 20)

          lf (NOT HCU_OutputValid)

             Transfer ColorNBuffer [ColorNAdr ｜ CurrColor_bit0] to C [ColorNAdr]

       ColorNAdr = ColorNAdr + 1                 

    Endlf

  EndWhile

EndWhile-wait until read has finished

 While writing 640 bits from C into DRAMStartAddress (> = 20 cycles)

    ColorNAdr = 0

    EFAdr = EFStartAdr

    While (ColorNAdr! = 20)

      lf (NOT HCU_OutputValid)

        Transfer D [ColorNAdr] to EF [CurrColor ｜ EFAdr]

        lf ((ColorNAdr == 19) AND (CurrColor == NumHalfColors))

            EFStartAdr = EFAdr + 1

        ELSE

            EFAdr = EFAdr + 1

        Endlf

        ColorNAdr = ColorNAdr + 1

     Endlf

   EndWhile

    EndWhile-wait until write has finished

    lf (DRAMStartAddress == DRAMMaxVal)                 

colorCurrAdr [currColor] = round up DRAMStartAddress to next 1KByte page

    Else

     ColorCurrAdr [currColor] = DRAMStartAddress + 640 bits

Endlf

       lf (Segment == maxSegments)

   lf (ColorCurrRow [CurrColor] == ColorMaxRow [CurrColor])

      ColorCurrRow [currColor] == ColorStartRow [currColor]

      ColorCurrAdr [currColor] == ColorStartAdr [currColor]

   Else

      ColorStartRow [currColor] = ColorCurrRow [currColor] +1

   Endlf

     Endlf

  Endfor

Enddo

Wait until next Advance signal from PHI

Note that the MaxHalfColors register is one less than the number of colors in odd and even color conditions, which are handled separately, but do not include color 1. For example, under the conditions of a standard 6 color printing system, 10 is present (colors 2-6 at odd and even), so MaxHalfColor should be set to 9.                 

The line loader / format unit (LLFU) requires 2 NumSegment cycles to prepare the first 180 bits of data for the printhead interface (PHI). As a result, during this time period after the LLFU is initiated, the printhead must be started and a first LineSync pulse should occur. This allows the initial Transfer value to be valid and prepares the next 90-bit value to be loaded into the transfer register.

The printhead interface (PHI) is a means by which the processor loads dots for printing into the printhead and controls the actual dot printing process. It takes input from LLFU and outputs data to the printhead. PHI can handle a variety of printhead lengths and formats. The internal structure of the PHI may take into account up to six colors, eight segments and up to two segment groups per transmission. This is enough for a 15-segment (8.5-inch) printer capable of printing A4 / Letter sizes at full bleed.

Characterization vectors of the combined printheads can be read via a serial interface. The characterization vector may include dead nozzle information as well as relative segment alignment data. Each printhead segment can be queried through its low speed serial bus, returning the segment's characterization vector. Characterization vectors from the plurality of printheads can be combined to create a nozzle defect list for the entire printhead, allowing the print engine to compensate for defective nozzles during printing. If the number of defective nozzles is small, compensation may result in indistinguishable from a printhead without a defective nozzle.

Each segment has 384 bits for the characterization vector and consists of:

64-bit flag and printhead segment information, including the number of colors and serial number represented in the segment.

16-bit alignment data associated with the preceding segment (0 = first segment)

Variable lengthed defective nozzle list using all remaining bits

The defective nozzle list is variable in length, and each set of defective nozzles has the following structure.

5-bit count (0 = end-of-list)

3 bit color

Count x 11 bits, 1 entry per defective nozzle

Under normal conditions, the printhead segment has connections as defined in Table 12. Note that some connections are replicated when there are multiple colors.

Table 12 Printhead Segment Connections

   designation Repetition of Multi-Color Segments           function   D [n]            Yes  N channels of image data   Sclk           no  Serial Data Transfer Clock   NPSync           no  Nozzle Phase Synchronization   PLL           no  Phase Locked Loop Clock   Ten           no  Parallel transfer enable   Reset           no  Control Reset   SCI           no I ² C serial clock for control    SD           no I ² C serial data for control   CCEn [n]           no  Control chip enable [n]    GND           no  Analog ground    Sense           no  Analog Sense Output    V-            Yes  Negative drive power    V +            Yes    Plus driving power    Vss            Yes  Negative logic power    Vdd            Yes    Plus logic power

The 21 mm long printhead segment may have 64 bond pads on a 300 μm center. 24 of these bond pads supply V- power to the driver and 20 supply V + power. The remaining 20 connections are CMOS logical power, signal and data connections. Table 13 details these connections.

Table 13.6 Color Segment Connections

   # designation            function 1-6 V- Negative drive power    7 Vss Negative logic power    8 D1 [n] Channel 1 [n] of image data (fixed solution in 6-channel printheads)    9 D2 [n] Channel 2 [n] of the image data (infrared on a 6-channel printhead)   10 Sclk Serial Data Transfer Clock   11 Vdd Plus logic power 12-16 V + Plus driving power 17-22 V- Negative drive power   23 NPSync Nozzle Phase Synchronization   24 D3 [n] Channel 3 [n] of image data (black on 6-channel printhead)   25 D4 [n] Channel 4 [n] of image data (yellow on 6-channel printheads)   26 PLL Phase Locked Loop Clock   27 TEn Parallel transfer enable 28-32 V + Plus driving power 33-38 V- Negative drive power   39 Reset Control reset   40 D5 [n] Channel 5 [n] of image data (magneta on 6-channel printheads)   41 D6 [n] Channel 6 [n] of image data (cyan on 6-channel printhead)   42 SCI I ² C serial clock for control   43 SD I ² C serial data for control 44-48 V + Plus driving power 49-54 V- Negative drive power   55 Vdd Plus logic power   56 Gnd Analog ground   57 CCEn [n] Control chip enable [n]   58 Vss Negative logic power   59 Sense Analog sense output 60-64 V + Plus driving power

Multi-segment printheads ideally consist of many identical printhead segments. These are usually manufactured together in 21 mm segments, or installed together after manufacture, to produce a printhead of the desired length. Segments can be installed to overlap as desired, taking into account smooth transitions between segments. Each 21mm inch segment prints 1600 dpi two-level dots on different parts of the page to produce the final image. Each segment produces a final image of 1280 dots, but each dot is represented by a combination of color inks. For example, 15 segments can be combined side by side to create a 12-inch printhead. Each segment may be considered to have a lead-in area, a central area and a lead-out area. The lead-out of one segment corresponds to the lead-in of the next segment.

12 shows two overlapping segments 106, 107, and three regions of the segment are shown. Note that the lead-out area 108 of the segment S 110 corresponds to the lead-in area 109 of the segment S + 1 107. The central area of the segment is an area (110 of 106 and 111 of 107) having no overlap at all. Although the segments are vertically staggered in the figure, the segments are staggered at some angle, aligned in the vertical dimension.

Assume that the printhead consists of many segments as above. For the purpose of data loading, assume that the segments are grouped into G segment groups, with L segments in the largest segment group. Assume there are C colors in the printhead. Assume that a firing mechanism for the printhead fires all segments simultaneously, and only one segment at a time places feedback information on a common tri-state bus. Assuming all of this, Table 15 shows the external connections available from the printhead.

Table 15. Printhead Connections

 designation  #pin  Explanation  Dn  CL Input to C Shift Register from Segment 0 to L-1  Sclk  G A pulse on SClk [N] (shift register clock N) loads the current value in segment group N into the L segment on the Dn line.  NPSync  One Pulse on NPSync starts printing lines for all segments  PLL  One Phase-Locked Loop Clock to Generate Timing Signals from the Printhead  Ten  One Parallel transfer of data from shift register to internal  Reset  One Control reset  SCI  One I ² C serial clock for control  SD  One I ² C serial data for control  CCEn  G Pulse on CCEn N ANDed with data on D1 [n] selects sense line for segment n in segment group N  Sense  One Analog sense output  Gnd  One Analog sense ground  V- Depends on the number of colors Negative drive power  V + Plus driving power  Vss Negative logic power  Vdd Plus logic power

Referring to FIG. 5, the HCU provides a means for dithering two different dither matrices selected by the dither matrix selection bitmap. Dither Matrix Access Unit (DMAU) 48 provides the appropriate dither value for each cycle. The DMAU also handles a plurality of overlapping message printhead segments. The purpose of the DMAU is simply to provide the appropriate 8-bit dither value for proper output dot location in the printhead.

If the entire Memjet printhead is physically monolithic, a single dither matrix (eg 64 × 64) is sufficient. However, the memjet printhead consists of a plurality of overlapping segments. Segment overlap allows for a smooth transition from one memjet segment to another, instead of sharp edges that may result in visible artifacts. Also, as a result of placing the segments, they do not necessarily have to be completely dot aligned. A typical dither matrix would not be able to handle this conversion and sub-dot alignment between segments. The solution for printing by a print engine / controller (PEC) is to use a characterization vector from the memjet printhead and construct a set of printhead specific dither matrices. Each segment may be considered to have a lead-in area, a center area and a lead-out area. The lead-out of one segment corresponds to the next lead-in. The central area of the segment is an area having no overlap at all.

In FIG. 12 two overlapping segments 106, 107 and three regions of the segments are illustrated. Note that the lead-out area 108 of the segment S corresponds to the lead-in area 109 of the segment S + 1. For any number of printhead segments, it can be considered that the center area has the same dither matrix, but the lead-out of segment S and the lead-in of segment S + 1 are in alignment between the two segments. Can be paired accordingly. If multiple print engines / controllers (PECs) can address the same page, one corresponding PEC can address a particular set of segments while another PEC can address the next set of segments. As a result, the lead-in area of the first segment for the PEC substantially corresponds to the lead-out of the last segment from another PEC.

The overall purpose of the dither matrix is to provide intensity levels and dot-gain characteristics to match a conventional dither cell for each luminance level for each point over each overlap region. A set of dither matrices is defined for the segments addressed by this print engine / controller (PEC). The set of dither matrices is collectively called a multi-segment dither matrix.

The center region dither matrix is a general dither matrix and may be the same for all segment segments (but the dither matrix values used for the first dot in the center region of a given dot line are aligned between the segment and the one before it). May not be the location expected by).

The lead-in / lead-out dither matrix is for overlap regions of segment pairs. Lead-in and lead-out for a whole set of segments managed by PEC are also required. The width of the lead-in / lead-out matrix is the total number of dots in both segments of the overlap area. The number is expected to be between 32 and 48 (corresponding to an overlap width of 16 to 24). The lead-in / lead-out dither matrix for one segment and the lead-out segment for the corresponding adjacent segment take into account sub-dot alignment and position in the center region dither matrix when the overlap region begins and ends. Are designed to be combined with each other.

The lead-in dither matrix is for the first segment and the lead-out dither matrix is for the last segment. These will correspond to similar matrices in the set of other segments managed by the PEC.

Each segment also specifies a horizontal offset within the center region dither matrix, for the first dot of that segment. This allows compensation for misalignment up to two dots caused by overlapping segments. This also gives the dither matrix generation software more flexibility, providing any joining point at the end of the lead-out component of the lead-in / lead-out dither matrix.

The multi-segment dither matrix consists of lines. The total number of lines is equal to the height of the dither matrix. Each line is loaded in a double buffer from external DRAM into local DMAU memory. While one dot line is generated with reference to the current line of the multi-segment dither matrix, the next line of the multi-segment dither matrix is loaded. The dither matrix line buffer is replaced when receiving an advance line signal from a half toner / synthesizer unit (HCU) state machine.

13 shows the synthesis of lines from the multi-segment dither matrix.

The size of a single line of the multi-segment dither matrix depends on the overlap size and the number of segments. Given 64 center region dither matrix widths, 32 dot overlap size and 15 segments, there are a total of 64 + 32 + 32 + (14 × (32 + 32)) entries, each entry being 8 bits = 1024 bytes.

DRAM storage requests are 64 lines (the height of the dither matrix) at 1 Kbyte per line for a total of 64 KBytes. The DMAU loads one of these lines at each output line of the DRAM. At a maximum print speed of 30,000 lines / second, this is approximately equal to 30MB / sec.

Indeed, DMAU supports two of these multi-segment dither matrices selected by the dither matrix select bit. If the Matrix2valid 1-bit register is set, the second dither matrix is used. DRAM storage requests are therefore 128 KBytes, and DRAM access requires a total bandwidth of 60MB / sec at maximum printing speed. Thus, the DMAU contains four line buffers at 1024 bytes per buffer and 15 offset registers to be used as the initial entry (one entry for each segment) in the center region dither matrix.

The address generation process is described in the pseudo code below.

DblBufferSelect = 0

MatrixLineStartAddress = 0 (refers to 64 KByte-aligned address of start of Matrix1)

Load Matrix 1 address pointed to by MatrixLineStartAddress

lf (Matrix2Valid)

Load Matrix 2, address pointed to by MatrixLineStartAddress + 64KBytes

Endlf

Do until end-of-page

currAdr = 64

lineAdvance = 0

dotAdvance = 0

dot = 1

segment = 1

While (NOT lineAdvance)

        CalculateEntry                 

EndWhile

DblBufferSelect = NOT DblBufferSelect

MatrixLineStartAddress = (MatrixLineStartAddress + 1) AND 63

Load Matrix 1 address pointed to by MatrixLineStartAddress

Load Matrix 2, address pointed to by MatrixLineStartAddress + 64KBytes

Enddo

Where an entry is produced is a single cycle process described by the following pseudocode: If the Matrix2Valid register is empty, the first dither matrix is always used, without considering any value from the dither matrix select bitmap.

Output matrix value read from:

                DblBufferSelect, DitherMatrixSelect AND Matrix2Valid, CurrAdr

Output dotAdvance = NOT (((dot <32) AND (segment NOT == 0) AND (dot ₀ == 0) OR ((dot> 1248)

AND (segment NOT = numSegments)) AND (dot ₀ == 0)

Output lineAdvance = ((segment == numSegments) AND (dot == 1280)

lf ((dot <32) OR (dot> 1248))

         CurrAdr = CurrAdr + 1

Else if (dot == 1248)

         CurrAdr = NextOverlapAdr                 

Else lf (dot == 32)

          NextOverlapAdr = CurrAdr

          CurrAdr = CentralArealFirstDotDitherOffset [segment]

Else

          CurrAdr = (CurrAdr + 1) AND63

Endlf

lf (dot == 1280)

          dot = 1

          segment = segment + 1

Else

          dot = dot + 1

Endlf

It should be noted that the dot and segment counters are used to count dots and only correspond to the actual segment / dot combination during the non-overlap area, lead-in and lead-out area of the last segment. During the overlap period, the replacement dots correspond to segment S and segment S + 1. dotAdvance is therefore given only every second dot during this period.

Each printhead segment can be queried over its slow serial bus and send back the segment's characterization vector. Characterization vectors from the plurality of printheads can be combined to construct a nozzle defect list for the entire printhead, and the print engine can compensate for defective nozzles during printing. As long as the number of defective nozzles is small, compensation can result in indistinguishable from a printhead without a defective nozzle.

Each segment has 384 bits for the characterization vector and is constructed as follows.

64-bit flag and printhead segment information, including the serial number and the number of colors represented in the segment.

16-bit alignment data related to the preceding segment (0 = first segment)

Variable length defective nozzles using all remaining bits

The defective nozzle list is variable in length, and each set of defective nozzles has the following structure.

5-bit count (0 = end-of-list)

3 bit color

Count x 11 bits, 1 entry per defective nozzle

The fade in / fade out dither matrix is not just a lead in and a lead out. When they are applied according to any unaligned overlap, it is defined together that there is a constant dot gain on the overlap area. The two segments may not be dot aligned with each other.

Misalignment between segments is important. Where the two segments are not perfectly dot aligned, the dots on the first segment are not perfectly aligned with the dots on the second segment. Two dots on the second segment may overlap one dot on the first segment. If the dot on the first segment is printed with the dot on the second segment, there will be a huge dot formed from the two combinations. If the dots on the first segment are printed and none of the overlapping dots on the second segment are printed, the result is a half dot space. The first case will make a dark strip down the page, and the second case will make a white strip down the page. Both results are undesirable.

The solution to the above misalignment problem is to have a dither cell that considers misalignment, so that the dot gain in the overlap region is generally constant so that there are no dark areas or strips under the entire page. Since there are two segments, two dither cells are needed. One may be considered fade-out and the other as fade-in. They must be used in combination with each other to produce a constant dot gain. It is clear that dither cell pairs are different if the misalignment is different. The overlap caused by half dot misalignment is different from the misalignment caused by quarter dot misalignment. Different dither cell pairs are required for each misalignment. Knowing where in the common dither cell there is an onset of overlap, a better dither cell pair can be generated.

Because of the misalignment, it is necessary to know whether to use the expected position (if there is a complete dot alignment) within the common dither cell when it reaches the end of the overlap area or whether it is in another column of the dither cell. Thus, there is an offset value that allows specifying which part of the common dither cell is attached to the end of the overlap pair of a particular segment.

Thus segment misalignment is used for two purposes. The first is to create a dither cell pair for the overlap area. Generation of the dither cell pair should be done by concatenating the known positions in the common dither cell to the selected column of the dither cell. The selected column will be the column expected in the case of a perfectly dot-aligned segment, and the adjacent column in the case of an unaligned segment. Thus, unalignment is used to determine what the offset is in the common dither cell. The extreme case is for each segment overlap area with a pair of different pairs of dither matrices for each overlap, taking into account misalignment and position within the common dither cell. Generation of the dither cell may be done once for each printhead unaligned pair. It can be done once for every printhead. For example, generating an excessive dither cell pair list for all misalignments up to the 100th dot misalignment is trivial. Doing so will require the generation of 100 × 64 dither cell pairs and the generation of 100 × 64 offset values for a total of 6400 sets. Given an overlap of 32 dots and a height of 64 dither cells, for a total of 12.5 MBytes, 4 KBytes per dither cell pair is required, which can be easily stored on the printer driver installation CD-ROM (or the like). During installation of the print driver, the correct dither cells are selected based on misalignment in the connected printheads and require a total of 64 KBytes for the 15 segment printheads. The important point here is that the creation of the dither cell only needs to be done once. The actual 6400 dither cell (assuming the alignment is 1/100 of the dot accuracy) can be easily generated by the simulated annealing dither cell generation technique. A good feature would be a simple dot-gain calculation. The purpose of the simulated anneal will be to minimize the dot gain difference compared to standard dither cells.

Throughout this specification, the present invention has not been limited to any particular embodiment or combination of features, but the purpose of the present invention has been described in the preferred embodiment of the present invention. Those skilled in the art will appreciate from the embodiments herein that various modifications may be made without departing from the scope of the invention.

Claims (9)

A method of preparing print data for a multi-segment printhead, comprising: A lead-in dither matrix associated with a lead-in overlap portion for a multi-segment printhead composed of a plurality of printhead chips with overlapped ends; A lead-out dither matrix associated with the lead-out overlap portion; Setting a dither matrix set consisting of a common dither matrix associated with a central portion of the printhead chip, Receiving print data; Accessing the set of dither matrices and applying dither to the received data when the received data is synthesized to maintain a nearly constant dot gain in the resulting image over the overlap portion. How to prepare your data. The method of claim 1, The lead-in dither value sets the fade-in of one segment, the lead-out dither value sets the fade-out of the preceding segment, and a combination of the two A method of preparing print data for a multi-segment printhead, characterized by providing a substantially constant dot gain in this overlap portion. The method of claim 1, In each of the two overlapping segments, the overlap is characterized in a condition of misalignment, wherein the misalignment is used to generate an offset leading to the common dither matrix. To prepare print data for printing. The method of claim 3, wherein Unaligned information is obtained from a stored characterization vector for each printhead segment. The method of claim 4, wherein And the characterization vectors from the plurality of segments of the printhead are combined to form a nozzle defect list for the entire printhead. As a print having a multi-segment printhead, An interface for receiving print data; A compositor for synthesizing the received print data; A printhead interface for placing the synthesized print data from the synthesizer into a multi-segment printhead, The synthesizer includes a dither matrix access unit representing a dither matrix used to synthesize print data so as to maintain a nearly constant dot gain in the resulting image, The dither matrix access unit addressing a dither matrix, which is a composite of a set of dither matrices for a multi-segment printhead having overlapping segments at an end, The set includes a lead-in dither matrix; A lead-out dither matrix; A printer having multi-segment print data organized in a center area dither matrix. The method of claim 6, The lead-in dither value sets the fade-in value of one segment, the lead-out dither value sets the fade-out of the preceding segment, and the two combinations provide nearly constant dot-gain for the overlap portion. And multi-segment print data. The method of claim 6, In each set of two overlapping segments, there is an overlap characterized in consideration of the misalignment, the misalignment being used to generate an offset leading to the center region dither matrix. Printer with print data. The method of claim 7, wherein Wherein the misalignment information is obtained from a characterization vector stored in each printhead segment, and they are combined to construct a nozzle defect list for the entire printhead.

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