KR100664334B1 - Data processing arrangement and memory system - Google Patents

Abstract

The data processing apparatus 1 includes a first processor PROC1 that provides a continuous set of input data, a second processor PROC2 that receives a continuous set of output data, and a plurality of memory circuits that store input and output data. And a memory system 2 having (MEM). According to the invention, the data processing apparatus further comprises a main controller MCP for setting up the memory system by a control command CC associated with the input data set and the output data set. This control command is received by the control unit (MCU) to the memory system. When data Di is provided from the input data set by the first processor, the control unit selects a first memory circuit based on a control command and generates write data AD_W in the first memory circuit. do. In the same way, when data Do is requested from the output data set by the second processor, the control unit selects the second memory circuit based on the control command, and read-out address AD_R in the second memory circuit. Will occur). Thus, there is no need for a processor to provide an address when requesting or transmitting data, thereby achieving a simple data processing apparatus.

Description

DATA PROCESSING ARRANGEMENT AND MEMORY SYSTEM}

The present invention provides a first processor for providing a continuous set of input data, a second processor for receiving a continuous set of output data, and a plurality of memory circuits for receiving a continuous set of input data and providing a continuous set of output data. It relates to a data processing apparatus including a memory system having a.

The invention also relates to a memory system capable of receiving data and providing the data to several processors and a method for processing data in such a data processing apparatus. The invention is particularly suitable for multimedia related applications involving data streams.

U. S. Patent No. 4,930, 066 includes a plurality of data input / output ports for providing page addresses, a plurality of memory banks for storing data pages, and a switching network for cycling connections between the data input / output ports and memory banks. Start the memory system. The address is sent to the memory system in association with the data. Therefore, the disclosed system includes an interface for receiving data and associated addresses for each input / output port. This causes a delay in data storage. Moreover, this interface is complex in hardware. In addition, the memory bank is only accessible for either read or write, and cannot be accessed for both. Memory access conflicts can occur when a memory bank is selected for both write data reception and read data provision. The configuration disclosed in the above cited document is prone to collisions when two different ports are required to access two pages located in the same bank.

It is an object of the present invention to provide a data processing device as described above at the outset much more simply.

According to the invention, such a data processing apparatus comprises a master controller for setting up a memory system by a control command associated with an input data set and an output data set, the memory system comprising: a first processor; Selects a first memory circuit based on a control command to generate a write address to the first memory circuit when the second processor provides the data of the input data set, and when the second processor requests data of the output data set, And a control unit for selecting a second memory circuit based on the second memory circuit and generating a read address in the second memory circuit.

The control commands associated with the input data set and the output data set set up the memory system to autonomously generate addresses for these two sets of data. The control unit of the memory system internally calculates addresses of such input and output data, and selects a memory circuit for each data. Thus, there is no need for the processor to send an address for providing or receiving data. In fact, the processor does not need to know anything about the internal workings of the memory system when requesting or providing a data set. As a result, the communication protocols that can exist between a processor and such a memory system and the resulting hardware implementations are significantly simplified compared to the prior art.

Another advantage of the present invention relates to the following aspects. In the data processing apparatus according to the present invention, the memory system may receive input data from the first processor, and at the same time, the memory system may provide output data to the second processor. The control unit made it possible to combat access conflicts by selecting two different memory circuits for input and output data. This prevents the destruction of the stored data. The memory circuit may also be of a type that allows one of reading and writing at a given moment but not both. Such memory circuits are relatively inexpensive, and thus cost efficiency is another advantage of the present invention.

Read and write addresses may be generated in different ways. One way to get this address is to put all addresses associated with the input data set and the output data set into a lookup table. However, these lookup tables are complex to implement and require a large chip area.

A preferred embodiment of the invention as claimed in claim 2 comprises a read counter and a write counter for generating read and write addresses that respectively determine where data is to be stored or fetched. These two counters are simply implemented means to provide a read address and a write address.

There are several ways for the memory system to know when the first processor provides data in the input data set and when the second processor requires data in the output data set. One solution is to count the two counters described above, incrementing or decrementing by one unit according to the clock pulses of the clock signal. This means that the input and output data are received or provided at a fixed rate determined by the clock signal.

Another embodiment of the invention claimed in claim 3 receives a read signal and a write signal from a processor. The processor sends a read or write signal to the memory system when requesting new output data or providing new input data. These signals allow the processor to asynchronously receive or provide data. In the data processing apparatus of this embodiment, two processors can access the memory system at their own speed. This is particularly advantageous if the various processors have their own processing speed and they cannot receive or provide data at the same rate. Compared to the solution in which data is transmitted in accordance with the clock signal, the embodiment claimed in claim 3 provides the main advantage of greater flexibility.

The invention also relates to a memory system comprising a plurality of memory circuits for receiving a continuous set of input data and providing a continuous set of output data, the memory system further comprising a control associated with the input data set and the output data set. A control unit programmable by a command, and based on these control commands, when data is received from an input data set, a first memory circuit is selected so that a write address is generated in the first memory circuit, while an output data set When data is provided from the second memory circuit is selected to generate a read address in the second memory circuit. More generally, the present invention also relates to a data processing method performed in the claimed data processing apparatus.

Specific aspects of the present invention will be described with reference to the embodiments described below in connection with the accompanying drawings.

1 is a block diagram of an embodiment of a data processing apparatus according to the present invention.

2 is a block diagram of a preferred embodiment of a data processing apparatus according to the present invention.

3 is a block diagram of a memory system illustrating internal connections between various components.

4 shows an 8-bit word MC_W.

The data processing apparatus 1 according to the invention is shown in FIG. 1. The apparatus comprises a memory system 2, a first processor PROC1 for providing a continuous set of input data to the memory system 2, and a second processor PROC2 for receiving a continuous set of output data from the memory system 2. PROC1 provides data Di through crossbar 6 and input port 3 of memory system 2. PROC2 receives data Do via crossbar 5 and output port 4 of memory system 2. The memory system 2 includes a memory control unit MCU # memory block MB. Data is physically stored in this memory block MB, and is composed of arbitrary (in this case five) independent memory circuits MEM1, MEM2, MEM3, MEM4, and MEM5. These memory circuits are, for example, static random access memory (SRAM) in a 256 word configuration of 10 bits, in a preferred embodiment of the present invention. When data Di is written here, each memory circuit MEM1, ..., MEM5 is accessible through each input port I1, I2, I3, I4, I5, and when data Do is read, each memory The circuits MEM1, ..., MEM5 are accessible through their respective output ports O1, O2, O3, O4 and O5.

The data processing apparatus 1 also comprises a main controller MCP, which sends a control command CC to the control unit MCU via the control bus CB. This control command CC is associated with the input data set received from PROC1 for writing to the memory block MB. This control command is also associated with the output data set required by PROC2, which is fetched from the memory block MB. The command CC is sent to the control unit MCU before PROC1 and PROC2 process the input data set and output data set, respectively. The command CC operates the setup of the control unit MCU. The main function of the control unit MCU of the memory system 2 is to manage storing data in the memory block MB. In response to the control command, the unit MCU generates a command set COM to be transmitted to the memory block MB, which indicates the position at which data Do is fetched from the MB or the position at which data Di is inserted into the MB. Therefore, when data Di is provided to port 3 by PROC1 for writing, the MCU firstly inputs the corresponding input ports I1, I2, The set COM indicated by activating I3, I4 and I5 is transferred to the memory system 2. The COM set also includes a write address which is a position where data is written in the selected memory circuit. Similarly, when data Do is requested by PROC2 at output port 4, the MCU indicates to the memory block MB which memory circuit MEM has been selected and contains a read address which is the location in the memory circuit to which the requested data is to be fetched. Send the set COM.

Note that write and read operations cannot be performed simultaneously in the same memory circuit. In addition, these two operations are not allowed at the same time, in order not to destroy data required simultaneously for reading and writing. If the same memory circuit is selected for simultaneous write and read, the read operation is inactivated and the write operation is performed as usual. Simultaneous write and read operations can only be performed in two different memory circuits. As a result, the access conflict is eliminated in the data processing apparatus according to the present invention. In the following description, a detailed description will be given of how an access conflict that may occur is detected and prevented.

Memory blocks may be used in conjunction with several processors. However, two processors cannot simultaneously access the memory system 2 for writing. However, several units may simultaneously access the memory block MB to read the same data set via (4). As described herein, memory blocks are often used as buffer memory between two processors in a processing chain.

In a preferred embodiment of the present invention, the control unit MCU shown in FIG. 2 sends a command set COM consisting of four signals MS, R / W, AD_W, AD_R. Moreover, in this preferred embodiment, the control unit MCU comprises a controller CTRL which transmits the signal MS to the memory block MB after setup by the control command CC when data is read or written. This signal MS allows one of the memory circuits MEM1, MEM2, MEM3, MEM4, and MEM5 to be selected. The controller CTRL also supplies an R / W signal to the memory block MB, which indicates whether the selected memory circuit is required for reading or for writing, and whether the memory circuit has been selected for reading or for writing. This allows the activation of its input ports I1, ..., I5 or its output ports O1, ..., O5. For example, this signal may be 1 if the selected memory circuit is needed for writing, while 0 may be required for reading.

The memory control unit MCU also includes two internal counters CNT_R and CNT_W that can be externally loaded. The value of the counter CNT_W is changed in response to the signal NXT_W received through the write input port 7 of the control unit MCU, and provides a signal AD_W which is a read address of data Di to be written to the memory circuit selected by the controller CTRL. Thus, when processor PROC1 provides data Di, this PROC1 also transmits signal NXT_W via crossbar 6 and write input port 7. The data Di is written to the position indicated by AD_W in the memory circuit selected by the controller CTRL. The counter CNT_W is then incremented in response to NXT_W to prepare to provide a new address AD_W indicating the next available location for the next data Di provided by PROC1. Therefore, the signal NXT_W allows to increase the address in the selected memory circuit for the continuous asynchronous writing of data Di. In this embodiment of the present invention the counter CNT_W is incremented after data is written to the selected memory circuit. CNT_W may be reduced in response to NXT_W before data is written.

Similarly, when PROC2 requests new data D0 from memory block MB, PROC2 sends signal NXT_R to counter CNT_R via crossbar 5 and read input port 8 of control unit MCU. In response to the signal NXT_R, the counter CNT_R increments and provides the read address AD_R in MB. This address AD_R is the address of data D0 requested by PROC2 in the memory circuit selected for reading by the controller CTRL. The counter CNT_R is incremented before data is taken from the selected memory circuit. In one embodiment of the present invention, signals NXT_W and NXT_R are provided at each clock input of the counter, and therefore they act as asynchronous clocks respectively for counters CNT_W and CNT_R. The main advantage of this preferred embodiment is the asynchronous operation of the data processing apparatus 1 which allows the memory system to be accessed by processors of different processing speeds. As a possible implementation of the invention, it is also possible for two counters to be connected to one clock signal, for example to provide read and write addresses at each rising edge of the clock signal. This implementation requires synchronous operation of the processor, which must receive and provide data at a fixed frequency of the clock.

One improved embodiment of the present invention is shown in FIG. 3. This figure shows a memory control unit MCU comprising two counters CNT_W, CNT_R in FIG. In this improved embodiment of the present invention, the controller CTRL described in FIG. 2 consists of two independent controllers CTRL_W and CTRL_R, and an independent unit COMP that detects and resolves access conflicts that may occur within the memory system 2. . The control unit MCU consists of four registers REG1, REG2, REG3, and REG4. This register receives the control command set CC from the main controller MCP. This set CC consists of four main command words Strt_W, MC_W, MC_R and Strt_R in this case. Commands MC_W and MC_R are stored in REG2 and REG3, respectively, in response to the load signal ld_conf sent to the control bus CB by the main controller MCP. Strt_W and Strt_R are loaded into REG1 and REG4 respectively in response to ld signals from controllers CTRL_W and CTR_R. The contents of REG1 are transmitted to the counter CNT_W via the connection line 10. The contents of REG2 are transmitted to the controller CTRL_W via the connection line 11. The contents of REG3 are transmitted to the controller CTRL_R via the connection line 12. The contents of REG4 are transmitted to the counter CNT_R via the connection line 13. The ld_conf signal sent to the control bus CB activates the setup of the memory control unit MCU. In response to this signal ld_conf, the contents of registers REG2 and REG3 are updated with a new control command CC received on the control bus CB.

The memory block shown in Fig. 3 is symmetrical, where the upper part of the memory block is related to the write function of the memory block, and the lower part that is symmetric to the upper part is related to the read function of the memory block. The following discussion focuses primarily on the elements of the memory block that relate to the write function, but the descriptions for these devices remain valid for symmetrical elements that relate to the read function.

Strt_W, MC_W, MC_R, Strt_R are 8-bit words, and these bits have the meaning described later. The signals MC_R and MC_W respectively define a read pattern during the read processing cycle and a write pattern during the write processing cycle. The processing cycle starts with a new control command set CC loaded in the controllers CTRL_W and CTRL_R during the setup phase. The exact meaning of each bit of the 8-bit word MC_W shown in FIG. 4 is as follows.

The least significant bit MC_W [0] indicates whether the write operation is enabled. If this bit is set to "1", a write operation is allowed, and if this bit is set to "0", the write operation is disabled, the counter CNT_W is not incremented, and other bits of MC_W are ignored.

MC_W [1] and MC_W [2] select a write operation pattern from four possible patterns. Table 1 defines the code stored in the internal controller CTRL_W that provides the pattern for the write operation.                 

MC_W [3], MC_W [4], and MC_W [5] represent the starting memory circuit number values for writing during the write cycle. In this embodiment of the present invention, the memory block MB includes five independent memory circuits, so that the numbers of the memory circuits 1 to 5 are encoded in this case as 3 bits in binary.

MC_W [6] is not used.

The most significant bit MC_W [7] indicates the need for a change of the memory circuit number during the write cycle. If this bit is set to "0", the memory circuit number is automatically incremented when the 8-bit address counter CNT_W advances from the beginning to the end of the memory circuit. If the memory circuit number is equal to the highest value (here 5), the memory circuit number coded in MC_W [3], MC_W [4], MC_W [5] is set to one. The controller CTRL_W accesses the current value of CNT_W for checking through transmission line 14. If this bit is set to "1", the memory circuit numbers coded in MC_W [3], MC_W [4], MC_W [5] are not changed during the write cycle.                 

Similar explanation is valid for the 8-bit word MC_R. The bits this time have the same meaning as the bits of MC_W for the read cycle. Thus, controller CTRL_R checks and resets the value of CNT_R via connection line 17 and allows counter CNT_R to load a new value in response to command ld.

An access collision is caused when the memory circuit selected during the read operation and the memory circuit selected during the write operation are the same, that is, MC_W [3] = MC_R [3], MC_W [4] = MC_R [4], MC_W [5] = MC_R Can occur when [5]. Conflicts also exist when both write and read operations are enabled, that is, when MC_W [0] = 1, MC_R [0] = 1. Unit COMP receives bits MC_W [0], MC_W [3], MC_W [4], MC_W [5] transmitted on line 15 from CTRL_W, and transmits bits MC_R [0] transmitted on line 16. , MC_R [3], MC_R [4], MC_R [5] are received from CTRL_R. Unit COMP compares the received bits bit by bit and, if a real memory access conflict (memory circuit number selected for read and write is the same and both read and write operations are enabled) detects line 16 By doing this, bit MC_R [0] that says the read operation is enabled is read as 0 by CTRL_R. In fact, the unit COMP does not exactly change MC_R [0], but MC_R [0] is still 1, but this causes it to be read as 0 by the controller CTRL_R. The collision is interrupted because one of the read and write operations is disabled during the new setup phase, or because the number of memory circuits accessed for read or write is changed during the new setup or during the read or write operation. In this case, the unit COMP no longer detects a collision, and the write operation is performed as usual.                 

Consider a case where it is necessary for data Di to be written to the memory system 2. Di is provided to port 3, and at the same time CTRL_W and CNT_W transmit their respective signals MS, R / W, AD_W. The MS signal is, for example, three coded bits representing the memory circuit number to be selected. This signal is transmitted to the demultiplexer DEMUX, and the output of the DEMUX is connected to each memory circuit MEM. The demultiplexer DEMUX sends a 1 to the memory circuit whose number is coded in the MS and 0 to all other circuits. The R / W signal is sent to all memory circuits, but only considered by the selected memory circuit, and also results in activation of the input port of the Di write memory circuit. The write address AD_W is also sent to all memory circuits, but only considered by the selected memory circuit. The data is then transferred towards the active input port in the memory block and to the indicated location in the selected memory circuit.

In an improved embodiment of the invention, the memory system 2 may transmit a signal indicating to the processor whether it is ready to receive or provide data. This prevents the processor from accessing this memory when the read memory is empty or when the write memory is already full.

The drawings and their descriptions are intended to illustrate, not limit, the invention. It will be apparent that various alternatives may exist that maintain the spirit of the appended claims. In this respect the following conclusion was made:

There are various ways of physically distributing the functions or functional elements across the various units. In this respect, the drawings are merely schematic, each of which merely represents a possible embodiment of the present invention.

Claims (5)

In the data processing apparatus 1, A first processor PROC1 for providing successive sets of input data, A second processor PROC2 that receives successive sets of output data, A memory system (2) having a plurality of memory circuits (MEM) for receiving said continuous input data set and providing said continuous output data set, The data processing apparatus further includes a master controller (MCP) for setting up the memory system by control commands (CC) associated with an input data set and an output data set, The memory system, When data Di is provided from the input data set by the first processor, a first memory circuit is selected based on the control command and a write address AD_W is generated in the first memory circuit. A control unit for selecting a second memory circuit based on the control command and generating a read address AD_R in the second memory circuit when data Do is requested from the output data set by the second processor; More including MCU) Data processing unit. The method of claim 1, The control unit, A write counter CNT_W indicating a value of the write address of the data in the first memory circuit, the value being changed in association with data received from the input data set; And a read counter (CNT_R) whose value is changed in association with data provided from the output data set, the read counter indicating the read address of the data in the second memory circuit. The method of claim 1, The control unit, A write input port 7 for receiving a write data signal NXT_W from the first processor in response to the control unit generating the write address; And a read input port (8) for receiving a read data signal (NXT_R) from said second processor in response to said control unit generating said read address. A memory system (2) comprising a plurality of memory circuits (MEM) for receiving a continuous set of input data and providing a continuous set of output data, Further comprising a control unit (MCU) programmable by a control command (CC) associated with the input data set and the output data set, Based on the control command, when data Di is received from the input data set, a first memory circuit is selected to generate a write address AD_W in the first memory circuit, while data from the output data set is received. When Do is provided, a second memory circuit is selected so that a read address AD_R is generated in the second memory circuit. Memory system. A first processor PROC1 for providing a continuous input data set, a second processor PROC2 for receiving a continuous output data set, and receiving the continuous input data set and providing the continuous output data set A method of processing data in a data processing apparatus 1 comprising a memory system 2 having a plurality of memory circuits MEM, For input data set and output data set, A configuration step of setting up the memory system with control commands associated with the input data set and the output data set; Based on the control command, when data belongs to the input data set, when the memory system selects a first memory circuit to generate a write address to the first memory circuit, and when data belongs to the output data set And an execution step in which the memory system selects a second memory circuit to generate a read address in the second memory circuit. How data is processed.

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