KR100655434B1 - Memory devices and methods for forming the same - Google Patents

Abstract

A memory device is provided to eliminate the necessity of an additional space for a byte select transistor and reduce the size of a chip by forming the byte select transistor in an N-well used for isolating a P-well in which a memory cell transistor is formed. A memory array is prepared in which memory cells are arranged in a matrix type in a well of a second conductivity type within a well of a first conductivity type. A byte select transistor is operationally coupled to memory cells of a byte unit in a corresponding row, formed in the well of the first conductivity type. Each row of the memory array includes at least two bundles of byte unit memory cells that are operationally coupled with different byte select transistors by a byte unit. The memory cell includes a channel of the first conductivity type, and the byte select transistor includes a channel of the second conductivity type.

Description

MEMORY DEVICES AND METHODS FOR FORMING THE SAME}

1 is an equivalent circuit diagram of a nonvolatile memory device according to one embodiment of the present invention;

2 is a top view of the exemplary memory device of FIG. 1;

3A is a cross-sectional view of the exemplary memory device of FIG. 2 taken along the local control lines 2A-2A '.

3B is a cross-sectional view of the example memory device of FIG. 2 taken along the bitline direction 2B-2B '.

4 is an equivalent circuit diagram of a nonvolatile memory device according to one embodiment of the present invention;

5 is a plan view schematically showing a memory device of a two transistor memory structure;

6 is an equivalent circuit diagram of a memory device according to an embodiment of the present invention in which a unit memory cell is composed of three transistors and has divided local control lines;

FIG. 7 schematically illustrates a program operating condition for a memory cell and a bias state of various memory cells in the memory device of FIG. 6; FIG.

FIG. 8 is a diagram schematically illustrating an erase operation condition of memory cells in units of bytes in the memory device of FIG. 6 and a bias state of various memory cells accordingly; FIG.

9 is a diagram illustrating a read operation condition of memory cells in units of bytes in the memory device of FIG. 6;

10 is an equivalent circuit diagram of a memory device according to an embodiment of the present invention in which a unit memory cell is composed of two transistors and has a divided local control line;

FIG. 11 is an equivalent circuit diagram of a memory device according to an embodiment of the present invention in which a unit memory cell is composed of one transistor and has a divided local control line; FIG.

12 schematically illustrates a program operating condition for a memory cell and a bias state of various memory cells according to the memory device of FIG. 10; And,

FIG. 13 is a view schematically illustrating an erase operation condition for byte memory cells and a bias state of various memory cells in the memory device of FIG. 10.

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a nonvolatile memory device and a method of forming the same.

A nonvolatile memory device has a characteristic of continuously retaining data even when power supply from the outside is interrupted. The nonvolatile memory device may be classified into a mask ROM, an EPROM, an EEPROM, and the like. EPIROM capable of erasing operations in units of pages, blocks, or sectors is particularly referred to as flash memory or flash EEPROM.

Since the flash memory performs an erase operation in units of pages or the like, a program (write) operation for a portion of data starts by reading data from flash memory cells in units of pages and storing the data in registers. The program operation is performed on the desired data in the register. Subsequently, the page-based memory cells in the flash memory array are erased, and the contents reprogrammed in the register are written back to the erased page-based flash memory cells.

Due to the characteristics of the erase and program operations in the flash memory, a flash memory device requires a register for storing data in units of erased pages. In addition, microprocessors are required for data processing in registers, and microprocessors must be larger and more complex when processing large amounts of data. Another disadvantage is that the endurance of the flash memory device is reduced due to the data read, erase and rewrite operations.

Accordingly, an EEPROM capable of byte-based erase operations has been proposed. A typical byte unit EEPROM includes a memory cell transistor and a selection transistor for selecting a byte unit memory cell transistor. However, these select transistors and memory cell transistors are formed in the same well as the same conductivity type. Thus, EEPROMs that support these conventional byte operations require high operating voltages for program / erase operations, which can interfere with reducing the size of memory cell transistors and select transistors.

An object of the present invention is to provide a nonvolatile memory device suitable for a high integration memory device and a method of forming the same.

Exemplary embodiments for achieving the object of the present invention provide a memory device.

In an embodiment, a memory device may include a memory array in which memory cells are arranged in a matrix in a well of a second conductivity type in a well of a first conductivity type; And byte select transistors formed in the well of the first conductivity type and operatively coupled to memory cells of byte units of a corresponding row, each row of the memory array being operatively coupled byte by byte to different byte select transistors. At least two groups of byte unit memory cells.

In the memory device, the byte select transistors may include a first byte select transistor and a second byte select transistor disposed in a first conductivity type well on both sides of the second conductivity type well.

In the memory device, each row of the memory array may include first byte unit memory cells operatively coupled to the first byte select transistor and second byte unit memory cells operatively coupled to the second byte select transistor. .

In the memory device, the first conductivity type may be n-type and the second conductivity type may be p-type.

In the memory device, the memory cell may include a channel of a first conductivity type, and the byte select transistors may include a channel of a second conductivity type.

In the memory device, each of the memory cells may include a first bit select transistor, a memory cell transistor, and a second bit select transistor, which are operatively coupled in series in a column direction. In this case, the control gates of the first byte unit memory cell transistors in each row of the memory array are connected to each other to form first local control lines operatively coupled to the first byte select transistor, and the second byte unit memory cell transistors Control gates may be connected to each other to form a second local control line operatively coupled to the second byte select transistor.

In the memory device, each of the memory cells may include: a memory cell transistor and a bit select transistor operatively coupled in series in a column direction. In this case, in each row of the memory array, the control gates of the first byte-byte memory cell transistors are connected to each other to form first local control lines operatively coupled to the first byte-selection transistor, and the second byte-by-byte unit The control gates of the memory cell transistors may be connected to each other to form a second local control line operatively coupled to the second byte select transistor.

The memory device includes a bit line operatively coupled to memory cell transistors in a column direction, a common source line operatively coupled to bit select transistors in a column direction, and a global control line operatively coupled to byte select transistors in a column direction. It may further include.

In an embodiment, a memory device may include a first bit select transistor, a memory cell transistor, and a second bit select transistor of a first conductivity type in a second well formed in a first well of a substrate. A memory array in which memory cells are arranged in a matrix; And byte select transistors of a second conductivity type formed in the first well to be operatively coupled to the memory cell transistors of the corresponding row.

In the memory device, control gates of memory cell transistors in each row of the memory array may be connected in units of bytes to form a first local control line and a second local control line that are operatively coupled to different byte select transistors.

In the memory device, global control lines operatively coupled to byte select transistors each arranged in a row direction, bit lines each operatively coupled to a first bit select transistor in a column direction, and each of the first in a row direction. The apparatus may further include common source lines operatively coupled to the 2 bit select transistors.

In the memory device, the memory cell transistor can be programmed by F-N tunneling. In this case, the program applies a negative voltage to the selected second well, applies a positive voltage to the selected global control line, and applies a voltage less than the voltage applied to the selected global control line to the unselected global control line. Float, turn on the selected byte select transistor, cut off the unselected byte select transistor, and conduct the signal sensing transistor to apply a voltage equal to the voltage applied to the selected second well to the selected bit line, and unselect. And applying a voltage greater than the voltage applied to the selected second well to the selected bit line.

In the memory device, the memory cell transistor may be erased by F-N tunneling. In this case, the erase applies a positive voltage to the selected second well, applies a negative voltage to the selected global control line, and applies a voltage greater than the voltage applied to the selected global control line to the unselected global control line. And floating the selected byte select transistor, blocking the unselected byte select transistor, and blocking the signal sensing transistor and the ground select transistor.

A memory device according to an embodiment of the present invention includes a plurality of memory cells including a first well of a first conductivity type formed in a substrate, and a memory array formed apart from each other in the first well, each having memory cells arranged in a matrix. Second wells of a second conductivity type; And a first byte selection formed in the first wells on both sides of each of the second wells and operatively coupled to the first byte unit memory cells and the second byte unit memory cells of each row of the memory array of the corresponding second well. A transistor and a second byte select transistor.

In the memory device, each of the memory cells may include a signal sensing transistor, a memory cell transistor, and a ground select transistor, which are operatively coupled in series in a column direction. In this case, the control gates of the memory cell transistors of the first byte unit of each row in each of the memory arrays are electrically connected to each other to form a first local control line that is operatively coupled to the first byte select transistor. Control gates of the memory cell transistors may be connected to each other to form a second local control line operatively coupled to the second byte select transistor.

In the memory device, each of the memory cells may include: a memory cell transistor and a bit select transistor operatively coupled in series in a column direction. In this case, the control gates of the memory cell transistors of the first byte unit of each row in each of the memory arrays are electrically connected to each other to form a first local control line that is operatively coupled to the first byte select transistor. Control gates of the memory cell transistors may be connected to each other to form a second local control line operatively coupled to the second byte select transistor.

In the memory device, the first conductivity type may be n-type and the second conductivity type may be p-type.

In the memory device, the memory cell may include a channel of a first conductivity type, and the byte select transistors may include a channel of a second conductivity type.

A method of forming a memory device according to an embodiment of the present invention comprises forming a memory array in which memory cells are arranged in a matrix in a well of a second conductivity type in a well of a first conductivity type; And forming byte select transistors formed in the well of the first conductivity type to be operatively coupled to the memory cells of the byte unit of the corresponding row, wherein each row of the memory array has byte units in different byte select transistors. At least two byte unit memory cells that are operatively coupled together.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween. In the drawings, the thicknesses of films and regions are exaggerated for clarity. In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films, and the like, but these regions and films should not be limited by these terms. . Also, these terms are only used to distinguish any given region or film from other regions or films. Thus, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment.

In addition, the meaning of "operating coupling" in the present specification means that a predetermined voltage applied to the gate element of the first transistor, for example, is transmitted to the terminal of the second transistor directly or indirectly through the third transistor. Can mean. Alternatively, it means that a specific terminal of the first transistor and a specific terminal of the second transistor (memory cell) are electrically connected or coupled to each other.

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device capable of byte-by-byte program / erase operations. The nonvolatile memory device of the present invention includes a nonvolatile memory cell and a byte select transistor arranged in a matrix. According to the nonvolatile memory device of the present invention, a memory cell transistor and a byte select transistor are formed in wells of different conductivity types. For example, the memory cell transistor may be formed in the p-type well and the byte select transistor may be formed in the n-type well. The p-type well in which the memory cell transistor is formed may be formed in the n-type well in which the byte select transistor is formed.

Alternatively, the conductivity type of the channel of the memory cell transistor and the conductivity type of the channel of the byte select transistor may be opposite conductivity types. For example, the channel of the memory cell transistors may be an n-type channel, and the channel of the byte select transistor may be a p-type channel.

In the present invention, a nonvolatile memory cell may be composed of one or more transistors. For example, a nonvolatile memory cell may consist of a single memory cell transistor (single transistor memory cell), a memory cell transistor and one bit select transistor (two transistor memory cell), or a memory cell transistor and two bits. Select transistors (three transistor memory cells). For convenience of description, a bit select transistor connected to a bit line in a two transistor memory cell and a three transistor memory cell will be referred to as a signal sensing transistor, and a bit select transistor connected to a common source line will be referred to as a ground select transistor.

The memory cell transistor includes a stacked gate structure. The stacked gate structure includes a memory layer insulated from the substrate and a control gate insulated from the memory layer by an inter-gate insulating film. As the charges move from the substrate to the insulated memory layer or the charges move in the opposite direction, the threshold voltage of the memory cell transistor is changed, thereby storing information. Various materials may be used as the memory layer, and when the memory layer used is a conductive layer, it is called a floating gate. In this case, the floating gates of adjacent memory cells may be electrically separated from each other. Polysilicon may be used as the floating gate. In addition to polysilicon, an insulating material having a high trap density such as silicon nitride may be used as the memory layer. In addition, as the memory layer, not only polysilicon, a nitride film, but also any material capable of storing charge, that is, aluminum oxide film (Al ₂ O ₃ ), hafnium oxide film (HfO), hafnium aluminum oxide film (HfAlO), and hafnium silicon oxide film (HfSiO) Insulators with a high trap density for charges may be used, or conductors such as metal, and nanocrystals of these materials or combinations of the materials listed above may be used.

The gates of the ground select transistor and the signal sensing transistor may have a stacked gate structure in the same manner as the memory cell transistor. Alternatively, the gates of the ground select transistor and the signal sensing transistor may have a different structure from that of the memory cell transistor. For example, the gates of the ground select transistor and the signal sensing transistor may be formed of the same material as the control gate of the memory cell transistor. Forming the same material here includes that when the control gates of the memory cell transistors are patterned, the gates of these ground select transistors and signal sensing transistors are also patterned at the same time.

On the other hand, the gate of the byte select transistor can also represent the same structure as the memory cell transistor. Preferably, the gate of the byte select transistor is formed of the same material as the control gate of the memory cell transistor. When the control gate of the byte select transistor is patterned, the gate of the byte select transistor is also patterned at the same time.

1 is an equivalent circuit diagram of a nonvolatile memory device in which three transistors according to the first embodiment of the present invention constitute a unit memory cell. 1 shows a P-well 15 in which the memory transistors are formed in a matrix in the N-well 13 for a clearer understanding of the present invention and for the sake of simplicity. Further, for example, 1024 rows of memory cell transistors may be formed in one P-well, but only 8 rows of memory cell transistors are shown. Also, although many bytes of memory transistors can be formed in one row of a memory arrangement, only one byte of memory cell transistors (eg eight memory cell transistors) is shown.

Referring to FIG. 1, memory cell transistors MCT11 to MCT1_8, MCT2_1 to 2_8,..., MCG8_1 to MCT8_8, are arranged in the P-well 15 in a lattice form. Signal sensing transistors (SST1_1 to SST1_8, SST2_1 to SST2_8, ..., SST8_1 to SST8_8) and ground select transistors (GST1_1 to GST1_8, GST2_1 to GST2_8, ..., GST8_1 to GST8_8) on both sides of each memory cell transistor In combination. One memory cell transistor MST1_1, a signal sensing transistor SST1_1, and a ground select transistor GST1_1 constitute a unit memory cell UMC1_1. These ground select transistors, signal sensing transistors, and memory cell transistors are all formed in the P-well 15.

Each memory cell transistor has a structure in which a floating gate, an inter-gate insulating film, and a control gate are stacked between a substrate and a tunnel insulating film. Control gates of adjacent memory cell transistors in a first direction (eg, row direction) are connected to each other to form local control lines LCL0, LCL1,..., LCL7. For example, in the drawing, control gates of the eight memory cell transistors MCT1_1, MCT1_2,..., MCT1_8 arranged in the first row are connected to each other to form a local control line LCL0. In addition, a separate low resistance local control line can be electrically coupled to the control gates in bytes.

Similarly, gates of adjacent signal sensing transistors in a row direction are connected to each other to form signal sensing lines SSL0, SSL1,..., SSL7. For example, in the drawing, gates of the eight signal sensing transistors SST1_1, SST1_2,..., SST1_8 arranged in the first row are connected to each other to form a signal select line SSL0. In addition, a separate low resistance signal sensing line may be electrically coupled to the gates of the signal sensing transistors.

In addition, the gates of the ground selection transistors adjacent in the row direction are connected to each other to form ground selection lines GSL0, GSL1, ..., GSL7. For example, in the drawing, gates of the eight ground selection transistors GST1_1, GST1_2,..., And GST1_8 arranged in the first row are connected to each other to form a ground selection line GSL0. In addition, a separate low resistance ground select line may be electrically coupled to the gates of the ground select transistors.

Signal sensing transistors arranged in a second direction (eg column direction) are operatively coupled to the same bit line. For example, the second impurity diffusion region (eg, drain) of the signal sensing transistors SST1_1, SST2_1,..., SST8_1 of the first column is electrically connected to the bit line BL0, and the signal of the eighth column. Second impurity diffusion regions (eg, drains) of the sensing transistors SST1_8, SST2_8,..., SST8_8 are electrically connected to the bit line BL7. Meanwhile, the first impurity diffusion regions (eg, sources) of the signal sensing transistors arranged in the column direction are connected to the first impurity diffusion regions of the corresponding memory cell transistors.

The second impurity diffusion region (eg, drain) of the ground selection transistors is connected to the second impurity diffusion region of the corresponding memory cell transistor, and the first impurity diffusion region (eg, source) of the ground selection transistors is grounded.

On the other hand, byte selection transistors BST1_1, BST2_1, ..., BST8_1 are operatively coupled to the byte unit memory cell transistors MST1_1, MST2_1, ..., MST8_1 of the corresponding row, respectively. For example, the byte selection transistor BST1_1 of the first row is operatively coupled to the local control line LCL1_1 to select the memory cell transistors MCT1_1 to MCT1_8. The byte selection transistor BST2_1 of the second row is operatively coupled to the local control line LCL2_1 to select the memory cell transistors MCT2_1 to MCT2_8. That is, the first impurity diffusion region (source) of each of the byte select transistors is electrically connected to a corresponding local control line. Meanwhile, the global control line GCL is electrically connected to the second impurity diffusion region (drain) of each of the byte select transistors. For example, the global control line GCL0 is operatively coupled to the byte selection transistor BST1_1 of the first row, and the global control line GCL1 is operatively coupled to the byte selection transistor BST2_1 of the second row. Therefore, eight memory cell transistors MCT1_1, MCT1_2,..., MCT1_8 are operatively coupled to the byte select transistor BST1_1. Gates of the byte select transistors arranged in the column direction are connected to each other to form a byte select line BSL0. Alternatively, a separate low resistance byte select line may be electrically coupled to the gates of adjacent byte select transistors in the column direction.

When an operating voltage is applied to the global control line and an appropriate voltage is applied to the byte select transistor, the operating voltage applied to the global control line is simultaneously applied to the control gates of the memory cell transistors in bytes.

These byte select transistors are formed in a different well from the P-well 15 in which the memory cell transistors are formed, that is, in the N-well 13. N-well 13 encloses P-well 15, that is, P-well 15 is formed in N-well 13.

Alternatively, the conductivity type of the channel of the byte select transistors is different from that of the channel of the memory cell transistors. For example, the conductivity type of the channel of the byte select transistors is p type, and the conductivity type of the channel of the memory cell transistors is n type.

The N-well 13 in which the byte select transistors are formed serves to electrically isolate adjacent P-wells. Therefore, in comparison with the byte select transistor formed in the same well as the memory cell transistor, according to the present invention, since the byte select transistor is formed in the N-well, the area of the P-well in which the memory transistors are formed is reduced. There are advantages to it. In addition, since the byte select transistors are formed inside the N-well necessary for the electrical separation of adjacent P-wells, no space for byte select transistors is required. Therefore, a high integration memory device can be implemented.

In FIG. 1, the ground selection transistors adjacent in the column direction may share a first impurity diffusion region (eg, a source). Similarly, the signal sensing transistors adjacent in the column direction may share the second impurity diffusion region (eg, drain). In addition, the sources of the ground selection transistors adjacent in the row direction may form a line type common source. In addition, the common source or the line-type common source in the row direction may be electrically connected to the common source line CSL which is a separate wiring.

FIG. 2 is a plan view of the exemplary memory device of FIG. 1, FIG. 3A is a cross-sectional view taken along the local control line 2A-2A ′ of FIG. 2, and FIG. 3B is a bit line BL direction of FIG. 2. It is sectional drawing when it cuts along (2B-2B '). 2, 3A and 3B, the shape of an exemplary active region in which memory cell transistors, signal sensing transistors, ground select transistors and byte select transistors are formed, and an exemplary relationship between a P-well and an N-well, An example coupling relationship between a byte select transistor and a memory cell transistor can be seen.

2, 3A and 3B, a P-well 15 is formed in the N-well 13 of the substrate 11, and a second fragrance (heat) is formed in the P-well 15, for example. Direction, the first active region 33 extending in the form of a line is formed, and the N-well 13 outside the P-well 15 is formed in a rectangular-shaped transistor, for example, in the form of a rectangular shape. 2 active regions 35 are formed. An isolation layer 19 defines active regions and electrically separates the active regions from each other. Referring to FIG. 2, the signal sensing line SSL, the local control line LCL, and the ground select line GSL pass across the first active region 33 and are disposed mirror symmetrically in the second direction. The signal sensing line SSL may be formed by connecting gates of signal sensing transistors arranged in a first direction (eg, a row direction), and the local control line LCL may be arranged in a first direction (row direction). The control gates 27 of the memory cell transistors 29 may be connected to each other, and the ground select line GSL may be formed by connecting the gates of the ground select transistors arranged in the first direction to each other. . The memory cell transistor includes a tunnel insulating film 21, a floating gate 23 as a memory layer, an inter-gate insulating film 25, and a control gate 27. In the ground selection transistor and the signal sensing transistor, the gate of the memory cell transistor may have the same stacked structure as that of the memory cell transistor. The gate of the byte select transistor may be formed of the same material as the control gate of the memory cell transistor.

Here, the signal sensing transistors adjacent in the second direction (eg, the column direction) share a common drain region. Similarly, the ground selection transistors adjacent in the second direction share a common source region, and the common source region extends in the first direction (row direction) to be connected to the adjacent common source region to form a line. The common source region in the form of a line is electrically connected to the common source line CSL. The bit line is electrically connected to the common drain region through the drain contact CDC.

The bite selection line BSL passes in the second direction (column direction) across the second active region 35. The byte select line BL may be formed by connecting the gates 39 of the byte select transistors arranged in the second direction to each other. The source 36S of the byte select transistor BST is electrically connected to the corresponding local control line LCL through the local wiring 37. The global control line GCL is electrically connected to the drain 36D of the byte select transistor BST.

Referring to FIG. 2, the line width of the memory cell transistor, for example, the width of the local control line LCL, is determined by the line widths of the signal sensing line SSL and the ground selection line GSL, such as the gates of the signal sensing transistor and the ground selection transistor. It may be narrower than the width. It is preferable to design the same line width in the manufacturing process, but the line widths of the ground selection transistor and the signal sensing transistor may be wider than the line width of the memory cell transistor in order to form a reliable device. However, the line width of the memory cell transistors should be as small as possible to achieve high integration. In addition, the narrower the line width of the memory cell transistor, the lower the program / erase operation.

In the case where the gate of the byte select transistor is formed in the same step as the control gate, the signal sensing line SSL and the ground select line GSL are formed in a well unit, and the signal sensing line and the ground select line between adjacent wells are formed. And each may be electrically connected to each other through local interconnection. At this time, a contact for local connection wiring between adjacent signal selection lines and adjacent ground selection lines is located in an N-well between adjacent P-wells. Electrical connection between adjacent signal sensing lines and electrical connection between adjacent ground selection lines can be implemented without the need for additional space.

However, in some embodiments, the ground selection line and the signal sensing line may not be cut in units of wells.

Hereinafter, the operation of the memory device according to the present embodiment will be described. The program / erase operation in the present invention uses, for example, Fouler-Nordheim (F-N) tunneling. F-N tunneling is performed through a tunnel insulating film interposed between the substrate (P-well) and the memory layer of the memory cell transistor. In order for F-N tunneling to occur, a high voltage difference must be generated between the substrate (P-well) and the memory cell transistor. In this embodiment, it is assumed that the high voltage difference required for the program / erase operation is about 18 volts for illustrative purposes only.

The program can refer to the injection of electrons into the memory layer of the memory cell transistor. In contrast, erasure may refer to the release of electrons from the memory layer to the substrate. On the other hand, in the case of a hole (hole) may refer to the reverse case. Further, the program may refer to increasing the threshold voltage of the memory cell transistor, and erasing may refer to decreasing the threshold voltage of the memory cell transistor.

According to the present invention, since the byte memory cell transistor, the signal sensing transistor, and the ground select transistor are formed in a well of a conductivity type different from that of the byte select transistor, the program / erase operation is required through an appropriate combination of negative voltage and positive voltage. The voltage level can be lowered to enable lower voltage operation and to reduce the size of the memory device. For example, the program operating voltage can be lowered by appropriately distributing a high amount of voltage required for the program operation to voltages of different polarities.

Consider a case where a voltage difference of, for example, 18 volts is required between a memory cell transistor and a channel during a program / erase operation. In a typical case, a high voltage of about 18 volts should be applied to a control gate of a memory cell transistor during a program operation, and a high voltage of about 18 volts should be applied to a substrate during an erase operation. However, in the case of the present invention, by applying a voltage of opposite polarity to the substrate and the memory cell transistor, a high voltage is prevented from being applied to the substrate and the memory cell transistor. For example, in accordance with the present invention, a memory cell transistor and the underlying device may be applied by applying about 10 volts to the control gate of the memory cell transistor and about -8 volts to the substrate P-well during the program operation. Create a voltage difference of about 18 volts between the channels. In the erase operation, a voltage of about 10 volts is applied to the substrate P-well, and a voltage of about -8 volts is applied to the control gate. As the negative voltage is applied to the substrate (P-well), the voltage applied to the gate (signal sensing line) of the signal sensing transistor, the gate (ground select line) of the ground select transistor, and the bit line is appropriately adjusted accordingly. In some cases, negative voltages may be applied to them.

In the present invention, for example, a self-boosting technique may be used to prevent the memory cell transistors (unselected memory cell transistors) adjacent to the memory cell transistors (selected memory cell transistors) to be programmed. The self-boosting technique uses an impurity diffusion region when a high program voltage is applied to the unselected memory cell transistor (control gate) while the potential of the impurity diffusion region of the unselected memory cell transistor is floated slightly higher than that of the substrate (P-well). The potential of the channel under the unselected memory cell transistor is boosted by capacitive coupling between the channels. On the other hand, if a high program voltage is applied to the selection memory cell transistor while the potential of the impurity diffusion region of the selection memory cell transistor is kept the same as the substrate (P-well), between the impurity diffusion region and the channel of the selection memory cell transistor. No capacitive coupling occurs and the potential of the channel remains intact. When using the self-boosting technique, unlike the two-transistor memory cell, since the high voltage does not need to be applied to the signal sensing transistor, it is possible to manipulate the size of the signal sensing transistor smaller than the two-transistor memory cell, It is easier to implement the memory device.

Hereinafter, the operation of the memory device according to the first embodiment of the present invention will be described in more detail with reference to Tables 1, 2, and 4 below. Unlike FIG. 1, another P-well 17 is added to FIG. 4. The added P-well 17 shows the same structure as the P-well 15 of FIG. However, the byte select transistor (BST) is not necessarily, but is located between the two P-wells (15, 17) to share the drain and the global control line is electrically connected thereto.

Exemplary program operating conditions for the memory cell transistor MCT1_1 of FIG. 4 are schematically shown in Table 1 below, and Table 2 below shows memory cell transistors MCT1_1, MCT1_2, ..., MCT1_8 in byte units. The erase operation condition is shown schematically.

In Tables 1 and 2 below, "source" refers to the source of the ground select transistor (GST).

Table 1 (Program Operating Conditions)

Source Ground Selection Line (GSL) Byte select line (BSL) Global control line (GCL) P-well Bit line BL Signal Sensing Line (SSL) N-well Floating -8 volts Apply 0 volt to selected byte select line (BSL0) 10 volts applied to the selected global control line (GCL0) Apply -8 Volts to Selected P-Well 15 Apply a voltage (-8 volts) equal to the voltage applied to the P-well 15 to the selected bit line BL0 Apply a voltage (-5 volts) greater than the voltage applied to the bit line to the selected signal sensing line SSL0 and the unselected signal sensing lines SSL1-7. 10 volts 10 volts applied to unselected byte select line (BSL1) Voltage (-5 volts) or less than the voltage applied to the selected global control line (GCL0) to the unselected global control lines (GCL1 to GCL7,) Apply 0 volts to unselected P-well 17 Applying a voltage (-5 volts) greater than the voltage applied to the selected bit line BL0 to the unselected bit lines BL1 to BL7, and floating the unselected bit lines BL8 to 15.

Referring to FIG. 4 and Table 1, for programming the memory cell transistor MCT1_1, a negative voltage (for example, about -8 volts) is applied to the selected P-well 15 and the selected global control line GCL0. ) Is applied to the selected byte select line BSL0, and 0 volts is applied to conduct the byte select transistor BST1_1 to the selected byte select line BSL0. The signal sensing transistors are turned on to apply -5 volts to the signal sensing line SSL0 so that the bit line voltage is transferred to the memory cell transistor. A voltage (for example, about −8 volts) equal to the voltage applied to the selected P-well 15 is applied to the selected bit line BL0 connected to the selected memory cell transistor MCT1_1. Under such a condition, the potential of the channel of the selected memory cell transistor MCT1_1 is equal to the impurity diffusion region between the memory cell transistor MCT1_1 and the signal sensing transistor SST1_1. As a result, a high voltage difference (for example, about 18 volts) occurs between the selected memory cell transistor MCT1_1 and the channel of the selected P-well 15 below, and the charge is moved to the selected memory cell transistor MCT1_1. do.

Meanwhile, in order to prevent program disturbance caused by memory cell transistors MCT1_2 to MCT1_8 belonging to the same byte row as the selected memory cell transistor MCT1_1, unselected bit lines BL1 to BL7 connected to the selected memory cell transistors MCT1_1. Is applied a voltage higher than the voltage applied to the selected P-well 15 (eg -8 volts), for example -5 volts. Under these conditions, the impurity diffusion region between the unselected memory cell transistors MCT1_2 to MCT1_8 and the signal sensing transistors SST1_2 to SST1_8 is floated to a somewhat higher state than the P-well 15. Therefore, even when a high amount of voltage (10 volts) is applied to the memory cell transistors MCT1_2 to MCT1_8, due to the capacitive coupling between the impurity diffusion region and the channel, these unselected memory cell transistors MCT1_2 to MCT1_8 and the channel are applied. There is no high voltage difference (about 18 volts) that causes the FN tunneling of the charge. Therefore, program disturb by memory cell transistors MCT1_2 to MCT1_8 belonging to the same byte as the selected memory cell transistor MCT1_1 does not occur.

Also, in order to prevent program disturb by unselected memory cells MCT2_1 to MCT2_8, ..., MCT8_1 to MCT8_8 belonging to the same P-well 15 as the selected memory cell transistor MCT1_1 but belonging to another byte row. The global control lines GCL1 to GCL7 coupled thereto are applied with a low voltage, for example about -5 volts, of the same polarity as the voltage applied to the floating or selected P-well 15. Thus, even if the selected P-well 15 is -8 volts, the memory cell is received -5 volts from the corresponding global control lines GCL1-GCL7 or the global control lines GCL1-GCL7 are floated. There is no high voltage difference that may cause FN tunneling between the transistors MCT2_1 to MCT2_8, ..., MCT8_1 to MCT8_8 and the channel beneath it.

In order to prevent program disturb by unselected memory cells (MCT1_9 to MCT1_16, MCT2_9 to MCT2_16, ..., MCT8_9 to MCT8_16) belonging to different P-wells and different bytes from the selected memory cell transistor MCT1_1. The byte select transistors BST1_2, BST2_2,..., BST8_2 coupled to the unselected P-well 17 are blocked. The blocking of the byte select transistors BST1_2 to BST8_2 may be achieved by applying a voltage equal to the voltage applied to the N-well 13 (for example, 10 volts) to the byte select line BL1. At this time, the unselected bit lines BL8 to BL15 coupled to the unselected P-well 17 may be floated for stability of operation although voltages applied to other terminals may be used. In addition, since the byte select transistors BST1_2 to BST8_2 are blocked, a voltage applied to other terminals, for example, a voltage applied to the selected P-well 15 may be applied to the unselected P-well 17. For the stability of the operation, 0 volts is applied to the unselected P-well 17.

In the above-described program operation, a program operation for several bits or bytes or a plurality of bytes may be simultaneously performed.

Table 2 below shows exemplary erase operation conditions for the memory cell transistors MCT1_1 to MCT1_8 of the P-well 15.

Table 2 (Erase Operation Conditions)

Source Ground Selection Line (GSL) Byte select line (BSL) Global Control Line (GCL) P-well Bit line BL Signal Sensing Line (SSL) N-well Floating Vcc Accreditation Apply -10 Volts to Selected Byte Selection Line (BSL0) -8 volts applied to the selected global control line (GCL0) 10 volts applied to selected P-wells 15 Plot the selected bit lines BL0 to BL7 4 to 5 volts 10 volts 10 volts applied to unselected byte select line (BSL1) Voltage (4 to 5 volts) or floating greater than the voltage applied to the selected global control lines (GCL0) to the unselected global control lines (GCL1 to GCL7) Apply 0 volts to unselected P-well 17 Plot unselected bit lines BL8 to BL15

4 and 2, in the erase operation for the memory cell transistors MCT1_1 to MCT1_8 in byte units, unlike the program operation for the memory cell transistor MCT1_1, a positive voltage is applied to the selected P-well 15. (E.g., about 10 volts) is applied, a negative voltage (e.g., about -8 volts) is applied to the selected global control line (GCL0) and a byte select transistor (BST1_1) is conducted to the selected byte select line (BSL0). A negative voltage (e.g. about -10 volts) is applied. The selected signal sensing line SSL0 and the selected ground select line GSL0 have an amount lower than the amount of voltage applied to the selected P-well 15 such that the signal sensing transistors and the ground selection transistors coupled thereto are blocked. For example, a voltage of about 4 to 5 volts is applied. Therefore, a negative voltage of about -8 volts is applied to the memory cell transistors MCT1_1 to MCT1_8 through the selected global control line GCL0, so that a positive voltage of about 10 volts is applied to the channel of the P-well 15. A high voltage difference occurs between and, and accordingly, an erase operation is performed on the memory cell transistors MCT1_1 to MCT1_8 in a byte unit.

On the other hand, for the unselected memory cells MCT2_1 to MCT2_8, ..., MCT8_1 to MCT8_8 belonging to the same P-well 15 as the byte-selected memory cell transistors MCT1_1 to MCT1_8 but belonging to another byte row. In order to prevent the erase operation, the global control lines GCL1 to GCL7 coupled thereto are applied with a low voltage, for example about 5 Volts, having the same polarity as the voltage applied to the floating or selected P-well 15. Thus, even if the selected P-well 15 is 10 volts, the memory cell transistors may receive 5 volts from the corresponding global control lines GCL1 to GCL7 or the global control lines GCL1 to C7 are floated. There is no high voltage difference that can cause FN tunneling between (MCT2_1 ~ MCT2_8, ..., MCT8_1 ~ MCT8_8) and the channel.

In addition, in order not to perform an erase operation on the memory cell transistors belonging to the P-well 17 different from the selected memory cell transistors MCT1_1 to MCT1_8 in units of bytes, the unselected P-well 17 may be erased. Blocks the combined byte select transistors BST1_2 to BST8_2. The blocking of the byte select transistors BST1_2 to BST8_2 may be achieved by applying a voltage equal to the voltage (for example, 10 volts) applied to the N-well 13 to the byte select line BL1. At this time, the unselected bit lines BL8 to BL15 coupled to the unselected P-well 17 may be floated for stability of operation although voltages applied to other terminals may be used. In addition, since the byte select transistors BST1_2 to BST8_2 are blocked, a voltage applied to other terminals, for example, a voltage applied to the selected P-well 15 may be applied to the unselected P-well 17. For the stability of the operation, 0 volts is applied to the unselected P-well 17.

By properly changing the voltages applied to the P-well, the byte select line, and the global control line in the erase operation, the number of bytes erased in the same P-well can be adjusted appropriately. For example, when a negative voltage is applied to the global control line GCL1, the erase operation is performed on the memory cell transistors MCT2_1 to MCT2_8.

In addition, it is possible to cause the erase operation in bytes in two or more P-wells at the same time. For example, if 10 volts is applied to the P-well 17 and −10 volts is applied to the byte select line BSL1, the erase operation is performed on the memory cell transistors MCT1_9 to MCT1_16 of the P-well 17.

Read operation can be performed by bit unit, byte unit, page unit, or block unit. For read operations, zero volts is applied to the selected P-well and an operating voltage (Vcc) of about 2 to 3 volts to the N-well. A voltage is applied between the threshold voltage of the memory cell transistor where the program operation is performed and the threshold voltage of the memory cell transistor where the erase operation is performed through the selection global control line GCL. For example, assuming that the threshold voltage of the programmed memory cell transistor is about 4 volts and the erased memory cell transistor is about 0.5 volt, the selected global control line (GCL) has an operating voltage of about 2 to 3 volts. Apply (Vcc). A 0 volt is applied to the selection byte selection line BSL to conduct the selection byte selection transistor connected to the selection memory cell transistors. The operating voltage Vcc is applied to the selection ground selection line GSL and the selection signal sensing line SSL to conduct ground selection transistors and signal sensing transistors connected to the selection memory cell transistors. 0 volts is applied to the selection common source line CSL, and a low positive voltage, such as 0.5-0.8 volts, is applied to the selection bit line as a precharge voltage. Under these conditions, if the memory cell transistor is in the programmed state (the threshold voltage is high), the memory cell transistor is not conductive and thus the voltage applied to the bit line does not change significantly. On the other hand, if the memory cell transistor is in an erased state (a threshold voltage is low), the memory cell transistor is turned on, and thus the voltage of the bit line will drop toward 0 volt. Therefore, when the voltage change of the bit line is detected, the state of the memory cell transistor can be checked.

On the other hand, in order to avoid read disturb of the unselected memory cell transistors, the unselected byte select line (BSL) is floated, 0 volts are applied to the unselected ground select line (GSL) and the unselected signal sensing line (SSL), and the unselected global control line ( GCL) is applied with a voltage lower than the threshold voltage of the unselected memory cell transistors connected thereto, for example, 0 volts.

In the program / erase operation described above, the voltage difference required between the P-well and the memory cell transistor is described as an example of 18 volts, but the required voltage difference may be lower, and accordingly, the P-well and the memory cell transistor are The voltage applied to will also be set to an appropriately low level.

1 to 4 may be equally applicable to a memory device in which two transistors constitute a unit memory cell or a memory device in which one transistor constitutes a unit memory cell. In particular, in a memory device having a two transistor memory cell structure, the channel width of the memory cell transistor is formed to be smaller than the channel width of the ground select transistor. 5 is a plan view schematically illustrating a two transistor memory device.

Referring to FIG. 5, P-wells 15 and 17 are formed in the N-well 13 of the substrate 11, and each of the P-wells 15 and 17 has a second direction (column direction, for example). The first active region 33 is formed to extend in the form of a line, and the N-well 13 between the P-wells 15 and 17 is formed in a rectangular shape, for example, for a byte select transistor. The second active region 35 of is formed. An isolation layer 19 defines active regions and electrically separates the active regions from each other. The local control line LCL and the ground select line GSL pass across the first active region 33 and are arranged mirror symmetrically in the second direction. The local control line LCL may be formed by connecting control gates of memory cell transistors arranged in a row direction, and the ground select line GSL may be formed by connecting gates of ground select transistors arranged in a row direction to each other. Can be. Each of the memory cell transistors includes a tunnel insulating film, a floating gate as a memory layer, an inter-gate insulating film, and a control gate. The gate of the ground select transistor has the same stacked structure as the memory cell transistor. The gate of the byte select transistor may be formed of the same material as the control gate of the memory cell transistor.

Here, the ground select transistors adjacent in the column direction share a common source region. In addition, the source region may extend in the row direction and be connected to an adjacent common source region to form a line shape. The common source region in the form of a line is electrically connected to the common source line CSL. Memory cell transistors adjacent in the column direction share a common drain region, and bit lines are electrically connected to each other through a drain contact (CDC).

The bite selection line BSL crosses the second active region 35 in the second direction column direction. The byte select line BL may be formed by connecting gates of byte select transistors arranged in a second direction to each other. The source 36S of the byte select transistor BST is electrically connected to the corresponding local control line LCL through the local wiring 37. The global control line GCL is electrically connected to the drain 36D of the byte select transistor BST.

The line width of the memory cell transistor, for example, the width of the local control line LCL, may be narrower than the line width of the ground select line GSL, for example, the width of the gate of the ground select line. Although it is preferable to design the same line width in the manufacturing process, the line width of the ground select transistor may be wider than the line width of the memory cell transistor in order to secure reliable device characteristics. On the other hand, the line width of the memory cell transistors should be formed as small as possible for high integration. In addition, the narrower the line width of the memory cell transistor, the lower the program / erase operation.

When the gate of the ground select transistor has the same structure as that of the memory cell transistor, and the gate of the byte select transistor is formed of the same material as that of the control cell of the memory cell transistor, the ground select line GSL may be formed by separating wells. have. In this case, the adjacent ground selection lines are electrically connected to each other through the local connection wiring 39, and a contact 38 for this is located in the N-well 13 between the adjacent P-wells 15 and 17. Electrical connections between adjacent ground select lines can be implemented without the need for additional space.

6 is a schematic equivalent circuit diagram of a memory device according to still another embodiment of the present invention. Unlike the memory device described with reference to FIGS. 1 through 4, two groups of byte unit memory cell transistors are formed in one P-well 15 controlled by different byte select lines. In the case of FIG. 4, for example, one byte of memory cell transistors is formed in different P-wells in a specific row so that adjacent byte-by-byte memory cell transistors are separated by P-wells in the same row. In this case, memory cell transistors of byte units are separated by separating control gates of units of bytes within the same P-well. According to the present embodiment, in the same P-well, two local control lines separated by bytes are arranged in each row, and different byte selection lines are operatively coupled to each local control line. And the distance between two local control lines separated from each other in the same P-well is smaller than the distance between adjacent P-wells. Thus, a higher degree of integration can be achieved compared to the memory device as shown in Figs.

Referring to FIG. 6, a plurality of P-wells are formed in the N-well 13 of the substrate. Two P-wells 15 and 17 are shown for simplicity of the figure. In each P-well, unit memory cells UMC including a signal sensing transistor SST, a memory cell transistor MCT, and a ground select transistor GST are arranged in a matrix. For the sake of simplicity, 8 rows and 16 columns of unit memory cells are shown in each P-well. Byte select transistors BST are arranged in the N-well 13 between adjacent P-wells 15 and 17. Since byte select transistors BST are formed in the N-well used to separate the P-wells, no additional space is needed for the byte select transistors BST.

Gates of the byte select transistors arranged in each column are connected to each other to form byte select lines BSL0 to BSL3.

In each P-well, the gates of the signal sensing transistors arranged in each row are electrically connected to each other to form signal sensing lines SSL0 to SSL7, and the gates of the ground selection transistors arranged in each row are electrically connected to each other. To form ground selection lines GSL0 to GSL7.

Drains of the signal sensing transistors of the same column are electrically connected to the same bit line, and two signal sensing transistors adjacent in the column direction share the drain to form a common drain. Two adjacent ground select transistors in the column direction share a source to form a common source region. Common source regions of the same row may be connected to adjacent common source regions to form a line shape. In addition, the common source region (or common source region in the form of a line) of each row is electrically connected to the corresponding common source lines CSL0 to CSL3.

Each memory cell transistor is located between the signal sensing transistor and the ground select transistor and is operatively coupled to these signal sensing transistors and the ground select transistor.

Meanwhile, the control gates of the memory cell transistors arranged in the same row in each P-well are connected to each other by byte to form a plurality of divided local control lines. For example, the control gates of the memory cell transistors MCT1_1 to MCT1_8 in the first byte of the first row of the P-well 15 are connected to each other to form a local control line LCL1_1, and Control gates of the memory cell transistors MCT1_9 to MCT1_16 of the second byte unit are connected to each other to form another local control line LCL1_2. Local control lines separated from each other in the same row of each P-well are operatively coupled to different byte select lines. For example, the local control line LCL1_1 of the first row of the first P-well 15 is operatively coupled to the byte select line BSL0, and the local control line LCL1_2 of the first row is the byte select line ( Operationally couple to BSL1).

Similarly, the control gates of the memory cell transistors in the first byte unit of the first row of the second P-well 17 are connected to each other to form a local control line LCL1_3, and the global control of the memory cell transistors in the second byte unit. The lines are connected to each other to form a local control line LCL1_4. The local control line LCL1_3 of the first row of the second P-well 17 is operatively coupled to the byte select line BSL2, and the local control line LCL1_4 is operatively coupled to the byte select line BSL3.

In this embodiment, the contact for electrical connection between the common source line and the common source region is located in the region between memory cell transistors belonging to different bytes in each P-well, that is, in the region between adjacent local control lines. can do. Therefore, a separate space is not required for a contact for electrical connection between the common source region and the common source line, and according to the present invention, a memory device having a higher degree of integration can be realized.

Also, as mentioned above, the distance between two local control lines apart from each other in each row is smaller than the distance between adjacent P-wells. Therefore, according to the present embodiment, the memory chip size can be further reduced. For example, assuming that the distance between adjacent P-wells is approximately 3.4 micrometers, the distance between adjacent local control lines in one P-well is approximately 0.14 micrometers.

For more efficient memory cell placement in this embodiment, two byte select lines are placed between P-wells 15 and 17 that are operatively coupled to local control lines of the P-well adjacent to each other. In addition, adjacent byte select transistors may share a drain, to which a global control line is electrically connected. For example, the byte select transistor BST1_2 is operatively coupled to the second local control line LCL1_2 of the first row of the first P-well 15, and the first local of the first row of the second P-well 17 is coupled. The byte select transistor BST1_3 is coupled to the control line LCL1_3 in operation. The byte select transistor BST1_2 and the byte select transistor BST1_3 between the first P-well 15 and the second P-well 17 share a drain, and the global control line GCL0 is electrically connected to each other. Connected.

Also, in the present embodiment, memory cell transistors of different bytes may be connected to two divided local control lines of the same row. For example, in each row of each P-well, a first byte of memory cell transistors are operatively coupled to the first local control line (LCL1_1), and a second byte of memory cell transistors are connected to the second local control line (LCL1_2). Can be combined in operation.

Also, in the present embodiment, four local control lines may be arranged in the same row of the same P-well, and four different byte select lines which are operatively coupled to each local control line are arranged on the top, bottom, left, and right sides of the P-well. It may be arranged.

The program operation for the memory device of this embodiment is almost the same as the operation condition of the memory device described with reference to FIGS. 1 to 4. That is, 10 volts is applied to the N-well 13 and -8 volts to the selected P-well 15; 10 volts to the selected global control line and -5 volts or to the unselected global control line; Apply 0 volts to the selection byte selection lines and 10 volts to the unselected byte selection lines; Applying -5 volts to the selected and unselected signal sensing lines; -8 volts are applied to the selected and unselected ground selection lines; -8 volts is applied to the bit line (selection bit line) connected to the selected memory cell transistor, -5 volts is applied to the unselected bit line connected to the unselected memory cell transistor of another column of the same byte row as the selected memory cell transistor. Plot the unselected bit lines.

In the present embodiment, two bytes of memory cell transistors separated by bytes are located in the same row in the same P-well, and each memory cell byte is controlled by a different byte select line. Therefore, the program operation of the present embodiment, unlike the program operation for the memory device of FIGS. 1 to 4, is local control in the selected P-well 15 to which the memory cell transistor to be programmed, for example, the memory cell transistor MCT1_1 belongs. The memory cells located on the right side coupled to the lines LCL1_2, LCL2_2,..., LCL8_2 and the memory cell transistors of the other P-well 17 adjacent to each other are placed under different bias conditions. That is, -8 volts is applied to the selected P-well 13, but 0 volts is applied to the unselected P-well 17. However, since the byte select transistors BST1_2, BST2_2,..., 8_2 are blocked, they are coupled to the local control lines LCL1_2, LCL2_2,..., LCL8_2 in the selected P-well 15. No voltage of 10 volts is transmitted from the global control line GCL0 to the memory cells located on the right side, and these memory cell transistors are not programmed in the same way as the memory cell transistors of the adjacent P-well 17.

Program operations for the memory device of the present embodiment described above are summarized in Table 3 below. Table 3 shows program operating conditions for the memory cell transistors MCT1_1 of the first row and the first column of the first P-well 15 in the memory device of FIG. 6.

Table 3 (Program Operating Conditions)

Common Source Line (CSL) Ground Selection Line (GSL) Byte select line (BSL) Global control line (GCL) P-well Bit line BL Signal Sensing Line (SSL) N-well Floating -8 volts Apply 0 volt to selected byte select line (BSL0) 10 volts applied to the selected global control line (GCL0) Apply -8 Volts to Selected P-Well 15 Apply a voltage (-8 volts) equal to the voltage applied to the P-well 15 to the selected bit line BL0 Applying a voltage (-5 volts) higher than the voltage applied to the bit line to the selected signal sensing line SSL0 and the unselected signal sensing lines SSL1 to SSL7 10 volts Apply 10 volts to unselected byte select lines (BSL1 to BSL3) Voltage (-5 volts) or less than the voltage applied to the selected global control line GCL0 in the unselected global control lines GCL1 to GCL7 Apply 0 volts to unselected P-well 17 The non-selected bit lines connected to other bytes by applying a voltage (-5 volts) higher than the voltage applied to the selected bit line BL0 to the unselected bit lines BL1 to BL7 connected to the byte to which the selected memory cell transistor belongs. Plot (BL8 ~ 31)

FIG. 7 schematically illustrates a program operating condition for a memory cell and a bias state of various memory cells in the memory device according to the present embodiment. Referring to FIG. 7, memory cell A is selectively programmed, adjacent memory cells B belonging to the same byte as memory cell A, and memory cells D and E of another byte row of the same P-well. And it can be seen that memory cells C belonging to different bytes of the same row of the same P-well and memory cells F of another P-well are not programmed.

The erase operation of the memory device of the present embodiment illustrated in FIG. 6 is the same as the erase operation of the memory device described above with reference to FIGS. 1 to 4. 10 volts is applied to the N-well 13, 10 volts to the selected P-well 15, and 0 volts to the unselected P-well 17 for byte erase operations; -8 volts to the selected global control line and 5 volts or to the unselected global control line; Apply -10 volts to the selection byte selection lines and 10 volts to the unselected byte selection lines; Applying 5 volts to the selected and unselected signal sensing lines; 5 volts are applied to the selected and unselected ground selection lines; Plot the selected and unselected bit lines.

In the present embodiment, two bytes of memory cell transistors separated by bytes are located in the same row in the same P-well, and each memory cell byte is controlled by a different byte select line. Therefore, in the program operation of the present embodiment, unlike the program operation for the memory device of FIGS. 1 to 4, 10 volts is applied to the selected P-well 13, but 0 volts is applied to the unselected P-well 17. Can be. However, since the byte select transistors BST1_2, BST2_2,..., 8_2 are blocked, they are coupled to the local control lines LCL1_2, LCL2_2,..., LCL8_2 in the selected P-well 15. The memory cells located on the right side do not receive a voltage of -8 volts from the global control line GCL0 and are not erased like the memory cell transistors of the adjacent P-wells 17.

The erase operation according to the present embodiment described above is summarized in Table 4 below. Table 4 shows the erase operation conditions for the first eight memory cell transistors MCT1_1 to MCT1_8 of the first row of the first P-well 15 in the memory device of FIG. 6.

Table 4 (Erase Operation Conditions)

Common Source Line (CSL) Ground Selection Line (GSL) Byte select line (BSL) Global Control Line (GCL) P-well Bit line BL Signal Sensing Line (SSL) N-well Floating Vcc Accreditation Apply -10 Volts to Selected Byte Selection Line (BSL0) -8 volts applied to the selected global control line (GCL0) 10 volts applied to selected P-wells 15 Floating selected bit lines BL0 to BL7 and unselected bit lines BL8 to BL31 About 4-5V 10 volts Apply 10 volts to unselected byte select lines (BSL1 to 3) Unselected global control lines (GCL1 to GCL7) Voltages greater than the voltage applied to the selected global control line (GCL0) (for example about 4 to 5 volts) or floating Apply 0 volts to unselected P-well 17

FIG. 8 schematically illustrates an erase operation condition for a byte unit memory cell and a bias state of various memory cells in the memory device according to the present embodiment. Referring to FIG. 8, an erase operation is performed on the memory cells A in the byte unit, the byte unit memory cells C in a row different from the memory cells A, the other byte unit memory cells B in the same row, In addition, it may be confirmed that the erase operation does not occur with respect to the memory cells D of the same row and the memory cells E of the other row of the other P-well.

The read operation of this embodiment is the same as the read operation of the memory device described with reference to FIGS. 1 to 4. That is, the operating voltage Vcc is applied to the selected global control line, 0 volts is applied to the unselected global control line, 0 volts is applied to the selected byte selection line, and the operating voltage is applied to the unselected byte selection line. Apply a positive low precharge voltage to the bit line, float the unselected bit line, apply zero volts to the ground select line, apply an operating voltage to the N-well and zero volts to the P-well.

FIG. 9 schematically illustrates a read operation condition for a byte unit memory cell in a memory device according to the present embodiment described above.

According to this embodiment, since a high voltage difference can be generated by applying an appropriate combination of positive and negative voltages to the P-well and the memory cell transistor, the memory cell transistor is typically used for program operation and erase operation. Or there is no need to apply a high voltage to the substrate. Further, according to the present embodiment, since the byte select transistor is formed in the N-well necessary for the electrical separation between adjacent P-wells, the size of the P-well in which the memory cell transistor is formed can be reduced. In addition, according to the present embodiment, since memory cell transistors are operatively separated from memory cell transistors of adjacent byte units by byte in one P-well by dividing the control gate, the P-well is separated. In comparison with this, the semiconductor device can be integrated at a higher density. In addition, according to the present embodiment, no additional space is required since a contact for electrical connection between the common source line and the common source region is formed in the space between two adjacent byte-cell memory transistors in the P-well.

The divided local control line structure of FIG. 6 may be applied to a memory device having a two transistor memory cell structure and a memory device having a one transistor memory cell structure, and an equivalent circuit diagram thereof is shown in FIGS. 10 and 11.

In the memory device of FIG. 6, in the memory device of FIG. 6, a signal sensing transistor or a ground select transistor of the transistors constituting the unit memory cell is omitted so that two transistors form the unit memory cell. 10 exemplarily shows a memory cell transistor and a ground select transistor constituting a unit memory cell.

Referring to FIG. 10, a plurality of P-wells are formed in the N-well 13 of the substrate. Two P-wells 15 and 17 are shown for simplicity of the figure. In each P-well, unit memory cells UMC including a memory cell transistor MCT and a ground select transistor GST are arranged in a matrix. For the sake of simplicity, 8 rows and 16 columns of unit memory cells are shown in each P-well. Byte select transistors BST are arranged in the N-well 13 between adjacent P-wells 15 and 17. Since byte select transistors BST are formed in the N-well used to separate the P-wells, no additional space is needed for the byte select transistors BST.

Gates of the byte select transistors arranged in each column are connected to each other to form byte select lines BSL0 to BSL3. The gates of the ground select transistors arranged in each row in each P-well are electrically connected to each other to form ground select lines GSL0 to GSL7.

Two adjacent ground select transistors in the column direction share a source to form a common source. Common sources of the same row may be connected to adjacent common sources to form a common source region, and the common source region of each row is electrically connected to the corresponding common source lines CSL0 to CSL3.

In this embodiment, the contact for electrical connection between the common source line and the common source region is located in the region between the memory cell transistors belonging to different bytes in each P-well. Therefore, a separate space is not required for a contact for electrical connection between the common source region and the common source line, and according to the present invention, a memory device having a higher integration can be realized.

Memory cell transistors adjacent in the column direction may share an impurity region (eg, a drain). Memory cell transistors adjacent in the column direction are operatively coupled to the same bit line. When adjacent memory cell transistors in the column direction share a drain, the bit line is electrically connected to the drain.

On the other hand, the control gates of the memory cell transistors arranged in the same row in each P-well are connected to each other in byte units to form a plurality of divided local control lines. In each P-well, the control gates of the memory cell transistors in the first byte unit of each row are connected to each other to form a first local control line, and the control gates of the memory cell transistors in the second byte unit are connected to each other so as to be connected to each other. A second local control line is formed away from the local control line. The first local control line and the second local control line of each row are operatively coupled to different byte selection lines.

For example, in the P-well 13, the control gates of the first byte unit memory cell transistors MCT1_1 to MCT1_8 of the first row are connected to each other to form a local control line LCL1_1, and the second of the first row. The control gates of the memory cell transistors MCT1_9 to MCT1_16 in byte units are connected to each other to form another local control line LCL1_2. Local control lines separated from each other in the same row of each P-well are operatively coupled to different byte select lines. For example, the local control line LCL1_1 of the first row of the first P-well 15 is operatively coupled to the byte select line BSL0, and the local control line LCL1_2 of the first row is the byte select line. Operationally couple to (BSL1).

As mentioned above, the distance between two local control lines apart from each other in each row is smaller than the distance between adjacent P-wells. Therefore, the memory chip size can be further reduced.

For more efficient memory cell placement in this embodiment, two byte select lines are placed between P-wells 15 and 17 that are operatively coupled to local control lines of the P-well adjacent to each other. In addition, adjacent byte select transistors may share a drain, to which a global control line is electrically connected.

The line width of the memory cell transistor may be wider than the line width of the ground select transistor. It is recommended to design the same line width in the manufacturing process, but the line width of the ground select transistor can be formed somewhat larger than the line width of the memory cell transistor in order to realize high integration and prevent leakage current. However, the line width of the memory cell transistors should be as small as possible for high integration. Alternatively, the thickness of the gate insulating film of the ground selection transistor may be increased instead of or at the same time as the design of the line width of the ground selection transistor.

The operation of the program according to the present embodiment will be briefly described. In the program operation according to the present embodiment, the source side (the side where the common source line is connected) of the memory cell transistor (the selected memory cell transistor) to be programmed is plotted, and the selection memory cell transistor is connected to the drain side (the side where the bit line is connected). Apply the same negative voltage (approximately -8 volts) to the formed P-well, conduct a byte select transistor (select byte select transistor) coupled to the selected memory cell transistor, and apply a positive high voltage (about 10 volts) to the global control line. Is applied. Floating on the source side of the select memory cell transistor can be accomplished by plotting a common source line, applying -8 volts to the ground select line and -8 volts to the P-well. The conduction of the select byte select transistor can be achieved by applying about 10 volts to the N-well and about 0 volts to the select byte line. Thus, about 10 volts is applied to the control gate of the selected memory cell transistor, the source side is floated, and -8 volts are applied to the drain side and the P-well so that charge is injected from the P-well into the memory layer of the selected memory transistor.

On the other hand, in order to prevent program disturb by memory cell transistors belonging to the same byte row in the selected P-well to which the selected memory cell transistor belongs, voltages applied to the selected P-well may be applied to unselected bit lines connected thereto. For example, -8 volts), for example an operating voltage of about 2 volts (Vcc). Under these conditions, a high voltage (10 volts) is applied to the control gates of the unselected memory cell transistors because an operating voltage is applied to the drain sides of unselected memory cell transistors of the same byte row of the same P-well as the selected memory cell transistor. Is applied, the capacitive coupling between the impurity diffusion region and the channel does not produce a high voltage difference (about 18 volts) causing FN tunneling of charge between these unselected memory cell transistors and the channel. Therefore, program disturb by memory cell transistors belonging to the same byte of the same P-well as the selected memory cell transistor does not occur.

In addition, in order to prevent program disturb by unselected memory cells belonging to the same P-well as the selected memory cell transistor but belonging to another byte row, a 0 volt voltage is applied to the global control lines coupled to the unselected byte. Select transistors are applied with the same voltage (about 10 volts) as that applied to the N-well. Thus, these unselected memory cell transistors are applied with -8 volts on their drain side and 0 volts on their control gate, or an operating voltage Vcc is applied to their drain side and the control gate is floated. Thus, in either case, there is no high voltage difference between the P-well and the control gate and therefore no program disturb by these unselected memory cell transistors belonging to the other byte row of the same P-well as the selected memory cell transistor.

In addition, in the case of the unselected memory cell transistors of the selected memory cell transistor and other P-wells (unselected P-well), the program may be prevented from occurring in various ways. For example, -8 volts may be applied to an unselected P-well, unselected byte select transistors may be blocked, and a bit line may be floated or an operating voltage may be applied to an unselected bit line. Alternatively, zero volts may be applied to the unselected P-well, the unselected byte select transistors may be blocked, and the unselected bit line may be floated or an operating voltage may be applied to the bit line. In either case, there is no high voltage difference between the unselected memory cell transistors belonging to these other P-wells and the unselected P-well.

In Table 5 below, program operating conditions for the memory cell transistors MCT1_1 of the first row and the first column of the first P-well 15 of FIG. 10 are summarized.

Table 5 (Program Operating Conditions)

Common Source Line (CSL) Byte select line (BSL) Global Control Line (GCL) P-well Bit line BL Ground Select Line (GSL) N-well Floating Apply 0 volt to selected byte select line (BSL0) 10 volts applied to the selected global control line (GCL0) Apply -8 Volts to Selected P-Well 15 Apply a voltage (-8 volts) equal to the voltage applied to the P-well 15 to the selected bit line BL0 Apply a voltage equal to the voltage applied to the selected P-well 15 to the ground selection lines GSL0 to GSL7. 10 volts Apply 10 volts to unselected byte select lines (BSL1 to BSL3) Applying a voltage (0 volt) less than the voltage applied to the selected global control line GCL0 to the unselected global control lines GCL1 to GCL7 -8 Volts or 0 Volts applied to unselected P-well 17 Applying or floating a voltage Vcc higher than the voltage applied to the selected bit line BL0 to the unselected bit lines BL1 to BL31

12 schematically illustrates a program operation condition for a memory cell and a bias state of various memory cells in the memory device according to the present embodiment. Referring to FIG. 12, memory cell A is selectively programmed, adjacent memory cells B belonging to the same byte as memory cell A, byte unit memory cells C of other rows of the same P-well, It can be seen that other byte unit memory cells D of the same row and memory cells E of other P-wells are not programmed.

A byte erase operation according to the present embodiment will be described. Unlike the program operation, the erase operation inverts the polarity of the voltage applied to the control gate of the selection P-well and the selection memory cell transistor. The selection byte selection transistor coupled to the selection byte unit memory cell transistors is turned on, and -8 volts is applied to the selection global control line to apply -8 volts to the control gates of the selection byte unit memory cell transistors. 10 volts is applied to the selected P-well. The conduction of the byte select transistor can be achieved by applying 10 volts to the N-well and applying -10 volts to the gate of the byte select transistor (ie, the select byte select line). The select bit lines coupled to the select memory cell transistors are floated, zero volts are applied to the common source line, and an operating voltage is applied to the select signal sensing line. As a result, the source and drain sides of the selected memory cell transistors are floated, and a high voltage difference is generated between the P-well and the control gate, thereby performing an erase operation.

On the other hand, in order to prevent program disturb by memory cell transistors belonging to another row in the selected P-well to which the selected memory cell transistors belong, the operating voltage Vcc is applied to the unselected global control lines coupled thereto, and the unselected byte Select transistors are applied with a voltage equal to the voltage applied to the N-well (about 10 volts) and shut off. Thus, an operating voltage is applied or floated to the control gates of the unselected memory cell transistors in these select P-wells.

In addition, in the case of the unselected memory cell transistors of the selected memory cell transistor and other P-wells (unselected P-well), the erase operation may be prevented from occurring in various ways. For example, applying zero volts to an unselected P-well, unselected byte select transistors block and float the bit line. As a result, the control gates of the unselected memory cell transistors of the unselected P-well are floated and the unselected P-well becomes 0 volts, so that the erase operation does not occur for these unselected memory cell transistors.

Table 6 below shows the erase operation conditions for the first byte-based memory cell transistors MCT1_1 to MCT1_8 in the first row of FIG. 10.

Table 6 (Erase Operation Conditions)

Common Source Line (CSL) Ground Selection Line (GSL) Byte select line (BSL) Global Control Line (GCL) P-well Bit line BL Signal Sensing Line (SSL) N-well Floating Vcc Accreditation -10 volts on the selected byte selection line (BSL0) -8 volts applied to the selected global control line (GCL0) 10 volts to selected P-well 15 Floating selected bit lines BL0 to BL7 and unselected bit lines BL8 to BL31 Vcc Accreditation 10 volts 10 volts on unselected byte select lines (BSL1 to 3) Unselected global control lines GCL1 to GCL7 Apply or float a voltage Vcc greater than the voltage applied to the selected global control line GCL0. 0 volts in unselected P-well (17)

FIG. 13 schematically illustrates an erase operation condition for a byte unit memory cell A and a bias state of various memory cells in the memory device according to the present exemplary embodiment. Referring to FIG. 13, an erase operation is performed on the memory cells A in a byte unit, other byte units in the same row as the memory cells A, and byte units of another row in the same P-well. It can be seen that the erase operation does not occur with respect to the memory cells C and the memory cells D of other P-wells.

The read operation of this embodiment is the same except that there is no signal sensing transistor and signal sensing line in the memory device described above with reference to FIGS. 1 to 4. That is, the operating voltage Vcc is applied to the selected global control line, 0 volts is applied to the unselected global control line, 0 volts is applied to the selected byte selection line, and the operating voltage is applied to the unselected byte selection line. Apply a positive low precharge voltage to the bit line, float the unselected bit line, apply zero volts to the ground select line, apply an operating voltage to the N-well and zero volts to the P-well.

The method of manufacturing a memory device according to the embodiments of the present invention described above includes the following processes; Formation of active region through device isolation process, well process (N-well process and P-well process), gate insulation process (tunnel insulation process for memory cell transistor, byte select transistor, signal sensing transistor, and gate for ground select transistor) Insulating film process), gate process (first conductive film deposition and patterning process for floating gate of memory cell transistor, inter-gate insulating film process, gate of ground select transistor and signal sensing transistor and control gate of memory cell transistor Film deposition and patterning process), interlayer insulating film process, source / drain process, local interconnection process for electrically connecting the source of the byte select transistor and the control gate of the memory cell transistor, the connection between adjacent signal sensing lines and adjacent ground Local interconnection process for connection between select lines, A common source line forming step and the like.

As already mentioned above, in the case where one P-well includes a divided local control line, a contact for a common source line process is formed in a common source region located between the divided local control lines.

So far, the present invention has been described with reference to the preferred embodiment (s). Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

According to the present invention, since the byte select transistor is formed in the N-well used for P-well separation in which the memory cell transistor is formed, no additional space for the byte select transistor is required, thereby reducing the size of the chip. In addition, a high integration memory device may be implemented.

According to the present invention, by forming the byte select transistor and the memory cell transistor in different conductivity types, it is possible to lower the high operating voltage required for program / erase, to enable low voltage operation, and to reduce power consumption.

According to the present invention, when one P-well includes a divided local control line, memory cells of a byte unit in the same row may be separated without depending on the wells, thereby achieving a higher memory density.

The memory device of the present invention can be usefully applied as a nonvolatile memory of a smart card requiring high security.

Claims (29)

A memory arrangement in which memory cells are arranged in a matrix in a second conductivity type well in a first conductivity type well; And, Byte select transistors formed in the well of the first conductivity type and operatively coupled to the memory cells of the byte unit of the corresponding row; Wherein each row of the memory array comprises at least two sets of byte unit memory cells that are operatively coupled byte by byte to different byte select transistors. In claim 1. The byte select transistors include a first byte select transistor and a second byte select transistor disposed in a well of a first conductivity type on both sides of the well of the second conductivity type, Each row of the memory array comprises a first set of byte unit memory cells operatively coupled to the first byte select transistor and a second set of byte unit memory cells operatively coupled to the second byte select transistor. The method according to claim 1 or 2, And the first conductivity type is n type and the second conductivity type is p type. The method according to claim 1 or 2, And the memory cell has a channel of a first conductivity type and the byte select transistor has a channel of a second conductivity type. The method according to claim 2, Each of the memory cells is: A first bit select transistor, a memory cell transistor, and a second bit select transistor, operatively coupled in series in a column direction, In each row of the memory array, the control gates of the first set of byte unit memory cell transistors are connected to each other to form first local control lines that are operatively coupled to the first byte select transistor, And control gates of the second byte-byte memory cell transistors are connected to each other to form a second local control line operatively coupled to the second byte select transistor. The method according to claim 2, Each of the memory cells is: A memory cell transistor and a bit select transistor operatively coupled in series in a column direction, In each row of the memory array, the control gates of the first set of byte unit memory cell transistors are connected to each other to form first local control lines that are operatively coupled to the first byte select transistor, And control gates of the second byte-byte memory cell transistors are connected to each other to form a second local control line operatively coupled to the second byte select transistor. The method according to claim 5, A bit line operatively coupled to the first bit select transistors in the column direction; A common source line operatively coupled to the second bit select transistors in the column direction; And, And a global control line operatively coupled to the byte select transistors in the column direction. The method according to claim 6, A bit line operatively coupled to the memory cell transistors in the column direction; A common source line operatively coupled to the bit select transistors in the column direction; And, And a global control line operatively coupled to the byte select transistors in the column direction. The memory cell transistor of claim 7 is programmed by F-N tunneling, the program comprising: Applying a negative voltage to the second well, Applying a positive voltage to the selected global control line and applying or plotting a voltage less than the voltage applied to the selected global control line; Conduct the selected byte select transistor, and block the unselected byte select transistor; And, Blocking the second bit select transistor; Conducting the first bit select transistor to apply a voltage equal to a voltage applied to the second well to a selected bit line, and applying a voltage greater than a voltage applied to the selected second well to an unselected bit line; Memory device. The memory cell transistor of claim 7 is erased by F-N tunneling, and the erase is: Applying a positive voltage to the second well, Applying a negative voltage to the selected global control line and applying or plotting a voltage greater than the voltage applied to the selected global control line; Conduct the selected byte select transistor, and block the unselected byte select transistor; And, And blocking the first bit select transistor and the second bit select transistor. The memory cell transistor of claim 8 is programmed by F-N tunneling, the program comprising: Applying a negative voltage to the second well, Applying a positive voltage to the selected global control line, applying a voltage less than the voltage applied to the selected global control line, or applying or floating zero volts; Conduct the selected byte select transistor, and block the unselected byte select transistor; Blocking the bit select transistor; And, And applying a voltage equal to a voltage applied to the second well to a selected bit line, and applying a voltage or an operating voltage greater than the voltage applied to the selected second well to an unselected bit line. The memory cell transistor of claim 8 is erased by F-N tunneling, and the erase is: Applying a positive voltage to the second well, Applying a negative voltage to the selected global control line and applying a voltage greater than the voltage applied to the selected global control line or an operating voltage to the unselected global control line; Conduct the selected byte select transistor, and block the unselected byte select transistor; Blocking the bit select transistor; And, And plotting the bit line. A first well formed in the substrate; A second well formed in the first well; A memory array in which memory cells are arranged in a matrix in the second well, each of the memory cells including a first bit select transistor, a memory cell transistor, and a second bit select transistor of a first conductivity type coupled in series in a column direction; And, And byte select transistors of a second conductivity type formed in said first well to operatively couple to memory cell transistors in corresponding rows. The method according to claim 13, And control gates of the memory cell transistors in each row of the memory array to form a first local control line and a second local control line operatively coupled to different byte select transistors. The method according to claim 13 or 14, Global control lines operatively coupled to byte select transistors each arranged in a row direction; Bit lines each operatively coupled to a first bit select transistor in a column direction; And, And a common source line each operatively coupled to second bit select transistors in a row direction. The memory cell transistor of claim 15 is programmed by F-N tunneling, the program comprising: Applying a negative voltage to the selected second well; Applying a positive voltage to the selected global control line and applying or plotting a voltage less than the voltage applied to the selected global control line; Conduct the selected byte select transistor, and block the unselected byte select transistor; And, Conducting the first bit select transistor to apply a voltage equal to the voltage applied to the selected second well to the selected bit line, and applying a voltage greater than the voltage applied to the selected second well to the unselected bit line. Memory device comprising. The memory cell transistor of claim 15 is erased by F-N tunneling, and the erase is: Applying a positive voltage to the selected second well, Applying a negative voltage to the selected global control line and applying or plotting a voltage greater than the voltage applied to the selected global control line; Conduct the selected byte select transistor, and block the unselected byte select transistor; And, And blocking the first bit select transistor and the second bit select transistor. A first well of a first conductivity type formed in the substrate; A plurality of second wells of a second conductivity type formed apart from each other in the first well, each of the second wells comprising a memory array in which memory cells are arranged in a matrix; And, A first byte selection transistor formed in the first wells on both sides of each of the second wells and operatively coupled to the first byte unit memory cells and the second byte unit memory cells of each row of the memory array of the corresponding second well; And a second byte select transistor. The method according to claim 15, Each of the memory cells is: A first bit select transistor, a memory cell transistor, and a second bit select transistor, operatively coupled in series in a column direction, In each of the memory arrays, control gates of the memory cell transistors of the first byte unit of each row are electrically connected to each other to form a first local control line operatively coupled to the first byte select transistor, and the memory of the second byte unit The control gates of the cell transistors are connected to each other to form a second local control line operatively coupled to the second byte select transistor. The method according to claim 18, Each of the memory cells is: A memory cell transistor and a bit select transistor operatively coupled in series in a column direction, In each of the memory arrays, control gates of the memory cell transistors of the first byte unit of each row are electrically connected to each other to form a first local control line operatively coupled to the first byte select transistor, and the memory of the second byte unit The control gates of the cell transistors are connected to each other to form a second local control line operatively coupled to the second byte select transistor. The method according to any one of claims 18 to 20, And the first conductivity type is n type and the second conductivity type is p type. The method according to any one of claims 18 to 20, And the memory cell has a channel of a first conductivity type and the byte select transistors have a channel of a second conductivity type. The method according to claim 19 or 20, And the distance between the first local control line and the second local control line in each row is smaller than the distance between second wells of an adjacent second conductivity type. The method according to claim 19, And a line width of the gates of the first bit select transistor and the second bit select transistor is wider than that of the control gate of the memory cell transistor. The method of claim 20, And a line width of a gate of the bit select transistor is wider than a line width of a control gate of the memory cell transistor. Forming a memory array in which memory cells are arranged in a matrix in a well of a second conductivity type in a well of a first conductivity type, and Forming byte select transistors formed in the well of the first conductivity type and operatively coupled to the memory cells of the byte unit of the corresponding row; Wherein each row of the memory array comprises at least two byte unit memory cells operatively coupled byte by byte to different byte select transistors. A first well of a first conductivity type formed in the substrate; A plurality of second wells of a second conductivity type formed apart from each other in the first well; Memory cells arranged in a matrix in each of the second wells, each of the memory cells including a memory cell transistor and a bit selection transistor connected in series in a column direction and having different line widths; And, And a byte select transistor operatively coupled to memory cell transistors of a corresponding row in the first well. The method of claim 27, And a line width of the memory cell transistor is smaller than a line width of the bit select transistor. The method according to claim 27 or 28, The gates of the bit select transistors arranged in the row direction in each of the second wells are connected to each other to form a bit select line, and the control gates of the memory cell transistors are connected to each other to form a local control line, And the bit select lines adjacent in the row direction are electrically connected to each other by a local connection line, and a contact between the local connection line and the bit select line is made in the first well.

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