KR100640641B1 - Semiconductor memory device having a stacked memory cell and method for manufacturing a stacked memory cell - Google Patents

Abstract

Disclosed are a semiconductor memory device including a phase change memory cell including a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material, and a method of forming a phase change memory cell. A phase change memory cell according to an embodiment of the present invention includes a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material. The number of the control transistors may be two. A semiconductor memory device according to another embodiment of the present invention is connected to a global bit line, a plurality of local bit lines connected to or blocked by a local bit line selection circuit corresponding to the global bit line, and connected to the respective local bit lines. A plurality of phase change memory cell groups for storing data is provided. As described above, the semiconductor memory device according to the present invention includes a phase change memory cell including a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material, and simultaneously converts a bit line into a global bit line and a local bit line. By dividing the bit line into a hierarchical bit line structure, the density can be improved and the current flowing through the phase change memory cell can be increased.

Description

 Semiconductor memory device having a stacked memory cell and a method of forming a stacked memory cell {Semiconductor memory device having a stacked memory cell and method for manufacturing a stacked memory cell}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a general phase change memory cell.

FIG. 2 is a diagram illustrating a phase change memory array including the phase change memory cell of FIG. 1.

3 is a diagram illustrating a phase change memory cell according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a vertical structure of the phase change memory cell of FIG. 3.

FIG. 5 is a diagram illustrating a phase change memory array of a semiconductor memory device according to an exemplary embodiment of the present invention including the phase change memory cell of FIG. 3.

6A is a cross-sectional view illustrating a structure of a phase change memory cell according to an embodiment of the present invention.

FIG. 6B is a plan view illustrating the structure of the first control transistor of the phase change memory cell of FIG. 6A.

FIG. 6C is a side view of the phase change memory cell of FIG. 6A viewed from the side.

7A is a cross-sectional view illustrating another structure of the phase change memory cell according to the embodiment of the present invention.

FIG. 7B is a plan view illustrating the structure of the first control transistor of the phase change memory cell of FIG. 7A.

FIG. 7C is a side view of the phase change memory cell of FIG. 7A viewed from the side.

7D is a side view illustrating another structure of the phase change memory cell according to the embodiment of the present invention.

FIG. 8A is a diagram illustrating a connection relationship between the substrate and the contact plugs of FIGS. 6A and 7A.

8 (b) is a diagram illustrating a connection relationship between a substrate and contact plugs for reducing contact resistance according to an exemplary embodiment of the present invention.

9A to 9D are cross-sectional views illustrating a method of manufacturing a phase change memory cell according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having stacked memory cells and a method of forming stacked memory cells.

Phase Change Random Access Memory (PRAM) is a phase change material such as a chalcogenide alloy that, when heated and cooled, remains in one of two states and can be changed again by heating and cooling. It is composed. In this case, the two states mean a crystalline state and an amorphous state. PRAM has been described in US Pat. Nos. 6,487,113 and 6,480438. PRAMs have low resistance in the crystalline state and high resistance in the amorphous state. The PRAM has a logic value of 0 or 1 depending on the resistance value. The decision state corresponds to set or logic 0 and the amorphous state corresponds to reset or logic 1.

The phase change material of the PRAM is heated above the melting point of the phase change material by heat of resistance in order to become amorphous. And it cools down quickly. To make the phase change material crystalline, the phase change material is heated to a temperature below the melting point for a period of time.

At the heart of phase change memory is phase change material such as chalcogenide. Phase change materials include germanium (Ge), antimony (Sb), and tellurium (Te), commonly referred to as GST alloys. GST alloys can be useful in memory devices because of their properties that can be quickly changed into an amorphous state (reset or 1) and a crystalline state (set or 0) by heating and cooling.

In the amorphous state, the phase change material has high resistance, and in the crystalline state, the phase change material has low resistance.

The operation of writing data to the memory cell may be performed by heating the calcogenide above the melting point and then rapidly cooling it to an amorphous state, or by heating it to a temperature below the melting point and then maintaining the temperature for a predetermined time and then cooling it. Get into the decision state.

1 is a diagram illustrating a typical phase change memory cell 10, as described in US Pat. No. 5,883,827.

The memory cell 10 includes a phase change variable resistor R1 having one end connected to a bit line and the other end connected to a drain of a select transistor, and a select transistor N1 having a gate connected to a word line and a source connected to a reference voltage. It is provided.

FIG. 2 is a diagram illustrating a phase change memory array including the phase change memory cell of FIG. 1.

Referring to FIG. 2, in the phase change memory array 100, a plurality of phase change memory cells are commonly connected to bit lines, and a sense amplifier (not shown) is connected to each bit line.

Meanwhile, PRAM (Phase Change Random Access Memory), which is recently emerging as a next generation memory, competes with other types of memories, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memories. In order to improve the density is urgently required.

Phase Change Random Access Memory (PRAM) uses a Joule heat to heat a phase change material in order to perform the write operation as described above. In this case, a conventional memory cell is configured to supply a necessary current. There is a limit to the size of the control transistor, which poses a problem for increasing the density.

Therefore, there is an increasing demand for improvement of the structure of a new cell for increasing the degree of integration and the structure of a semiconductor memory device employing the cell.

An object of the present invention is to provide a phase change memory cell with improved degree of integration.

Another object of the present invention is to provide a semiconductor memory device having a phase change memory cell with improved integration.

Another object of the present invention is to provide a method of forming a phase change memory cell with improved integration.

A phase change memory cell according to an embodiment of the present invention for achieving the above technical problem includes a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material. The number of the control transistors may be two.

The control transistors include a first control transistor which is a bulk transistor and a second control transistor which is formed on the first control transistor and is a thin film transistor.

The control transistors may further include a third control transistor formed on the second control transistor. The control transistors may be MOS transistors. The control transistors may form a diode.

The control transistors may be bipolar transistors. The second control transistor may be stacked on the first control transistor. The variable resistance elements may include germanium (Ge), antimony (Sb), and tellurium (Te).

A semiconductor memory device according to another embodiment of the present invention is connected to a global bit line, a plurality of local bit lines connected to or blocked by a local bit line selection circuit corresponding to the global bit line, and connected to the respective local bit lines. A plurality of phase change memory cell groups for storing data is provided.

Each of the phase change memory cells included in the phase change memory cell groups,

A variable resistance element including a plurality of control transistors and a phase change material formed in different layers is provided.

The local bit line selection circuit is a transistor that connects or blocks the local bit line and the global bit line in response to a local bit line selection signal. The control transistors are commonly connected to word lines to which gates correspond.

The semiconductor memory device may further include a peripheral circuit, and the peripheral circuit may be an inverter circuit including a bulk transistor and a thin film transistor formed on the bulk transistor. The bulk transistor may be an NMOS transistor, and the thin film transistor may be a PMOS transistor.

The semiconductor memory device may further include a sense amplifier connected to the global bit line.

A phase change memory cell according to another embodiment of the present invention for achieving the above technical problem is a variable of a plurality of control transistors and phase change material formed in different layers, each gate is commonly connected to a word line A resistance element is provided.

One of the first and second terminals of the control transistors is commonly connected to the variable resistance element and the other is commonly connected to the ground voltage.

In accordance with another aspect of the present invention, a phase change memory cell is formed on a first substrate and includes a first control transistor having a source, a gate, and a drain, and a second substrate formed on the first control transistor. And a second control transistor formed on the second substrate, the second control transistor having a source, a gate, and a drain, and a variable resistance element made of a phase change material connected to one of a source or a drain of the second control transistor.

A source of the first control transistor and a source of the second control transistor are electrically connected, a drain of the first control transistor and a drain of the second control transistor are electrically connected, and a gate of the first control transistor; The gate of the second control transistor is electrically connected.

The first and second control transistors have a planar transistor structure. The first and second control transistors have a Fin Field Effect Transistor (FinFET) structure. The first and second control transistors have a multichannel field effect transistor (McFET) structure.

The second substrate may be formed to be parallel to the first substrate and overlap a portion of an area, and may include a contact plug connecting the variable resistance element and the source or drain of the first control transistor, an external power supply, and the first control transistor. The contact plug connecting the source or drain is formed of an integral conductive layer that is not separated by the second substrate.

The contact plug is connected to the source and the drain of the second control transistor.

According to another aspect of the present invention, there is provided a method of forming a phase change memory cell, including forming a first control transistor having a source, a gate, and a drain on a first substrate, on the first control transistor; Forming a second substrate, forming a second control transistor having a source, a gate and a drain on the second substrate, and a variable resistance element made of a phase change material in one of the source or the drain of the second control transistor It has a step of connecting.

A method of forming a phase change memory cell may include forming a contact plug connecting the variable resistance element and a source or a drain of the first control transistor, and a contact plug connecting an external power source and a source or a drain of the first control transistor. It is further provided.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a phase change memory cell according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a vertical structure of the phase change memory cell of FIG. 3.

Hereinafter, a cell structure of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 to 4. Here, the semiconductor memory device is a phase change memory device having a phase change material.

Referring to FIG. 3, the phase change memory cell 30 according to the embodiment of the present invention includes a plurality of control transistors N31 and N32 formed in different layers and a variable resistance element R3 made of a phase change material. .

A word line WL is connected to gates of the control transistors N31 and N32. First terminals of the control transistors N31 and N32 are commonly connected to a reference voltage, for example, a ground voltage.

The second ends of the control transistors N31 and N32 are commonly connected to the first end of the variable resistance element R3. The second end of the variable resistance element R3 is connected to the bit line BL.

Referring to FIG. 4, the control transistors N31 and N32 are stacked on different layers, respectively. The first control transistor N31 may be a bulk transistor, and the second control transistor N32 may be a thin film transistor. The gate electrode 65 of the first control transistor N31 and the gate electrode 67 of the second control transistor N32 are commonly connected to a word line (not shown).

The source electrode 71B of the first control transistor N31 and the source electrode 69B of the second control transistor N32 are commonly connected to the ground voltage through the contact plug 61. The drain electrode 71A of the first control transistor N31 and the drain electrode 69A of the second control transistor N32 are commonly connected to the landing pad 59 through the contact plug 61.

The landing pad 59 is connected to the phase change layer 55 through the lower electrode 57. The phase change film 55 is connected to the local bit line 51 through the upper electrode 53. The second control transistor N32 is a thin film transistor formed in a silicon epitaxial layer.

The first and second control transistors N31 and N32 may be MOS transistors or bipolar transistors. In addition, the first and second control transistors N31 and N32 may constitute a diode.

According to the exemplary embodiment of the present invention, the degree of integration may be improved by stacking the control transistors N31 and N32 on different layers. That is, the phase change memory cell 30 according to the embodiment of the present invention uses the plurality of control transistors N31 and N32 to increase the current flowing through the variable resistance element R3 and also controls the plurality of control transistors ( The increase in area generated by using N31 and N32 can be reduced by stacking the control transistors N31 and N32.

In addition, when the memory cell 30 further includes a third control transistor (not shown) including the thin film transistor, the degree of integration may be further improved.

FIG. 5 is a diagram illustrating a phase change memory array of a semiconductor memory device according to an exemplary embodiment of the present invention including the phase change memory cell of FIG. 3.

Referring to FIG. 5, a phase change memory array 300 of a semiconductor memory device according to an exemplary embodiment may include a global bit line GBL, a plurality of local bit lines LBL1 and LBL2, and respective local bit lines LBL1. And a plurality of phase change memory cell groups 50 and 70 connected to the LBL2 to store data.

The plurality of local bit lines LBL1 and LBL2 are connected or disconnected by local bit line selection circuits N3 and N5 corresponding to the global bit line GBL. In more detail, the local bit line selection circuits N3 and N5 connect or block the local bit lines LBL1 and LBL2 and the global bit line GBL in response to the local bit line selection signals LBS1 and LBS2. Can be. Here, only two local bit lines LBS1 and LBS2 are illustrated, but the present invention is not limited thereto.

The phase change memory cells 30 and 40 of the phase change memory cell groups 50 and 70 each include a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material. In FIG. 5, seven phase change memory cells included in the phase change memory cell groups 50 and 70 are provided, but the present invention is not limited thereto.

In the first phase change memory cell group 50, the phase change memory cells 30 are connected to the first local bit line LBL1 as shown in FIG. 5. In the second phase change memory cell group 70, phase change memory cells 40 are connected to a second local bit line LBL2.

The first local bit line selection circuit N3 connects the first local bit line LBL1 to the global bit line GBL in response to the first local bit line selection signal LBS1. The second local bit line selection circuit N5 connects the second local bit line LBL1 to the global bit line GBL in response to the second local bit line selection signal LBS2.

The first and second local bit line selection signals LBS1 and LBS2 are signals for selecting memory cell groups in which data is to be stored or read according to an address signal during a data read or write operation.

A sense amplifier (not shown) is connected to the global bit line GBL to amplify the data read from the selected memory cell.

The semiconductor memory device according to the exemplary embodiment of the present invention can supply more programming current to the phase change variable resistance element by forming a memory cell using a plurality of control transistors formed in different layers.

In addition, by implementing a hierarchical bit line structure using the global bit line GBL and the local bit lines LBL1 and LBL2, the memory array may be more compactly implemented.

The semiconductor memory device according to an embodiment of the present invention may further include a peripheral circuit (not shown). The peripheral circuit may be an inverter circuit including a bulk transistor and a thin film transistor formed on the bulk transistor.

The bulk transistor of the inverter circuit may be an NMOS transistor and the thin film transistor may be a PMOS transistor.

As such, when the inverter circuit used for the peripheral circuit is implemented with the NMOS transistor and the PMOS transistor formed in different layers, the integration degree of the semiconductor memory device is further improved. For example, the degree of integration of the semiconductor memory device may be improved by stacking transistors used in the peripheral circuit in the same structure as the phase change memory cell 30 of FIG. 3.

In the present exemplary embodiment, the control transistors constituting the phase change memory cell may be formed in different layers and may be plural in number. Since the control transistor has been described with reference to FIG. 3, a detailed description thereof will be omitted.

The semiconductor memory device of the present invention may be mounted together with a logic chip in a system LSI logic chip.

6A is a cross-sectional view illustrating a structure of a phase change memory cell according to an embodiment of the present invention.

FIG. 6B is a plan view illustrating the structure of the first control transistor of the phase change memory cell of FIG. 6A.

FIG. 6C is a side view of the phase change memory cell of FIG. 6A viewed from the side.

Referring to FIG. 6A, a phase change memory cell 600 according to an embodiment of the present invention is formed on a first substrate 612 and includes a source S1, a gate G11, and a drain D1. A first control transistor N31, a second substrate 614 formed on the first control transistor N31, a second substrate 614 formed on the second control transistor N31, and having a source S2, a gate G21, and a drain D2. And a variable resistance element 616 connected to one of a source S2 or a drain D2 of the second control transistor N32 and the second control transistor N32.

In FIG. 6A, two control transistors are formed on the first substrate 612 and the second substrate 614 for convenience of description, but the first and second substrates 612 and 614 are illustrated in FIG. A plurality of control transistors may be formed.

The phase change memory cell 600 shown in FIG. 6A shows a cross section in the manufacturing process of the phase change memory cell 30 shown in FIGS. 3 and 4.

The source S1 of the first control transistor N31 and the source S2 of the second control transistor N32 are electrically connected. The drain D1 of the first control transistor N31 and the drain D2 of the second control transistor N32 are electrically connected to each other.

Such electrical connection is made by contact plugs CP11, CP21, CP12, CP22. That is, the source S1 of the first control transistor N31 and the contact plug CP11 are connected and the contact plug CP11 is connected to the second substrate 614. The source S2 of the second control transistor N32 and the contact plug CP21 are connected.

Similarly, the drain D1 of the first control transistor N31 and the contact plug CP12 are connected and the contact plug CP12 is connected to the second substrate 614. The drain D2 of the second control transistor N32 and the contact plug CP22 are connected.

Contact plugs CP11, CP21, CP12, CP22 are conductive layers capable of flowing electricity.

The gate G11 of the first control transistor N31 and the gate G21 of the second control transistor N32 are also electrically connected. Although not shown in Figure 6 (a) is also connected by a contact plug. A contact plug connecting the gates G11 and G21 is shown as CP in FIG. 6 (c). I1 shown in Fig. 6A is an insulating material and I2 is a dielectric film.

The first and second control transistors N31 and N32 shown in FIG. 6A have a planar transistor structure. Planner transistors are transistors whose gates are formed on the surface of a substrate. A plan view of a first control transistor N31 as a planner transistor is shown in FIG. Gates G11 and G12 are formed on the wide first substrate 612.

FIG. 6C is a side view of the phase change memory cell 600 of FIG. 6A, in which gates G11 and G21 of the first and second control transistors N31 and N32 are formed on a first substrate. The sidewalls 612 and the second substrate 614 are formed long sideways, and the gates G11 and G21 are electrically connected by the contact plug CP.

The active region ACTIVE, that is, the source and the drain, are formed in the first substrate 612 and the second substrate 614.

7A is a cross-sectional view illustrating another structure of the phase change memory cell according to the embodiment of the present invention.

The phase change memory cell 700 of FIG. 7A has a structure of FIG. 6 except that the first and second control transistors N31 and N32 have a Fin Field Effect Transistor (FinFET) structure. It has the same structure as the phase change memory cell 600 of a).

That is, the first control transistor N31 is formed on the first substrate 712, and the second substrate 714 is formed on the first control transistor N31. The second control transistor N32 is formed on the second substrate 714.

The variable resistance element 716 is connected to the drains of the first and second control transistors N31 and N32 by contact plugs CP12 and CP22. The sources of the first and second control transistors N31 and N32 are electrically connected to each other by the contact plugs CP11 and CP21.

Since the fin field effect transistor has a structure in which gate electrodes exist on both sides of the channel, the channel length of the gate electrode becomes long, and thus a short channel effect can be suppressed.

FIG. 7B is a plan view illustrating the structure of the first control transistor of the phase change memory cell of FIG. 7A.

It can be seen that the size of the first substrate 712 is greatly reduced compared to the first substrate 612 of FIG. 6B by using the fin field effect transistor.

FIG. 7C is a side view of the phase change memory cell of FIG. 7A viewed from the side.

Compared to the side view of FIG. 6C, the fin field effect transistor has a structure in which the gates G11 and G21 surround the active region ACTIVE, so that the channel CH is very long.

The first and second control transistors N31 and N32 may have a multichannel field effect transistor (MFET) structure. A multichannel field effect transistor structure is shown in Fig. 7 (d).

The multichannel field effect transistor structure is similar to the fin field effect transistor structure, but the active region ACTIVE has a structure as shown in FIG. 7 (d) in order to increase the length of the channel CH.

As such, the first and second control transistors of the phase change memory cell according to the embodiment of the present invention may have a planar transistor structure, a fin field effect transistor (FinFET) structure, or multiple A channel field effect transistor (McFET) may have a structure.

FIG. 8A is a diagram illustrating a connection relationship between the substrate and the contact plugs of FIGS. 6A and 7A.

As shown in FIG. 8A, the contact plug CP1 is connected to the first substrate 812, and the contact plug CP1 is connected to the bottom surface of the second substrate 814. In addition, a contact plug CP2 is connected to an upper surface of the second substrate 814. An external power source, for example, a ground voltage may be connected to the contact plug CP2.

However, when the first substrate 812 and the external power source are electrically connected as described above, resistance is generated on the contact surfaces of the contact plugs CP1 and CP2 and the first and second substrates 812 and 814. Therefore, there is a need to reduce the contact resistance.

8 (b) is a diagram illustrating a connection relationship between a substrate and contact plugs for reducing contact resistance according to an exemplary embodiment of the present invention.

The second substrates 614 and 714 of the phase change memory cells 600 and 700 illustrated in FIGS. 6A and 7A are parallel to the first substrates 612 and 712 and overlap a part of an area thereof. Is placed. Description will be made with reference to FIG. 8 (B) for better understanding.

The second substrate 814 is not exactly disposed in the vertical direction in the first substrate 812, but is moved slightly to the right or left in the vertical direction. The contact plug CP is formed of a conductive layer which is not separated from the external power source (not shown) by the second substrate 814 to the first substrate 812.

Therefore, the contact resistance can be greatly reduced. Of course, the contact plug CP is also connected to the second substrate 814 as shown in FIG. 8 (b).

6 (a) and 7 (a), the contact plugs CP12 and CP22 connecting the variable resistance elements 616 and 716 to the drain D1 of the first control transistor N31 are described. And contact plugs CP11 and CP12 connecting the external power source (not shown) and the source S1 drain of the first control transistor N31 to each other, which are not separated by the second substrates 614 and 714. Formed into layers.

9A to 9D are cross-sectional views illustrating a method of manufacturing a phase change memory cell according to an exemplary embodiment of the present invention.

First, a first control transistor including a source, a gate, and a drain is formed on the first substrate 912 (FIG. 9A). An insulating material I1 surrounds the gate G11 and a dielectric film I2 is also formed.

A second substrate 914 is formed on the first control transistor N31 (FIG. 9B). Contact plugs CP11 and CP12 are also formed on the first substrate 912.

A second control transistor N32 having a source, a gate, and a drain is formed on the second substrate 914 (FIG. 9C). Finally, contact plugs CP21 and CP22 are formed and a variable resistance element 916 made of a phase change material is connected to one of a source or a drain of the second control transistor N32 (Fig. 9 (d)).

In the method of manufacturing the phase change memory cell of FIG. 9, the contact plug connecting the source or the drain of the variable resistance element 916 and the first control transistor N31 and the external to form the contact plug as shown in FIG. The method may further include forming a contact plug connecting a power supply and a source or a drain of the first control transistor N31.

Since the structure of the phase change memory cell manufactured by the method of manufacturing the phase change memory cell of FIG. 9 has been described above, a detailed description thereof will be omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device according to the present invention includes a phase change memory cell including a plurality of control transistors formed in different layers and a variable resistance element made of a phase change material, and simultaneously converts a bit line into a global bit line and a local bit line. By dividing the bit line into a hierarchical bit line structure, the density can be improved and the current flowing through the phase change memory cell can be increased.

Claims (43)

A variable resistance element made of a phase change material; And And a plurality of control transistors which control supply / blocking of current to the variable resistance element and are formed in different layers. The method of claim 1, And the number of the control transistors is two. The method of claim 1, wherein the control transistors, A first control transistor which is a bulk transistor; And And a second control transistor formed on the first control transistor, the second control transistor being a thin film transistor. The method of claim 3, wherein the control transistors, And a third control transistor formed over the second control transistor.        The method of claim 4, wherein the control transistors,       A phase change memory cell, characterized in that it is a MOS transistor or a bipolar transistor.        The method of claim 4, wherein the control transistors,        A phase change memory cell comprising a diode. The method of claim 1, wherein the variable resistance elements, A phase change memory cell comprising germanium (Ge), antimony (Sb), and tellurium (Te). Global bitline; A plurality of local bit lines connected or blocked by a local bit line selection circuit corresponding to the global bit line; And A plurality of phase change memory cell groups connected to each of the local bit lines to store data; Each of the phase change memory cells included in the phase change memory cell groups, A variable resistance element made of a phase change material; And And a plurality of control transistors which control the supply / blocking of current to the variable resistance element and are formed in different layers. The circuit of claim 8, wherein the local bit line selection circuit comprises: And a transistor which connects or blocks the local bit line and the global bit line in response to a local bit line selection signal. The method of claim 8, wherein the control transistors, And a gate is commonly connected to a corresponding word line. The method of claim 8, And the number of the control transistors is two. The method of claim 8, wherein the control transistors, A first control transistor which is a bulk transistor; And And a second control transistor formed on the first control transistor and being a thin film transistor. The method of claim 12, wherein the control transistors, And a third control transistor formed on the second control transistor.        The method of claim 13,        And the control transistors are MOS transistors or bipolar transistors.        The method of claim 13,        And the control transistors form a diode.       The method of claim 8,      The variable resistance elements may include germanium (Ge), antimony (Sb), and tellurium (Te). The semiconductor memory device of claim 8, wherein the semiconductor memory device comprises: Further has a peripheral circuit, The peripheral circuit may be an inverter circuit including a bulk transistor and a thin film transistor formed on the bulk transistor. The method of claim 17, And said bulk transistor is an NMOS transistor and said thin film transistor is a PMOS transistor. The method of claim 18, And a sense amplifier connected to the global bit line. A plurality of control transistors, each gate being connected to a word line in common and formed in different layers; And With a variable resistance element made of a phase change material, And one of the first and second terminals of the control transistors is commonly connected to the variable resistance element, and the other is commonly connected to the ground voltage. The method of claim 20, wherein the control transistors, A first control transistor which is a bulk transistor; And And a second control transistor formed on an upper layer of the first control transistor and being a thin film transistor. The method of claim 21, wherein the control transistors, And a third control transistor formed on the upper layer of the second control transistor.        The method of claim 20, wherein the control transistors,       A phase change memory cell, characterized in that it is a MOS transistor or a bipolar transistor.        The method of claim 20, wherein the control transistors,        A phase change memory cell comprising a diode. A first control transistor formed over the first substrate and having a source, a gate, and a drain; A second substrate formed on the first control transistor; A second control transistor formed on the second substrate and having a source, a gate, and a drain; And And a variable resistance element made of a phase change material and connected to one of a source or a drain of the second control transistor. The method of claim 25, A source of the first control transistor and a source of the second control transistor are electrically connected, a drain of the first control transistor and a drain of the second control transistor are electrically connected, and a gate of the first control transistor; And the gate of the second control transistor is electrically connected. The method of claim 25, wherein the first and second control transistors, A phase change memory cell characterized by having a planar transistor structure. The method of claim 25, wherein the first and second control transistors, A phase change memory cell having a Fin Field Effect Transistor (FinFET) structure. The method of claim 25, wherein the first and second control transistors, A phase change memory cell having a multichannel field effect transistor (McFET) structure. The method of claim 25, And wherein the first control transistor is a bulk transistor and the second control transistor is a thin film transistor. The method of claim 25, wherein the second substrate, Parallel to the first substrate and formed to overlap a portion of the area; The contact plugs connecting the variable resistance element and the source or drain of the first control transistor and the contact plugs connecting the external power source and the source or drain of the first control transistor are not separated by the second substrate. A phase change memory cell, characterized in that formed of a conductive layer. The method of claim 31, wherein the contact plug, And a phase change memory cell connected to the source and the drain of the second control transistor. The method of claim 25, The first control transistor and the second control transistor may have different structures selected from a planar transistor, a fin field effect transistor (FinFET), and a multi channel field effect (McFET). A phase change memory cell, characterized in that it has. A method of forming a phase change memory cell, comprising: a variable resistance element made of a phase change material; Forming a first control transistor having a source, a gate, and a drain on the first substrate; Forming a second substrate over the first control transistor; Forming a second control transistor having a source, a gate and a drain on the second substrate; And And coupling the variable resistance element to one of a source or a drain of the second control transistor. The method of claim 34, A source of the first control transistor and a source of the second control transistor are electrically connected, a drain of the first control transistor and a drain of the second control transistor are electrically connected, and a gate of the first control transistor; And a gate of the second control transistor is electrically connected to the phase change memory cell. The method of claim 34, wherein the first and second control transistors, A method of forming a phase change memory cell, characterized by having a structure that is a planar transistor. The method of claim 34, wherein the first and second control transistors, A method of forming a phase change memory cell, characterized in that it has a fin field effect transistor (FinFET) structure. The method of claim 34, wherein the first and second control transistors, A method of forming a phase change memory cell, characterized in that it has a multichannel field effect transistor (McFET) structure. The method of claim 34, And wherein the first control transistor is a bulk transistor and the second control transistor is a thin film transistor. The method of claim 34, wherein the second substrate, And forming a portion parallel to the first substrate and overlapping a portion of the area. The method of claim 40, Forming a contact plug connecting the variable resistance element and a source or a drain of the first control transistor, and a contact plug connecting an external power supply and a source or a drain of the first control transistor, The contact plug, And forming a conductive layer which is not separated by the second substrate. The method of claim 41, wherein the contact plug, And a source and a drain of the second control transistor. The method of claim 34, The first control transistor and the second control transistor may have different structures selected from a planar transistor, a fin field effect transistor (FinFET), and a multi channel field effect (McFET). And a phase change memory cell forming method.

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