KR100640570B1 - Capacitor comprising an electrode formed by using the electroplating and method for manufacturing the same - Google Patents

Abstract

A capacitor having an electrode formed by an electroplating method and a method of manufacturing the same are disclosed. A first conductive layer having a wider width than that of the second conductive layer is provided between the second conductive layer and the conductive plug. This result is obtained by forming the second conductive layer on the seed layer to be the first conductive layer by electroplating, forming a spacer on the side, and then etching the seed layer. The polymer generated during the etching of the seed layer does not adhere to the side of the second conductive layer due to the spacer. In addition, even if the second conductive layer deviates from the alignment margin, the conductive plug may be exposed and the conductive plug may be prevented from being damaged in the process of separating the seed layer by the cell unless the degree is greater than the spacer width.

Description

Capacitor comprising an electrode formed by using the electroplating and method for manufacturing the same

1 is a cross-sectional view of a capacitor using an electroplating method according to an embodiment of the present invention.

2 to 10 are cross-sectional views showing step by step a capacitor manufacturing method according to a first embodiment of the present invention.

11 and 12 are cross-sectional views illustrating only processes that are different from the first embodiment in the capacitor manufacturing method according to the second embodiment of the present invention.

<Code Description of Main Parts of Drawing>

20, 40: substrate 22, 42: interlayer insulating layer

24, 44: contact hole 26: conductive plug

27: lower electrode 28, 30: first and second lower electrodes

32, 60: dielectric layer 34: upper electrode

44: contact hole 46: conductive plug

48: first conductive layer (first lower electrode) 50: insulating layer

52a: Photoresist pattern 54: Mold hole

56: second conductive layer (second lower electrode) 58: sacrificial layer

62: third conductive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device constituting a highly integrated circuit and a manufacturing method thereof, and more particularly, to a capacitor using an electroplating method and a manufacturing method thereof.

As the integration of semiconductor devices increases, high dielectric materials such as BST and PZT are used as the dielectric film of the capacitor to obtain sufficient capacitance to drive the semiconductor devices in a narrow area. ), Heat resistant metal materials such as ruthenium (Ru) and the like are used. However, a heat resistant metal material such as platinum (Pt) is inert and difficult to etch. Therefore, it is a solution to form a capacitor electrode using such a metal material by electroplating.

In the conventional method of forming a capacitor electrode using an electroplating method, an electrode is formed on a seed layer to form a mold defining a region in which an electrode is to be formed. An electrode is then formed by applying electroplating to fill the confined region within the mold with a heat resistant metal material and then removing the mold.

However, in the conventional method, when the electrode is formed, a polymer is generated in the seed layer etching process for separating the electrode by the cell unit, and the electrode is attached to the side of the electrode and the alignment of the electrode is misaligned. There is a problem that the conductive plug connecting the substrate is damaged.

The polymer attached to the side of the electrode is not completely removed even in the subsequent wet process, which is one of the factors that make the subsequent process unstable. Damage to the conductive plug impairs the safety of the electrode and causes contact between the dielectric film and the conductive plug in the dielectric film forming process. This reduces the leakage current characteristics of the capacitor.

Therefore, the technical problem to be achieved by the present invention is to solve the problems of the prior art described above, in order to prevent the polymer from adhering to the side of the electrode in the process of separating the electrode by the cell unit, The present invention provides a capacitor including an electrode formed by electroplating to increase the alignment margin of the electrode in order to prevent the lower conductive plug from being exposed by mis-alignment.

Another object of the present invention is to provide a method of manufacturing a capacitor having an electrode formed by the electroplating method.

In order to achieve the above technical problem, the present invention is formed on the first lower electrode and the first lower electrode covering the substrate, the conductive plug connected to the substrate and the upper surface of the conductive plug, than the first lower electrode A capacitor having a second lower electrode having a narrow cross-sectional area, a dielectric film in contact with the first and second lower electrodes, and an upper electrode formed on the dielectric film is provided.

Another technical object of the present invention is to form an interlayer insulating layer on a substrate, and to form a conductive plug in contact with the substrate on the interlayer insulating layer and a seed in contact with the conductive plug on the interlayer insulating layer. Forming a layer, forming an insulating layer on the seed layer, forming a mold hole in the insulating layer exposing a seed layer covering the conductive plug, and filling a second conductive layer in the mold hole. And removing the insulating layer, separating the seed layer in cell units, separating the seed layer in a wider width than the second conductive layer, and sequentially disposing the dielectric layer and the conductive layer in front of the resultant product in which the seed layer is separated in cell units. It provides a capacitor manufacturing method comprising the step of forming a.

The second conductive layer serves as a second lower electrode and is formed by electroplating.

The separating of the seed layer in cell units may include forming a spacer on a side surface of the second conductive layer, separating the seed layer in cell units by using the spacer and the second conductive layer as an etching mask. And removing the spacer.

The seed layer serves as a first conductive layer and is formed using a material having a high electrical barrier and the dielectric film.

Forming a spacer on a side of the second conductive layer further includes forming a sacrificial layer with a predetermined thickness on the entire surface of the resultant product on which the second conductive layer is formed, and anisotropic dry etching the entire surface of the sacrificial layer. .

The sacrificial layer may be formed using a material having a high etching selectivity with respect to the interlayer insulating layer.

As described above, according to the present invention, after forming a capacitor electrode by electroplating, a spacer is formed on a side of the electrode, and the seed layer is separated into cells by using the spacer and the electrode as an etching mask. Accordingly, the polymer generated in the process of separating the seed layer may be prevented from adhering to the side of the electrode.

In addition, the present invention forms the spacer after the electrode is formed, so that the thickness of the seed layer separated in units of cells can be increased by a method of determining the thickness in consideration of the misalignment of the electrode when forming the spacer. have. Since this increases the area of the seed layer covering the conductive plug, there is an effect of compensating for misalignment of the electrode. In other words, the formation of the spacers allows the formation of electrodes with a wider alignment margin.

Hereinafter, a capacitor having an electrode formed by an electroplating method and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity. In the drawings, like reference numerals refer to like elements.

Referring to FIG. 1, an interlayer insulating layer 22 is formed on a substrate 20. A contact hole 24 through which the substrate 20 is exposed is formed in the interlayer insulating film 22, and the inside thereof is filled with a conductive plug 26. A lower electrode 27 is formed on the interlayer insulating film 22 to contact the entire surface of the conductive plug 26. The lower electrode 27 is composed of a first lower electrode 28 and a second lower electrode 30. The capacitance of the capacitor is determined by the first and second conductive layers 28 and 30, but the effect is larger for the second lower electrode 30. For this reason, the second lower electrode 30 is formed thicker than the first lower electrode 28. The first lower electrode 28 is formed on the interlayer insulating layer 22 and is in direct contact with the entire surface of the conductive plug 26. The second lower electrode 30 is formed on the first lower electrode 28. The second lower electrode 30 is formed on a portion of the region other than the front surface of the first lower electrode 28. As shown in the figure, the width W1 of the first lower electrode 28 is greater than the width W2 of the second lower electrode 30 so that the first lower electrode 28 is formed of the second lower electrode 30. Provide enough space to be formed. In this manner, the first lower electrode 28 may serve as a pad conductive layer with respect to the second lower electrode 30. In the drawing, the distance d between one edge of the second lower electrode 30 and the edge of the first lower electrode 28 adjacent thereto is a distance at which the second lower electrode 30 can be freely moved. The alignment margin of the lower electrode 30 is increased by that amount.

The materials constituting the first and second lower electrodes 28 and 30 are all heat resistant metals. Accordingly, materials constituting the first and second lower electrodes 28 and 30 include ruthenium (Ru), platinum (Pt), ruthenium oxide (RuO ₂ ), strontium ruthenium oxide, and iridium (Ir). The crowd made up is either one chosen. However, the materials constituting the first and second lower electrodes 28 and 30 are not necessarily the same. For example, the material constituting the first lower electrode 28 may be ruthenium, and the material constituting the second lower electrode 30 may be platinum. At this time, the thickness of the first lower electrode 28 is preferably about 500 kPa or less.

Subsequently, the dielectric film 32 is formed on the exposed entire surface of the lower electrode 27. The dielectric film 32 is in contact with the interlayer insulating film 22 exposed between the first lower electrodes 28 as a high dielectric film such as BST or PZT. An upper electrode 34 is formed on the dielectric layer 32. The material constituting the upper electrode 34 is preferably a heat resistant metal similarly to the lower electrode 27, and particularly preferably a material constituting the second lower electrode 30, for example, platinum.

Next, a method of manufacturing a capacitor having the above components will be described.

<First Embodiment>

Referring to FIG. 2, an interlayer insulating layer 42 is formed on the substrate 40. A photoresist pattern (not shown) defining a contact hole forming region is formed on the interlayer insulating layer 42. A contact hole 44 through which the substrate 40 is exposed is formed in the interlayer insulating layer 42 using the photoresist pattern as an etching mask. The contact hole 44 is filled with the conductive plug 46 in contact with the substrate 40. A seed layer 48 is formed on the interlayer insulating layer 42 to cover the entire surface of the conductive plug 46. The seed layer 48 is preferably formed using a material having a high dielectric film and a high electrical potential barrier to be formed in a subsequent process. Therefore, the seed layer 48 is preferably formed using a heat resistant metal material, such as ruthenium (Ru), platinum (Pt), ruthenium oxide (RuO ₂ ), strontium ruthenium oxide and iridium (Ir). It is preferable to form using one of the selected crowds, but it is most preferable to use ruthenium which can maintain excellent properties and relatively easy to etch the high dielectric film. At this time, the seed layer 48 is preferably formed to a thickness of about 500 kPa or less so that the etching can be easily performed later.

Subsequently, an insulating layer 50 is formed on the seed layer 48 and the storage node forming region is defined on the insulating layer 50, that is, a photoresist pattern (exposing the region where the storage node is to be formed and covering the remaining region) 52a). The insulating layer 50 is preferably formed of an oxide film. The region defined by the storage node forming region in the insulating layer 50 is a region formed on the conductive plug 46. Using the photoresist pattern 52a as an etching mask, the exposed region of the insulating layer 50 is anisotropically dry etched until the lower seed layer 48 is exposed. Next, the photosensitive film pattern 52a is removed.

Referring to FIG. 4, the mold hole 54 is filled with the second conductive layer 56. The second conductive layer 56 is preferably formed by an electroplating method as a heat resistant metal layer. Therefore, the second conductive layer 56 is preferably formed using any one selected from a group consisting of ruthenium, platinum, ruthenium oxide, strontium ruthenium oxide, and iridium, and most preferably, it is formed of platinum (Pt). .

Meanwhile, since the second conductive layer 56 is formed on the seed layer 48, the second conductive layer 56 and the seed layer 48 are preferably formed using the same heat resistant metal, but different heat resistant metals are used. It may be formed by.

Subsequently, the insulating film pattern 50a is wet etched. As a result, as shown in FIG. 5, only the second conductive layer 56 remains on the seed layer 48. The second conductive layer 56 is used as the lower electrode of the capacitor.

 Since the width W2 of the second conductive layer 56 is limited at the step of forming the photosensitive film pattern 52a, the height W of the second conductive layer 56 may be increased in order to increase the surface area of the second conductive layer 56 for the purpose of increasing the capacitance of the capacitor. There is no choice but to increase H). As shown in FIG. 4, since the height H of the second conductive layer 56 is determined by the thickness of the insulating layer 50, the insulating layer 50 may be formed to have a desired height. It is preferable to form the thickness which can be. For example, if the height H of the second conductive layer 56 for obtaining the appropriate capacitance is about several thousand to tens of thousands, the insulating layer 50 is also preferably formed to the same thickness.

Referring to FIG. 6, a sacrificial layer 58 covering the surfaces of the seed layer 48 and the second conductive layer 56 is formed. The sacrificial layer 58 prevents exposure and damage of the conductive plug 46, which may be caused by the misalignment of the second conductive layer 56, and occurs during the etching of the seed layer 48 cell by cell. It is formed to prevent the polymeric material from adhering to the side of the second conductive layer 56. Since the former can be prevented as long as the side surface of the second conductive layer 56 is covered with the sacrificial layer 58, the former is not strongly related to the thickness of the sacrificial layer 58. However, the latter is related to the alignment of the second conductive layer 56 and the alignment of the second conductive layer 56 in consideration of the thickness at which the sacrificial layer 58 is to be formed in the step of forming the second conductive layer 56. Since the margin can be determined, it is closely related to the thickness of the sacrificial layer 58. In addition, the sacrificial layer 58 is preferably an etching etchant in which the interlayer insulating layer 42 is not etched in an etching process in which the seed layer 48 is separated in units of cells. Therefore, the sacrificial layer 58 is preferably formed of a polysilicon layer or an aluminum oxide film (Al ₂ O ₃ ). In this case, the sacrificial layer 58 may be formed to be as thick as possible, but the thickness of the sacrificial layer 58 may be about 10 kV to 1,000 kPa in consideration of the narrow gap between the second conductive layers 56 and the side effects caused by excessive etching. .

Subsequently, using the physical etching method, the entire surface of the sacrificial layer 58 is anisotropically etched until the seed layer 48 is exposed. The etching gas used for the anisotropic etching may vary depending on the material forming the sacrificial layer 58. For example, when the sacrificial layer 58 is a polysilicon layer or an aluminum oxide layer, a mixed gas including argon gas (Ar) and chlorine gas (Cl ₂ ) may be used as an etching gas, but the sacrificial layer 58 may be a different material. In some embodiments, the etching gas may be another etching gas or another mixed gas other than the mixed gas including argon gas Ar and chlorine gas Cl ₂ . As a result of the anisotropic etching of the sacrificial layer 58, as shown in FIG. 7, a spacer 58a is formed on the side surface of the second conductive layer 56. Subsequently, the exposed layer of the seed layer 48 is exposed using the second conductive layer 56 and the spacer 58a as an etching mask and a mixed gas containing oxygen gas (O ₂ ) and chlorine gas (Cl ₂ ) as an etching gas. The entire surface is anisotropically etched until the interlayer insulating layer 42 is exposed. The polymer generated at this time is prevented from adhering to the side surface of the second conductive layer 56 due to the spacer 58a formed by the anisotropic etching of the sacrificial layer 58.

Referring to FIG. 8, the seed layer pattern 48a separated in cell units is formed according to the anisotropic etching. The width W1 of the seed layer pattern 48a is wider than the second conductive layer 56 by the width of the spacer 58a. As a result, the alignment margin of the second conductive layer 56 is increased by the width of the spacer 58a. That is, in the absence of the spacer 58a, the alignment margin of the second conductive layer 56 is proportional to the distance d1 between the edge of the conductive plug 46 and the edge of the second conductive layer 56, but the spacer ( If there is 58a, the distance d1 and the width of the spacer 58a are proportional to the combined distance d2, so that the alignment margin of the second conductive layer 56 is increased by the width of the spacer 58a.

Referring to FIG. 9, after forming the seed layer pattern 48a, the spacer 58a is wet etched. The spacer 58a is wet-etched using an etching etchant that does not etch the interlayer insulating layer 42, such as an etching agent for polysilicon and an polymer removal etchant, in sequence. The polymer generated in the process of forming the seed layer pattern 48a and attached to the spacer 58a is also removed while the spacer 58a is removed.

Referring to FIG. 10, after the spacers 58a are removed, the dielectric layer 60 is formed on the interlayer insulating layer 42 to contact the entire surface of the seed layer pattern 48a and the second conductive layer 56. The dielectric film 60 is preferably formed of a high dielectric film such as Ta ₂ O ₅ , Al ₂ O ₃ , BST film or PZT film. Subsequently, a third conductive layer 62 is formed over the entire dielectric film 60. The third conductive layer 62 serves as an upper electrode. In this way, a capacitor in which the lower electrode is formed by electroplating is completed.

Second Embodiment

After forming the second conductive layer 56 according to the first embodiment, as shown in FIG. 11, the sacrificial layer 70 is formed on the entire surface of the second conductive layer 56, but the step coverage is poor. Form under. In this case, the thickness of the sacrificial layer 70 formed as shown in FIG. 11 becomes thicker from bottom to top along the side surface of the second conductive layer 56, and is thinly formed between the second conductive layers 56. In this state, the entire surface of the sacrificial layer 70 is anisotropically etched until the seed layer 48 is exposed. However, even after the sacrificial layer between the second conductive layer 56 is removed and the seed layer 48 is exposed to terminate the anisotropic etching, the second conductive layer 56 may be formed due to the step coverage characteristic of the sacrificial layer 70. The front surface is still covered with the sacrificial layer 70a (FIG. 12). Thereafter, according to the first embodiment, the sacrificial layer 70a formed on the front surface of the seed layer 48 and the second conductive layer 56 is sequentially removed, and the dielectric film 60 is formed on the front surface of the resulting product as shown in FIG. 10. ) And the third conductive layer 62 are sequentially formed.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art may have a larger alignment margin of the second conductive layer 56 by forming the spacer 58a in a double manner. Alternatively, by forming a separate etch stop layer on the interlayer insulating layer 42 before the contact hole 44 is formed, the interlayer insulating layer 42 may not be damaged in the process of removing the spacers 58a. This means that various etching etchant may be used to etch the spacer 58a, and the spacer 58a may be formed of a material layer other than the polysilicon layer or the aluminum oxide film.

As described above, a first lower electrode having a larger planar area than the second lower electrode is provided between the second lower electrode and the conductive plug. This result is obtained by forming the second lower electrode by electroplating on the seed layer which becomes the first lower electrode as a result, forming a spacer on the side, and then etching the seed layer. In this way, the polymer generated during the etching of the seed layer can be prevented from adhering to the side of the second conductive layer.

As shown in FIG. 11, even when the second conductive layer 56 deviates from the alignment margin, the conductive plug may be formed in the process of forming the seed layer pattern 48a unless the extent thereof is greater than the width of the spacer 58a. Exposing the 46 and damaging the conductive plug 46 can be prevented.

Claims (6)

Board; A conductive plug connected to the substrate; A first conductive layer covering an upper surface of the conductive plug; A second conductive layer formed on the first conductive layer and having a narrower cross-sectional area than the first conductive layer; A dielectric film in contact with the first and second conductive layers; And And an upper electrode formed on the dielectric layer. The capacitor of claim 1, wherein the first and second conductive layers are heat-resistant metal layers, and the second conductive layer is an electrode formed by an electroplating method. The capacitor of claim 1, wherein the first and second conductive layers are ruthenium (Ru) and platinum (Pt), respectively. Forming an interlayer insulating layer on the substrate; Forming a conductive plug in the interlayer insulating layer in contact with the substrate; Forming a first conductive layer in contact with the conductive plug on the interlayer insulating layer; Forming an insulating layer on the first conductive layer; Forming a mold hole in the insulating layer to expose a first conductive layer on the conductive plug; Filling a second conductive layer into the mold hole; Removing the insulating layer; Separating the first conductive layer in cell units, but separating the first conductive layer in a wider width than the second conductive layer; And And sequentially forming a dielectric layer and a conductive layer on the entire surface of the resultant product in which the first conductive layer is separated in units of cells. The method of claim 4, wherein the second conductive layer is formed by an electroplating method. The method of claim 4, wherein the separating of the first conductive layer into cells is performed. Forming a spacer on a side surface of the second conductive layer; Separating the first conductive layer in cell units by using the spacer and the second conductive layer as an etching mask; And And removing the spacers.

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