KR100627368B1 - Module and Method for Generating Delayed Clock and Plasma Display Panel Using the Same - Google Patents

Abstract

The present invention relates to a clock delay module, a delay clock generation method, and a plasma display device using the same.

According to the present invention, by using a plurality of delay units for delaying a clock, one delay clock signal is selected from among the plurality of delay units according to each temperature range to generate a delay clock having a stable and accurate timing regardless of temperature. Can be. In addition, since the data can be stably input regardless of the temperature in the system using the DDR memory, the plasma display device can stably display the screen regardless of the temperature.

Clock Delay Modules, Delayed Clock Generation, DDR, Memory Controllers, Plasma Displays

Description

Module and Method for Generating Delayed Clock and Plasma Display Panel Using the Same}

1A and 1B are timing diagrams for inputting data in a DRAM according to the prior art.

2 is a timing diagram when data is input from a DDR RAM according to the prior art.

3 is a timing diagram illustrating a delayed clock used in a DDR RAM according to the prior art.

4 is a schematic diagram of a clock delay module according to an embodiment of the present invention.

5 is a flowchart of a delay clock generation method according to an embodiment of the present invention.

6 is a schematic diagram of a plasma display device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock delay module, a delay clock generation method, and a plasma display device using the same. More particularly, the present invention relates to a clock delay module, a delay clock generation method, and a plasma display device using the same. It is about.

Memory is a storage device capable of storing data, and is widely used in computers, personal digital assistants (PDAs), digital cameras, and plasma display devices.

The memory is divided into a volatile memory in which stored data disappears when the power is turned off, and a nonvolatile memory in which stored data does not disappear even when the power is turned off. Volatile memories include static random access memory (SRAM) and dynamic random access memory (DRAM). Nonvolatile memories include NAND flash memory and NOR flash memory.

The SRAM is a memory that always retains its contents while power is supplied. In general, a single memory device is composed of four transistors, and thus the manufacturing speed is high. However, the DRAM has a high manufacturing cost. As a memory that needs to refresh information periodically, one memory device is generally composed of one transistor, so that the speed is lower than that of the SRAM, but the manufacturing cost is low.

Recently, with the development of technology, DDR (Double Date Rate) memory, which is faster than conventional DRAM, has been developed.

1A and 1B are waveform diagrams for inputting data in a DRAM according to the prior art.

Generally, the DRAM has a rising progress transition (when the clock waveform changes from 0 to 1, a positive-going-transition (PGT) state) or a falling progress transition (clock waveform) as shown in FIGS. 1A and 1B. When the value is changed from 1 to 0, data input / output is executed around Negative-Going-Transition (NGT).

To input data into a PGT type DRAM (DRAM that performs data input / output in the PGT state), a data waveform is input when the clock signal becomes NGT. When a clock signal becomes PGT to input data to the NGT type DRAM, Just enter the data waveform. In this case, the data input is executed without error in the DRAM only when the data input time is correct.

2 is a waveform diagram when data is input from a DDR memory according to the prior art.

In the DDR memory, data input / output is executed not only in the PGT state but also in the NGT state. That is, DDR memory can input and output two data at one clock.

However, in order to input data into such DDR memory, the data input point should be the middle point between PGT and NGT. Therefore, when inputting data into the DDR memory, using a phase locked loop (PLL) or delay locked loop (DLL) module, a quarter (or 4) of one clock as shown in FIG. A clock signal delayed by 3) is generated, and a data waveform is input when the delayed clock signal is in the PGT state or the NGT state.

However, the PLL or DLL module for delaying the clock causes the delay of the output clock to be delayed or accelerated according to the ambient temperature when the input clock is increased. If the clock delay is delayed or accelerated, a time point at which data is input is delayed or faster, resulting in a problem that data input fails.

In addition, a module for delaying such a clock is included in a DDR memory controller for controlling DDR memory, and a DDR memory controller is included in a CPU of a computer or a chipset of a motherboard, and a module for delaying such a clock is provided. If it does not operate properly, the yield of the CPU of the computer or the chipset of the motherboard is reduced.

This problem also occurs in the control unit of the plasma display device using the DDR memory. That is, in the plasma display device, the generated image data is temporarily stored in the DDR memory and then output. When the heat generation in the plasma display device is severe, the input of the image data fails and the image is not displayed correctly. do.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a clock delay module, a delayed clock generation method, and a plasma display device using the same for stably inputting and outputting data regardless of temperature change.

Clock delay module according to a feature of the present invention for achieving the above object,

A plurality of delay units configured to generate clock signals delayed by a predetermined timing based on timing of an input clock; A temperature measuring unit measuring a current temperature; A selection signal generator for generating a selection signal according to the temperature; And a selection unit MUX for selecting and outputting one of the clock signals generated by the plurality of delay units according to the generated selection signal. Here, the delayed clock signal output by the selector is constant regardless of the change in temperature.

Delayed clock generation method according to another aspect of the present invention,

A delayed clock generation method for generating a predetermined delayed clock using an input reference clock, comprising: (a) generating a clock signal delayed by a predetermined timing using a plurality of delay units; And (b) selecting and outputting one of delayed clock signals generated by the plurality of delay units according to the measured temperatures. Here, the delayed clock signal selected in step (b) is characterized in that it is constant regardless of the change in temperature.

Plasma display device according to another aspect of the present invention,

A plasma panel in which discharge cells are formed in an area where a plurality of address electrodes, a plurality of scan electrodes, and a sustain electrode cross each other; A controller configured to generate a control signal for driving the plasma panel by dividing a frame into several subfields by using an input image signal and dividing each subfield into a reset period, an address period, and a sustain period; An address driver configured to apply a voltage to the address electrode according to a control signal generated by the controller; And a scan / hold electrode driver for driving the scan / hold electrode according to a control signal generated by the controller,

The control unit may include: a plurality of delay units configured to generate delayed clocks necessary for temporarily storing a control signal provided to an address driver, and clock signals delayed by a predetermined timing based on timings of input clocks; A temperature measuring unit measuring a current temperature; A selection signal generator for generating a selection signal according to the temperature; And a selector MUX for selecting and outputting one of clock signals generated by the plurality of delay units according to the generated select signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention.

4 is a schematic diagram of a clock delay module according to an embodiment of the present invention.

As shown in FIG. 4, the clock delay module 10 according to the embodiment of the present invention may include the first to fifth delay units 11-15, the temperature measuring unit 16, the selection signal generator 17, and the selection. Part 18 is included.

The first to fifth delay units 11-15 receive a clock signal and generate clocks delayed by a predetermined timing based on the input clock timing. The delay time of the first to fifth delay units 11-15 increases as the temperature increases.

For example, the first to fifth delay units 11-15 may be about 0.8 ns, 0.9 ns, based on the timing of the input clock at operating temperatures (40 ° C. to 60 ° C.) of a general semiconductor chip. A clock signal delayed by 1.0 ns, 1.1 ns, and 1.2 ns is output, and a clock signal delayed by 1 ns is generated based on the timing of the input clock when the temperature T is in the range shown in Table 1 below.

That is, within any temperature range, any one of the first to fifth delay units 11-15 outputs the delayed clock signal as much as desired (in this case, 1 ns).

Each delayed clock signal generated by the first to fifth delay units 11-15 is input to a selector (MUX) 18, which will be described later, and the selector 18 is one of delay clocks. Select and output the signal.

Such first to fifth delay units 11-15 are preferably connected in series. That is, when the first to fifth delay units 11-15 are connected in series, the first delay unit 11 delays the timing by 0.8 ns from the input clock, and the second to fifth delay units ( 12-15) may be designed to each delay by a timing of 0.1 ns. That is, the second to fifth delay units 12-15 may use the same module.

However, when the first to fifth delay units 11-15 receive the respective clocks, the first to fifth delay units 11-15 are 0.8 ns, 0.9 ns, respectively. It should be designed to delay by 1.0 ns, 1.1 ns, 1.2 ns timing.

The first to fifth delay units 11-15 may be manufactured using a buffer, a PLL, a DLL, or a D-flop.

The temperature measuring unit 16 generates temperature data by measuring the temperature of the clock delay module 10, the memory controller, or the memory. The temperature measurement of the temperature measuring section 16 is continuously performed periodically.

The selection signal generator 17 receives the temperature data generated by the temperature measuring unit 16 and generates three bits of data according to the temperature data.

Selection signal generator 17 according to an embodiment of the present invention is a binary number when the current temperature is more than 90 degrees Celsius 000, 60 degrees Celsius or more less than 90 degrees Binary 001, 40 degrees Celsius or more less than 60 degrees 010, 10 degrees Celsius or more and less than 40 degrees Binary 011, less than 10 degrees Celsius generates a binary number 100.

The selector (MUX) 18 receives a binary select signal from the select signal generator 17 and outputs the delayed outputs from the first to fifth delay units 11-15 according to the binary select signal. One clock signal is output from the clock signal.

That is, the selector 18 outputs a delayed clock signal output from the first delay unit 11 when the binary selection signal received from the selection signal generator 17 is 000, and when 001, The delayed clock signal output from the second delay unit 12 is output, and in the case of 010, the delayed clock signal output from the third delay unit 13 is output. In the case of 011, the fourth delay unit 14 is output. The output delayed clock signal is output, and in the case of 100, the delayed clock signal output from the fifth delay unit 15 is output.

For example, the first to fifth delay units 11-15 may be about 0.8 ns, 0.9 ns, based on the timing of the input clock at operating temperatures (40 ° C. to 60 ° C.) of a general semiconductor chip. Clock signals delayed by 1.0 ns, 1.1 ns, and 1.2 ns are output, and clock signals delayed by 1 ns are output based on the timing of the input clock within the temperature T range as shown in Table 1, respectively. The delay module outputs a clock signal delayed by 1 ns based on the timing of the input clock in any temperature range.

In addition, the selector 18 may continuously receive the binary select signal from the select signal generator 17 so as to constantly output a clock signal delayed by 1 ns even when the ambient temperature changes.

The clock delay module 10 may output the clock signal delayed as much as desired within any temperature range by adjusting the number of the delay units and the delay timing of the delay units.

Next, a delay clock generation method will be described with reference to FIG. 5.

First, a plurality of delay units are each adjusted to generate a clock signal delayed by a desired timing (1 ns in the embodiment of the present invention) within various temperature ranges.

For example, each temperature T is adjusted to generate a clock signal delayed by a timing of 1 ns within the range shown in Table 1 above (S100).

Next, the present temperature is measured, and a selection signal is generated according to the temperature. The selection signal is preferably generated in binary, for example, as shown in Table 2 below (S110).

Next, according to the generated selection signal, the clock signal delayed by the desired timing is selected. It is preferable to use the selection unit MUX to select such a delayed clock signal (S120).

Steps S110 and S120 may be repeated periodically to output a constant delay clock regardless of a change in temperature.

Next, a plasma display device using the clock delay module 10 will be described with reference to FIG. 6.

6 is a schematic plan view of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 6, a plasma display device according to an exemplary embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan / hold driver 300, and a controller 400.

The plasma panel 100 includes a plurality of electrodes. The electrodes are arranged in a matrix of m × n. Specifically, address electrodes (hereinafter referred to as 'A electrodes') A1-Am are arranged in a column direction, and n rows of scan electrodes are arranged in a row direction. Hereinafter, 'Y electrode' (Y1-Yn) and sustain electrode (hereinafter referred to as 'X electrode') (X1-Xn) are arranged in a zigzag. Here, the discharge space at the intersection of the A electrodes A1-Am and the X and Y electrodes X1-Xn and Y1-Yn forms a discharge cell.

The address driver 200 receives an address drive control signal from the controller 400 and applies an address pulse for selecting a discharge cell to be displayed to each address electrode A1-Am.

The scan / hold driver 300 receives a control signal from the controller 400 and alternately applies a sustain pulse to the scan electrodes Y1-Yn and the sustain electrodes X1-Xn to perform sustain discharge for the selected discharge cell. .

The controller 400 receives R, G, and B image signals and a synchronization signal from the outside, divides one frame into several subfields, and divides each subfield into a reset period, an address period, and a sustain period to drive the plasma display device. Generate a control signal. The controller 400 generates a control signal for applying an address pulse and supplies the control signal to the address driver 200. In addition, the controller 400 obtains the number of sustain pulses applied in the sustain period of each subfield, generates a control signal accordingly, and supplies it to the scan / maintenance driver 300.

The control unit 400 according to an embodiment of the present invention temporarily stores a control signal provided to the address driver 200 in a DDR memory. In this case, the control unit 400 inputs a control signal to the DDR memory using the clock delay module 10.

The control unit 400 includes an inverse gamma correction unit 410, an error diffusion unit 420, a memory control unit 430, an APC unit 440, and a scan / hold driver 450.

The inverse gamma correction unit 410 maps the n-bit R, G, and B image input data currently input to the inverse gamma curve and corrects the m-bit (m≥n) image signal.

The error diffusion unit 420 error spreads the lower m-n bit image signal to the surrounding pixels from the m-bit image signal inversely gamma corrected by the inverse gamma correction unit 410. The error diffusion is a method of displaying an image by separating an image signal for a lower bit and spreading it to adjacent pixels. A detailed description thereof is described in Korean Laid-Open Patent Publication No. 2002-0014766.

The memory controller 430 generates subfield data corresponding to the gray level of the image signal output from the error diffusion unit 420, and then rearranges the subfield data into address data for driving the plasma display device. Temporary storage in memory (not shown). In this case, the memory controller 430 temporarily stores the address data of all the discharge cells for each subfield in the DDR memory using the clock delay module 10 and then transmits the address data to the address driver 200.

The APC unit 440 calculates an average gray value of the image signal output from the inverse gamma correction unit 420, calculates an APC level according to the average gray value, and maintains the number of sustain pulses in the frame unit corresponding to the APC level ( Number of sustain discharge pulses). In addition, the APC unit 440 calculates the number of sustain pulses in each subfield using the number of sustain pulses in the frame unit.

The scan and sustain drive control unit 450 generates a control signal corresponding to the number of sustain pulses of each subfield calculated by the APC unit 440 and transmits the control signal to the scan and sustain drive unit 300.

As such, when the clock delay module or the delay clock generation method is used, a delay clock with an accurate timing may be generated regardless of temperature.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, it is possible to generate a delay clock having a stable and accurate timing regardless of temperature.

In addition, this allows stable data input regardless of temperature in a system using DDR memory.

In addition, the plasma display device can stably display a screen regardless of temperature.

Claims (10)

A plurality of delay units configured to generate clock signals delayed by a predetermined timing based on timing of an input clock; A temperature measuring unit measuring a current temperature; A selection signal generator for generating a selection signal according to the temperature; And And a selection unit (MUX) for selecting and outputting one of the clock signals generated by the plurality of delay units according to the generated selection signal. The method of claim 1, And a delayed clock signal output by the selector is constant regardless of a change in temperature. The method according to claim 1 or 2, And the temperature measuring unit periodically measures the current temperature. The method according to claim 1 or 2, And the plurality of delay units are connected in series to generate a delayed clock signal. The method according to claim 1 or 2, And the delay unit is a buffer. In the delayed clock generation method for generating a predetermined delayed clock using an input reference clock, (a) generating a clock signal each delayed by a predetermined timing using a plurality of delay units; And (b) selecting and outputting one of delayed clock signals generated by the plurality of delay units according to the measured temperatures. The method of claim 6, And the delayed clock signal selected in step (b) is constant regardless of temperature change. The method according to claim 6 or 7, The plurality of delay units are connected in series to generate a delayed clock signal, characterized in that for generating a delayed clock signal. The method according to claim 6 or 7, And the delay unit is a buffer. A plasma panel in which discharge cells are formed in an area where a plurality of address electrodes, a plurality of scan electrodes, and a sustain electrode cross each other; A controller configured to generate a control signal for driving the plasma panel by dividing a frame into several subfields by using an input image signal and dividing each subfield into a reset period, an address period, and a sustain period; An address driver configured to apply a voltage to the address electrode according to a control signal generated by the controller; And A scanning / holding electrode driver for driving the scan / holding electrode in accordance with a control signal generated by the controller; The control unit may include: a plurality of delay units configured to generate delayed clocks necessary for temporarily storing a control signal provided to an address driver, and clock signals delayed by a predetermined timing based on timings of input clocks; A temperature measuring unit measuring a current temperature; A selection signal generator for generating a selection signal according to the temperature; And a selection unit (MUX) for selecting and outputting one of the clock signals generated by the plurality of delay units according to the generated selection signal.

Images