KR100625911B1 - Clock Control Circuit - Google Patents

Abstract

The present invention provides a clock control circuit that can reduce the circuit scale and eliminate the delay difference in a short time as compared with the case where a PLL circuit or a DLL circuit is used in a circuit that eliminates the delay difference in the entire clock transmission line.

A clock is input from a position on the trailing path 111 of the clock propagation path that returns and inputs an input clock from one stage, and a timing difference between these clocks is input from a position on the trailing path 112 corresponding to the position of the trailing path. And a timing averaging circuit 10 for outputting.

Clock, delay, control circuit, propagation path, timing

Description

Clock Control Circuit

1 is a view showing the configuration of an embodiment of the present invention.

2 is a timing diagram illustrating operation of one embodiment of the present invention.

3 is a diagram showing the configuration of a timing averaging circuit according to an embodiment of the present invention.

4 is a view for explaining the operation of the timing averaging circuit in one embodiment of the present invention;

5 is a diagram showing a configuration of a second embodiment of the present invention.

Fig. 6 is a diagram showing one example of the configuration of the timing averaging circuit in one embodiment of the present invention.

Fig. 7 is a diagram showing one example of the configuration of the timing averaging circuit in one embodiment of the present invention.

Fig. 8 is a diagram showing one example of the configuration of the timing averaging circuit in one embodiment of the present invention.

9 is a diagram showing the configuration of a third embodiment of the present invention.

Fig. 10 is a timing diagram showing the operation of the third embodiment of the present invention.

FIG. 11 is a diagram showing one example of a configuration of a multiplication circuit of the third embodiment of the present invention. FIG.

FIG. 12 is a diagram showing an example of the configuration of the multiphase clock multiplication circuit shown in FIG. 11; FIG.                 

Fig. 13 is a diagram showing an example of the configuration of a four-phase clock multiplication circuit.

14 is a timing chart showing the operation of the four-phase clock multiplication circuit.

FIG. 15 is a diagram showing an example of the configuration of timing difference dividing circuits 208 and 209 of the four-phase clock multiplication circuit of FIG.

Fig. 16 is a diagram showing the configuration of the fourth embodiment of the present invention.

FIG. 17 is a diagram showing the configuration of a timing averaging circuit having a dividing function in a fourth embodiment of the present invention; FIG.

18 is a timing diagram showing the operation of the fourth embodiment of the present invention;

Fig. 19 shows the construction of a fifth embodiment of the present invention.

20 is a timing diagram showing the operation of the fifth embodiment of the present invention;

21 is a diagram showing the configuration of a sixth embodiment of the present invention.

Fig. 22 is a diagram showing an example of the configuration of a conventional clock control circuit.

(Explanation of symbols for the main parts of the drawing)

1: clock 2: divider

3: polyphase clock 4a: timing difference division circuit

4b: multiplexing circuit 5: multiphase clock multiplication circuit

6: cycle detection circuit 7: control signal

8: clock synthesis circuit 10: timing averaging circuit

11: clock full path 12: buffer circuit

13: clock 14: frequency divider circuit                 

15: multiplication circuit 16: synthesis circuit

17: variable delay line 18: phase comparison circuit

100: timing averaging circuit with division function

101: division circuit 110: timing difference averaging circuit

102: timing averaging circuit 111, 114: clock full path

112, 113: buffer circuit 201: 1/4 divider

202: four-phase clock multiplication circuit 203: clock synthesis circuit

204: Period detecting circuit 208 to 215: Timing difference dividing circuit

216 to 223: pulse correction circuit 224 to 227: multiplexing circuit

The present invention relates to a clock control circuit, and more particularly, to a clock control circuit suitable for using a clock supply circuit of a semiconductor integrated circuit having a circuit synchronous with a system lock.

In a semiconductor integrated circuit device which controls internal circuits in synchronism with system lock, the entire internal circuit is controlled by executing a constant circuit operation every clock cycle. In recent years, as the chip size increases due to the high integration of semiconductor integrated circuits and the high functionality, shortening of the delay time difference in the clock path is a problem as the clock cycle is shortened due to the increase in the operating frequency.                         

For example, Japanese Patent Application Laid-Open No. 09-258841 provides a round trip clock wire from a clock source, divides it into two paths back and forth, and wires two paths back and forth. A clock supply method for detecting wiring delay and adjusting a clock is disclosed. A first and second input terminals connected to a first position of the return path and a second position in a predetermined vicinity of the first position of the return path, respectively, and detecting a delay between the return path and the return path from the first and second input terminals; The structure provided with the receiver which outputs the average is disclosed.

That is, in Japanese Unexamined Patent Publication No. 9-258841, for example, as shown in Fig. 22, the A point of the return path _{1 1 1} and the H point of the return path _{1 1 2} are inputted, and the A point is entered. Is input to one end of the phase detection circuit 18 ₁ via the variable delay line 17 ₁ and the variable delay line 17 ₂ , the H point is input to the other end of the phase detection circuit 181, and the phase detection circuit ( 18 ₁ ), based on the phase comparison result of the variable comparison, the delay time of the variable delay lines 17 ₁ , 17 ₂ is variably controlled to adjust the phase, and the output of the receiver at the connection point of the variable delay lines 17 ₁ , 17 ₂ is obtained. (L) is getting.

Since the delay time from the point A to the return point _{1 1 3} of the path _{1 1} of the clock propagation path is a, the delay time from the point A to the point H is 2a. The delay time from point B to return point _{1 1 3} of the path 11 _{1 of the} clock transmission line is 2b, and the delay time from point B to G is 2b. The sum of the delay time to the point (ab) and the delay time from the input to the point G ((ab) + 2b) is

 {(a-b) + (a-b) + 2b} = 2a

When the average is taken, the value is a. Thus, a clock signal having an ordered phase can be obtained without depending on the position of the clock propagation path.

As described above, the conventional method described in Japanese Patent Laid-Open No. 9-258841 returns a clock bus and takes a delay timing in the middle of the round trip path, thereby adjusting the delay amount of the variable delay line in the clock path. will be.

In this adjustment method, the phase difference detection circuit detects the phase difference and changes the delay amount of the variable delay line based on the detected phase difference phase delay loop (PLL) or delay lock loop (DLL). A feedback circuit configuration such as) is generally used.

However, PLLs and DLLs have a feedback circuit, requiring a period of several hundred cycles to several thousand cycles until the clock is stable.

In addition, a plurality of phase comparators, delay circuit trains, and the like are required, and the circuit scale also increases.

Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a clock which can eliminate the delay difference in a short time in a circuit which eliminates the delay difference in the entire clock transmission line, compared with the case where a PLL circuit or a DLL circuit is used. To provide a control circuit.

Another object of the present invention is to provide a clock control circuit which suppresses an increase in circuit scale by eliminating a phase comparator.

According to the first aspect of the present invention, there is provided a first position on a path of a clock propagation path for inputting and returning an input clock from one end (inverting direction), and a second position on a return path corresponding to the first position of the path. A clock control circuit is provided, which comprises a timing division circuit for inputting a clock from and outputting a signal having a delay time corresponding to a time obtained by dividing the timing difference between these two clocks by a predetermined endocrine ratio.

According to a second aspect of the present invention, a clock control circuit inputs and returns an input clock from one end and clocks from a first position of a return path of the clock return circuit and a second position on the return path corresponding to the first position of the return path. A timing averaging circuit for outputting the clock timing difference is divided into two equally as an input.

According to the third aspect of the present invention, the timing averaging circuit outputs an output signal when the first and second input terminals for inputting the two clocks are simultaneously inputted with the clocks of the two clocks which are shifted faster. The output signal is output with a delay time obtained by adding a delay time corresponding to a time T / 2 obtained by dividing the timing difference T between the two clocks equally.

According to the fourth aspect of the present invention, there is provided a first position on a path of a clock propagation path for inputting and returning a clock divided by an input clock into a division circuit from one end, and corresponding to the first position of the path. A timing averaging circuit for inputting a clock from the second home position and dividing the timing difference of these clocks into two equally and a multiplication circuit for multiplying the output of the timing averaging circuit.

According to a fifth aspect of the present invention, a clock control circuit includes a first clock from a first position on a path of a clock propagation path for inputting and returning an input clock from one end, and a first clock of a return path corresponding to the first position of the path. Two clocks of the second clock from the two positions are respectively divided to output a plurality of phase divided clocks having different phases, and the same timing difference of the divided clocks of the corresponding phases that divide the two clocks is equally divided into two. And a synthesizing circuit for synthesizing and outputting a signal having a delay time corresponding to time into one signal.

According to a sixth aspect of the present invention, a clock control method includes a first position on a trailing path of a clock propagation path for inputting and returning an input clock from one end and a second position of a return corresponding to the first position of the trailing path. By averaging the timing difference of the clocks, it is possible to generate a clock whose timing has been adjusted regardless of the position of the round trip path.

Other aspects and features of the invention are as set forth in each claim and are cited herein as required and can be viewed as described herein.

In addition, in the present invention, "return" means to reverse the propagation path direction of the signal.

(Embodiment of the Invention)

Embodiment of this invention is described. According to one preferred embodiment of the present invention, referring to FIG. 1, the first positions A, B, C, and D on the path 11 ₁ of the clock propagation path for inputting and returning an input clock from one end. ) and, and the clock from the forward path (11 _1), the first position (a, B, C, D) a second position (H, G, F, E on the ears (11 ₂₎ corresponding to a) to the input And a timing averaging circuit 10 ₁ , 10 ₂ , 10 ₃ , 10 ₄ which averages and outputs timing differences of these clocks. The delay time between the first position wherein the clock delay time of the turn-around point (11 ₃₎ of the first half path and a turn-around point (11 ₃₎ and the second position of the clock path of the first half is equal to each other, respectively.

In one embodiment of the present invention, in the timing averaging circuit, an output signal is outputted when the clocks of the two clocks which are shifted earlier are simultaneously input to the first and second input terminals for inputting two clocks. The output signal is output with a delay time obtained by adding a delay time corresponding to a time T / 2 obtained by dividing the timing difference T between the two clocks equally. That is, the present invention does not use a PLL or a DLL, and in the timing averaging circuit, an internal node is charged or discharged based on one of the clocks that transitions quickly among the two clocks input, and then, the one clock. The internal node is charged or discharged based on another clock that transitions later and the one clock, the internal node is connected to an input terminal, and the internal node voltage exceeds or falls below a threshold voltage. The circuit has a return or electrostatic buffer circuit for changing the output logic value.

According to one preferred embodiment of the present invention, referring to FIG. 5, an input clock is inputted from one end of the clock propagation path, branched into the paths 11A and 11B of the first and second paths, and then opposed to the one end. Returned from the other end, the return paths 11C and 11D of the returned first and second paths are provided along the paths 11B and 11A of the second and first paths, respectively, and the path 11A of the first path. The timing difference between these first clocks A and B and the clocks from the second positions H and G of the return path 11D of the second path corresponding to the position of the return path are input. A timing averaging circuit 10 ₁ , 10 _{2 for} averaging and outputting the third path, the third positions E and F on the path 11B of the second path, and the return path of the second path corresponding to the position of the path. The timing average which inputs the clock from the 4th position D and C of 11C, and averages and outputs the timing difference of these clocks. Sum circuits 10 ₄ and 10 ₃ are provided.

According to one preferred embodiment of the present invention, referring to FIG. 9, a divider circuit 14 for dividing an input clock is provided, and a clock propagation path for inputting and returning a clock divided by the divider circuit 14 from one end is provided. The timing difference between the clocks from the first positions A, B, C, and D on the path and the second positions H, G, F, and E on the path corresponding to the position of the path are input. the average to the timing of outputting the averaging circuit (10 _1, 10 _2, 10 _3, 10 _4), and a timing averaging circuit multiplication to each multiplier output (10 _1, 10 _2, 10 _3, 10 ₄₎ a circuit (15 ₁ , 15 ₂ , 15 ₃ , 15 ₄ ).

According to one preferred embodiment of the present invention, referring to FIG. 16, the first positions A, B, C, and D on the path _{1 1 1} of the clock propagation path for inputting and returning an input clock from one end, and Timing averaging circuit (100 ₁ , 100 ₂ , 100 ₃ , 100 ₄ ) having a division function for inputting two clocks from the second position (H, G, F, E) of the return path corresponding to the position of the return path And output one divided output signals L1 to L4, K1 to K4, J1 to J4, and I1 to I4 respectively output from the timing averaging circuits 100 ₁ , 100 ₂ , 100 ₃ , and 100 ₄ having a frequency division function. Synthesis circuits 16 ₁ , 16 ₂ , 16 ₃ , 16 ₄ are synthesized.

The timing averaging circuit having a division function divides two clocks and outputs a plurality of phase division clocks having different phases from each other, and the first and second division circuits 101 ₁ and 101 ₂ , and the first and second division circuits 101. A plurality of timing averaging circuits 102 ₁ , 102 ₂ , 102 ₃ , 102 ₄ for inputting two divided clocks of corresponding phases of ₁ , 101 ₂ and outputting a signal obtained by averaging timing differences; And a synthesizing circuit 16 for synthesizing and outputting the outputs L1, L2, L3, L4 of the circuits 102 ₁ , 102 ₂ , 102 ₃ , 102 ₄ into one signal.

According to one preferred embodiment of the present invention, referring to FIG. 19, a divider circuit 14A for dividing an input clock and outputting a plurality of phase divided clocks having different phases from each other, and a plurality of divided outputs outputted from the divider circuit 14A. Regarding each of the plurality of clock propagation paths 11-1 to 11-4 which inputs and returns a clock from one end, two clocks from any position on the path and the return path corresponding to the position of the path A plurality of timing averaging circuits (four TMs) serving as inputs and a synthesizing circuit 16 for synthesizing and outputting outputs from the plurality of timing averaging circuits (four TMs) into one signal are provided.

According to one preferred embodiment of the present invention, referring to FIG. 21, the first positions A, B, C, and D on the path of the first clock propagation path 111 for inputting and returning an input clock from one end, and a second position timing averaging circuits (110 ₁ to 110 ₄₎ for the two clock input from the (H, G, F, E) of the ear corresponding to the position of the forward path, the timing averaging circuit (110 ₁₎ A timing averaging circuit for inputting a position of a second clock propagation path 114 ₁ on which a clock outputted from one end is returned, and two clocks from a return position corresponding to the position of the return path (120 ₁ to 120 ₄ ).

Further, a position on the path of the second clock propagation path 114 ₂ that inputs and returns the clock output from the timing averaging circuit 110 ₂ from one end and ₂ from the position of the return path corresponding to the position of the path. A timing averaging circuits 121 ₁ to 121 ₄ having two clocks as inputs, and on a path of the second clock first path 114 _{3 for} inputting and returning a clock outputted from the timing averaging circuit 110 ₃ from one end; any position and, a clock that is provided, and the output from the timing averaging circuit (110 ₄₎ a timing averaging circuit (122 ₁ to 122 ₄₎ for the two clock from the ear corresponding to the position of the forward position as the input The second clock propagation path 114 ₄ , which is inputted from one end and returned from the position of the return path corresponding to the position of the return path, and the two clocks Timing averaging circuits 123 ₁ to 123 ₄ serving as inputs are provided. The output signals of these timing averaging circuits are provided, for example, in a mesh shape in the two-dimensional plane of the semiconductor integrated circuit (or printed wiring board).

Next, some of the circuit configurations will be described with respect to the timing averaging circuit. In one embodiment of the present invention, in the timing averaging circuit which inputs the clock at two points of the return type clock propagation path and the return path, the first power supply VCC and the internal node N1 are referred to as shown in FIG. First and second switch elements MP1 and MP2 connected in parallel to each other, being turned on when the first input IN1 and the second input IN2 are respectively the first value, and turned off when the second input is the second value. ) And an output of a logic circuit NOR1 connected between the internal node N1 and the second power supply GND, the input of the first input and the second input being input to a control terminal, and the first input. The third switch element MN1 which is turned on when the input and the second input are the second value, the capacitance C connected between the internal node N1 and the second power source GND, and the internal node ( A buffer circuit BUF is provided in which the output logic value is determined by the magnitude of the potential of N1) and the threshold value.

In one embodiment of the present invention, in the timing averaging circuit, referring to FIG. 6, the first power supply VCC and the internal node N52 are connected in series, and the first input IN1 is connected to the control terminal. The first input IN1 is connected in series between the plurality of first switch elements MP51 and MP52 that are turned off when the first input IN1 is the first value, and between the internal node N52 and the second power source GND. ) Is connected to the control terminal and is inserted in series between the plurality of second switch elements MN51 and MN52, which are turned on when the first input IN1 is the first value, and the first power supply and the internal node N52. A third switch element MP53 and a second input IN2 connected to a control terminal, wherein the first input IN1 is connected to a control terminal, and is turned off when the first input IN1 is a first value. And is connected in series between the fourth switch element MP54 and the internal node N52 and the second power supply which are turned off when the second input IN2 is the first value. The first switch IN1 is connected to the control terminal, the fifth switch element MN54 that is turned on when the first input is the first value, the second input is connected to the control terminal, and the second input is connected to the control terminal. The sixth switch element MN53 is turned on when the first value is the first value, and the inverter circuit INV51 is provided in which the output logic value is determined by the magnitude of the potential of the internal node N52 and the threshold value. The switch elements MP55 and MP56 having the second input connected to the control terminal are connected to the first power supply, and the switch elements MN55 and MN56 having the second input connected to the control terminal are connected to the second power supply side. And the number of switch elements used as the load of the said 1st, 2nd input is made into the same number.

In one embodiment of the present invention, in the timing averaging circuit, referring to FIG. 7, the first switch element MP61 connected between the first power source VCC and the first internal node N71, and the first and second ones. The first switch element is input when the input signals IN1 and IN2 are inputted at the input terminal, and the output terminal is connected to the control terminal of the first switch element MP61, and both the first and second input signals have a first value. Connected in series between a first logic circuit NAND61 for turning on and the first internal node N71 and a second power source GND, and turned off / on when the first input signal is a first / second value; The second switch element MN61, the third switch element MN62 that is turned on / off when the value of the output signal OUT is the first / second value, the first internal node N71 and the second power source. A fourth switch element MN63 connected in series between each other and turned off / on when the second input signal is a first / second value, and an output signal OU; And a fifth switch element MN64 that is turned on / off when the value of T) is a first / second value, and is also connected between a first power source and a third internal node N73, and the first internal node. The sixth switch element MP66 for inputting N71 to the control terminal is provided.

The seventh switch element MN65 connected between the second power source GND and the second internal node N72 and the first and second input signals IN1 and IN2 are inputted, and the seventh switch element MN65 is input. A second logic circuit (NOR61) for turning on the seventh switch element (MN65) when the output is connected to a control terminal of the first and second input signals (IN1, IN2) at a second value, and the second, The eighth switch element MP64 connected between the internal node N72 and the first power supply VCC and turned on / off when the first input signal is a first / second value, and the value of the output signal OUT. A ninth switch element MP62 that is turned off / on when the first / second value is the same, and is connected between the second internal node N72 and the first power supply VCC, and the second input signal is connected to a first signal. A tenth switch element MP65 that is turned on / on when the second value is a second value; an eleventh switch element that is turned off / on when the value of the output signal OUT is the first / second value; Third internal node A twelfth switch element (MP63) connected between the first and second internal nodes to a control terminal, the third internal node is input to an input terminal, and the third internal node potential and the threshold are large and small. Inverter circuit INV65 is provided, whereby an output logic value is determined, and an output signal is output from an output terminal of the inverter circuit. A first pair of switch elements comprising the third switch element MN65 and the fifth switch element MN64 and the ninth switch element based on the first and second input signals IN1 and IN2; And circuit means for controlling the on / off control of the second pair of switch elements including the MP62 and the eleventh switch element MP63.

The circuit means includes, for example, inverter circuits INV67 and INV66 for generating an electrostatic signal of an output signal defined by the first and second input signals IN1 and IN2. It is commonly connected to the 3rd switch element MN65, the 5th switch element MN64, the 9th switch element MP62, and the control terminal of the 11th switch element MP63.

In one embodiment of the present invention, in the timing averaging circuit which receives clocks from two points of the return type clock propagation path and the return path as inputs, referring to FIG. 8, between the first power supply and the first internal node N81. The first switch element MP71 to be connected and the first and second input signals IN1 and IN2 are inputted at an input terminal, and an output terminal is connected to the control terminal of the first switch element. A first logic circuit NAND71 for turning on the first switch element MP71 when the inputs are all at a first value, and second and third switch elements connected between the first internal node N81 and a second power source; MN71 and MN72, and the second switch element MN71 is turned off / on when the first input signal IN1 is a first value / second value, and a first internal node N81 and the second power source. And fourth and fifth switches MN73 and MN74 connected between the fourth and fifth switch elements MN73. The second input signal is on-off / when the first / second value. A sixth switch element MP76 connected between the first power source and the third internal node N83 and inputting the first internal node N81 to the control terminal is provided.

The seventh switch element MN75 connected between the second power source GND and the second internal node N82 and the first and second input signals IN1 and IN2 are inputted to the seventh switch element MN75. And a second logic circuit NOR71 and a second internal node N82 which turn on the seventh switch element MN75 when the output is connected to the control terminal of the control panel and the first and second inputs are both at the second value. An eighth switch element and an ninth switch element MP74 and MP72 connected between a first power source, wherein the eighth switch element MP74 is turned on when the first input signal IN1 has a first / second value; A tenth switch element and an eleventh switch element MP75 and MP73 which are turned on / off and connected between a second internal node N82 and the first power source, and the tenth switch element MP75 is connected to the second power source. On / Off when the input signal is the first / second value, connected between the second power source and the third internal node N83, control the second internal node Inverter circuit INV75 which inputs the 12th switch element MN76 and the said 3rd internal node to an input terminal, and an output logic value is determined by the magnitude of the potential of the said 3rd internal node N83, and the threshold value. ).

The output of the first logic circuit NAND71 is commonly connected to the control terminals of the ninth switch element and the eleventh switch elements MP72 and MP7 3, and the output of the second logic circuit NOR71 is connected to the third switch element and the fifth. It is commonly connected to the control terminal of the switch element MN7 MN73.

In one embodiment of the present invention, an example of the configuration of the multiplication circuits 15 ₁ , 15 ₂ , 15 ₃ , 15 ₄ that multiplies the output clocks of the timing averaging circuits 10 ₁ , 10 ₂ , 10 ₃ , 10 ₄ is an example. For example, referring to FIG. 11, a divider 2 for dividing a clock to generate a multiphase clock, a cycle detection circuit 6 for detecting a clock cycle, and a clock output of the divider 2 are input. A plurality of multi-phase clock multiplication circuits 5 for generating a multi-phase clock multiplied by the clock and a clock synthesizing circuit 8, wherein the multi-phase clock multiplication circuits output a signal obtained by dividing a timing difference between two inputs; The timing difference division circuit 4a and the multiplexing circuit 4b which multiplexes the output of two timing difference division circuits, The said timing difference division circuit is a timing difference division circuit which inputs the clock of the same phase. And two clocks of neighboring phases as inputs And a timing difference division circuit.

In one embodiment of the present invention, the multi-phase clock multiplication circuit inputs n-phase clocks (first to n-th clocks) and outputs a signal obtained by dividing a timing difference between two inputs with reference to FIG. The timing difference dividing circuit is provided, and the timing difference dividing circuits 208, 210, 212, and 214 of the 2I-1 < th > The timing difference dividing circuits 209, 211, 213, and 215 of the 2I-th (where 1≤I≤n) are the I-th clock and the (I + 1 mod n) -th (where I + 1 mod n is The output of the J-th (where 1≤J≤2n) and (J + 2n pulse width correction circuits 216 to 223 which input the output of the timing difference division circuit of 2 mod n) th (where J + 2 mod n is the remainder of J + 2 divided by n), and K th ( However, 1≤K≤n) pulse width correction circuit And having an output and (K + n), n of the multiplexing circuit to the output of the second pulse width correction circuit to the input (224 to 227).

In one embodiment of the present invention, when the timing difference dividing circuit uses the first and second input signals as inputs and the first and second input signals have a first value, the internal node is supplied with a potential of the first power supply. And a buffer circuit or inverter circuit INV15 for changing the output logic value by the magnitude of the potential and the threshold value of the internal node which is the output of the logic circuit, and the logic circuit NOR14 set to N, and the internal node and the second power supply. A plurality of switch elements and capacitors connected in series are connected in parallel to each other (MN51 and CAP51, MN52 and CAP52, MN53 and CAP53), and the capacitance is added to the internal node as a periodic control signal connected to the control terminal of the switch element. It is configured to determine.

By providing a clock control circuit according to an embodiment of the present invention in a semiconductor integrated circuit device and supplying a clock to a clock synchronous circuit, it is possible to supply a clock whose phase is aligned over the entire clock path.

(Example)                     

BRIEF DESCRIPTION OF DRAWINGS To describe the above embodiments of the present invention in more detail, embodiments of the present invention will be described below with reference to the drawings.

1 is a diagram showing the configuration of one embodiment of the present invention. As shown in Fig. 1, in one embodiment of the present invention, in a circuit for adjusting a delay in a clock path by returning a clock-wide path and taking an intermediate timing of the round trip path, each pulse of the clock signal And a timing averaging circuit for averaging the timing difference between them.

On the path (11 ₁ ) of the clock propagation path,

Delay time a from point A to return point 1 1 ₃ ,

Delay time from point B to return point 1 1 ₃ b,

Delay time from point C to return point 1 1 ₃ c,

Delay time from point D to return point 1 1 ₃ ,

On the return path 1 _{1 2} of the clock propagation path,

E point is time delayed from the turn-around point (11 ₃₎ d,

F point is delay time c from return point 1 1 ₃ ,

G is a point of time delayed from the turn-around point (11 ₃₎ b,

H point of time delayed from the turn-around point (11 ₃₎ a,

It is.

The clock input from the input buffer 12 to the path _{1 1 1} of the clock propagation path is returned at the return point _{1 1 3} , is propagated to the return path _{1 1 2} , and two clock signals, A and H points are timingd. Inputted to the averaging circuit 10 ₁ , an output signal L having an average delay time of two timing differences is output, and two clock signals of point B and G are input to the timing averaging circuit 10 ₂ . The output signal K of the average delay time of two timing differences is output, two clock signals of the point C and the F are input to the timing averaging circuit 10 ₃ , and the average delay of the two timing differences is input. The output signal J of time is output, two clock signals of the point D and the E are input to the timing averaging circuit 10 ₄ , and the output signal I of the delay time of the average of the two timing differences is output. do.

FIG. 2 is a timing diagram showing the basic operation of one embodiment of the present invention shown in FIG. Clock overall path is arranged to return 1, the path of the outgoing path of each point (11 ₁₎ (A, B, C, D), the ear path (11 ₂₎ of each point (E, F of the , G, H) is input to the clock output timing averaging circuits (10 ₁ to 10 ₄₎ adjacent, respectively, the timing averaging circuits (10 ₁ to 10 ₄₎ from the timing with a median value component of the timing difference of two clock Is output.

The output of each of the adjacent points (AH, BG, CF, DE) median value of the timing difference (2a, 2b, 2c, 2d ) is correctly, the turn-around point (11 _3), each of the timing averaging circuit (1), since the same as the timing of the in I, J, K, and L are output at the same timing.

That is, in FIG. 2, the timing of the rising edge of the output L of the timing averaging circuit 10 ₁ is the average value of the timing difference 2a of the adjacent point AH with respect to the rising edge of the clock of the point A. In FIG. , (Constant delay time Cons) + (2a / 2) = Cons + a. The constant delay time Cons is a propagation delay time inherent in the timing averaging circuits 10 ₁ to 10 ₄ . More specifically, the constant delay time Cons is a propagation delay time between inputting the same signal to two inputs of the timing averaging circuit and outputting the output signal.

The output K of the timing averaging circuit 10 ₂ , which inputs the clock at the adjacent point BG, adds the constant delay time Cons + 2b / 2 to the delay time ab to the adjacent point B. It rises after one delay time and rises after Cons + a from the rising edge of the clock at point A. The output J of the timing averaging circuit 10 ₃ and the output I of the timing averaging circuit 10 ₄ also rise after Cons + a from the rising edge of the clock at point A, so that the signals I, J, K, The timing of the rising edge of L) is trimmed.

3 and 4 are diagrams for explaining the principle of the timing averaging circuit 10 according to an embodiment of the present invention. In addition, the timing averaging circuit sets the timing difference T between the two signals to be input to a timing difference dividing circuit (also referred to as an "interpolator") that outputs an output signal corresponding to the delayed delay time at a predetermined ratio (a). Therefore, endocrine a is set to 0.5, and the timing difference is equally divided to output. The timing averaging circuit shown in FIG. 1 is constituted by a timing difference dividing circuit.

As shown in Fig. 3A, the timing difference dividing circuit TMD includes inverters INV1 and INV2 for returning and outputting input signals IN1 and IN2, and a source is connected to a power supply VCC, and a gate Is connected to the outputs of the inverters INV1 and INV2, the drain is connected to the internal node N1, and the internal node N1 is connected to the input terminal, and the internal node N1 is connected to the internal node N1. Buffer circuit BUF for changing the output logic value when the potential of the transistor exceeds or falls below the threshold voltage, and the NOR circuit NOR1 for inputting the input signals IN1 and IN2 and outputting the NOR operation result. The N-channel MOS transistor MN1 and the internal node N31 having a drain connected to the internal node N1, a source connected to a ground potential GND, and a gate connected to an output terminal of the NOR circuit NOR1. The capacitor C is connected between the ground and the ground.

Here, the timing difference dividing circuit TMD is shown in the block diagram shown in Fig. 3B. Further, as described above, the timing averaging circuit outputs an output signal corresponding to a delay time obtained by averaging the timing difference of the input signal with the endocrine ratio of the timing difference dividing circuit being 0.5.

Referring to FIG. 4 (c), in the three timing difference dividing circuits TMD, the same input signal IN1 is input to the two inputs in FIG. 4 (c) to output the output signal OUT1, and the second Input signals IN1 and IN2 are input to the timing difference dividing circuit TMD to output the output signal OUT2, and the same input signal IN2 is input to the two inputs to the third timing difference dividing circuit TMD. Output the output signal OUT3. Among these, the second timing difference dividing circuit TMD for inputting the input signals IN1 and IN2 and outputting the output signal OUT2 corresponds to the configuration of Fig. 3A. In addition, as a circuit structure provided with the 1st thru | or 3rd timing difference division circuit TMD shown in FIG.4 (c), the structure shown in FIG.13 (a) is referred, for example.

Referring to FIG. 4 (d), there is a timing difference T between the input signal IN1 and the input signal IN2, and the first timing difference dividing circuit TMD outputs the output signal OUT1 of the delay time t1. And the third timing difference dividing circuit TMD outputs the output signal OUT3 of the delay time t3, and the second timing difference dividing circuit TMD outputs the output signal OUT2 of the delay time t2. The delay time t2 is a value obtained by dividing the delay times t1 and t3 (internal).

Referring to FIG. 3A again, when the input signals IN1 and IN2 are at the low level, the output of the NOR circuit NOR1 is at a high level, and the N-channel MOS transistor MN1 is turned on. The potential of the node N1 becomes the ground potential, and the output of the buffer circuit BUF becomes the low level.

Assuming that the threshold voltage returned by the output of the buffer circuit BUF to a high level is V, in FIG. 3A, when the same input signal IN1 is input to the two input terminals IN1 and IN2, the input signal is input. When IN1 rises, the outputs of the inverters INV1 and INV2 are at a low level, both the P-channel MOS transistors MP1 and MP2 are turned on, the N-channel MOS transistor MN1 is turned off, and the drain current i1 If the node N1 is charged to i2), and the charge of the node N1 that needs to be charged to the place where the threshold of the buffer circuit BUF is reached is CV (where C is capacitance and V is voltage).

 t1 = CV / (il + i2)                     

Is given by

In Fig. 3A, when the input signals IN1 and IN2 (the time T rises later from the input signal IN1) are input to the two input terminals IN1 and IN2 (Fig. 4 (c)). ), When the input signal IN1 rises, the output of the inverter INV1 becomes low level, only the P-channel MOS transistor MP1 is turned on, the N-channel MOS transistor MN1 is turned off, and the drain current i1 is turned off. When the low node N1 is charged for T time (the charge i1T of the node N1), and subsequently the input signal IN2 rises, the output of the inverter INV2 becomes low level and the P-channel MOS transistor ( Both MP1 and the P-channel MOS transistor PM2 are turned on, the N-channel MOS transistor MN1 is turned off, the node N1 is charged with the drain current i1 + i2, and the buffer circuit BUF If the charge of the node N1 that needs to be charged to reach the threshold is CV (where C is the capacitance and V is the voltage),

 t2 = T + (CV-i1T) / (i1 + i2)

 = T + CV / (il + i2) -ilT / (il + i2)

 = T (i2 / (il + i2)) + t1

When the drain currents i1 and i2 of the P-channel MOS transistors MP1 and MP2 are the same,

 t2 = (1/2) T + t1

3A, when the same input signal IN2 (the time T is delayed from the input signal IN1) is input to the two input terminals IN1 and IN2,

 t3 = T + CV / (il + i2)

Becomes

In this manner, the time T (two times) of the P channel MOS transistor MP1 for first inputting the input signal IN1 to the capacitance C of the internal node N1 of the timing difference dividing circuit shown in Fig. 3A. Charges during the timing difference of the input clock), and then charges with two P-channel MOS transistors in combination with the P-channel MOS transistor MP2 which inputs the input signal IN2 as an input, thereby simultaneously providing the same input signal IN1. The time difference of T / 2 (the average value of the timing difference T between the input signals IN1 and IN2) is determined from the time t1, compared to charging with the two P-channel MOS transistors MP1 and MP2 by inputting To produce.

For this reason, this timing difference division circuit is called a "timing averaging circuit."

According to the present invention, the delay time difference in the clock path 11 can be kept low without using a PLL circuit or a DLL circuit.

In the timing averaging circuit, a P-channel MOS of Fig. 3 (a) is used when outputting a signal obtained by averaging the timing difference by dividing the timing difference between the clock of the first transition and the clock of the late transition by 1/2. This is realized by making the on currents (drain currents) i1 and i2 of the transistors MP1 and MP2 equal. In this case, by setting the ratio of the on currents (drain currents) i1 and i2 of the P-channel MOS transistors MP1 and MP2 in Fig. 3A to m: 1 (m> 1) or the like, for example. An output signal having a delay time obtained by dividing the timing difference T between two clocks by an arbitrary endocrine ratio is obtained. In the present invention, such a timing difference dividing circuit may be used as a timing averaging circuit for inputting two clocks, the two paths of the clock forward path and the return path. In this way, even when the delay time between the first position of the return path and the return point and the delay time between the return point and the second position of the return home are not equal to each other, the phase of each clock output from the timing difference dividing circuit can be adjusted. I can tidy it up.

5 is a diagram showing the configuration of a second embodiment of the present invention. In the second embodiment of the present invention, the clock path 11 has a circular arrangement, and the return point is the same as the start point of the clock path. The output of the input buffer 12 branches the clock propagation path and branches into the paths of A, B, C, and D, and the paths of E, F, G, and H, and the two points A and H that form adjacent points. Clock signals are input to the timing averaging circuit 10 ₁ , an output signal L having an average delay time between two timing differences is output, and two clock signals of point B and G are outputted to the timing averaging circuit 10. ₂ ), an output signal K having an average delay time between two timing differences is output, two clock signals of point C and F are input to the timing averaging circuit 10 ₃ , and the two timings are input. The output signal J of the average delay time of the difference is output, and two clock signals of the point D and the E point are input to the timing averaging circuit 10 ₄ , and the output signal of the average delay time of the two timing differences. (I) is output. In FIG. 5, the same advantages are also achieved by extending the two branch paths parallel (antiparallel) to each other at the return point but not crossing each other. The aspect shown in FIG. 5 has the advantage that it can be configured symmetrically with respect to the line joining the intersection point with the input point (branch point) of the clock path.

In the above-described embodiment (first embodiment) described with reference to FIG. 1, a plurality of timing averaging circuits ( _{1 1} , 11 ₂ ) basically along the return paths 11 ₁ and 11 ₂ of the clock propagation path extending in one axis direction. 10 ₁ to 10 ₄ are provided, but in the second embodiment of the present invention, the trailing paths 11 _A and 11 _D and the trailing paths 11 _B and 11 _C of the clock propagation paths spaced apart from each other and disposed to face each other. A plurality of timing averaging circuits 10 ₁ to 10 ₄ are provided along the circumference of the circuit to enlarge an area in which the timing averaging circuit can be arranged in the chip.

In the second embodiment of the present invention, as the timing averaging circuit 10, for example, the structures of Figs. 6, 7 and 8 described below are used. The configuration of any of the timing averaging circuits shown in FIGS. 6 to 8 takes the average of the timings of both rising and falling clock signals. On the other hand, the timing averaging circuit shown in Fig. 3A is configured to output a rising signal defined by a delay time in which the timing difference between rising edges of two clock signals is equally divided. The timing averaging circuit shown in Figs. 6 to 8 is also suitable to be applied to a configuration in which a clock is supplied to a circuit that operates using both edges of rising and falling clock signals.

The timing averaging circuit shown in FIG. 6 will be described.

Referring to FIG. 6, a P-channel MOS transistor MP51 having a source connected to a power supply VCC, a P-channel MOS transistor MP52 having a source connected to a drain of the P-channel MOS transistor MP51, and a P-channel MOS transistor An N-channel MOS transistor MN51 having a drain connected to the drain of MP52, and an N-channel MOS transistor MN52 having a drain connected to the source of the N-channel MOS transistor MN51 and whose source is connected to the ground potential. The input IN1 is commonly connected to the gates of the P-channel MOS transistors MP51 and MP52 and the N-channel MOS transistors MN51 and MN52.

P-channel MOS transistor MP53 whose source is connected to power supply VCC, P-channel MOS transistor MP54 whose source is connected to the drain of P-channel MOS transistor MP53, and drain of P-channel MOS transistor MP54 An N-channel MOS transistor MN53 having a drain connected thereto and a N-channel MOS transistor MN54 having a drain connected to a source of the N-channel MOS transistor MN53 and a source connected to ground, and having a P-channel MOS transistor The input IN1 is commonly connected to the gate of the MP53 and the N-channel MOS transistor MN54, and the input IN2 is common to the gate of the P-channel MOS transistor MP54 and the N-channel MOS transistor MN53. Connected.

In addition, a P-channel MOS transistor MP55 having a source connected to the power supply VCC and a P-channel MOS transistor MP56 having a source connected to the drain of the P-channel MOS transistor MP55 and a drain connected to the power supply VCC. And an N-channel MOS transistor MN56 having a source connected to ground, and an N-channel MOS transistor MN56 having a source connected to a drain of the N-channel MOS transistor MP56 and a drain connected to ground. The input IN2 is connected to the gates of the P-channel MOS transistor MP55 and the P-channel MOS transistor MP56, and the input IN2 is also connected to the gates of the N-channel MOS transistor MP55 and the N-channel MOS transistor MP56. Connected.

The connection point of the P-channel MOS transistor MP52 and the N-channel MOS transistor MN51 is connected to the input terminal of the inverter INV5, and the connection point of the P-channel MOS transistor MP54 and the N-channel MOS transistor MN53 is the inverter INV5. The output terminal of the inverter INV51 is connected to the output terminal OUT.

The P-channel MOS transistors MP55 and MP56 and the N-channel MOS transistors MN55 and MN56 having the input IN2 connected to the gate are circuits provided for equalizing the load of the input IN1 and the input IN2. .

Next, the operation of the timing averaging circuit shown in FIG. 6 will be described. When the input signal IN1 rises from the low level to the high level, the charge of the node N51 is discharged from the paths of the N-channel MOS transistors MN51 and MN52 that are turned on, and the time T is delayed so that the input signal ( When IN2 rises from the low level to the high level, the node N51 through the two-channel N-channel MOS transistors (N-channel MOS transistors MN51 and MN52 and N-channel MOS transistors MN53 and MN54). The charge is discharged, and as described above, the rising signal corresponding to the delay time obtained by averaging the timing difference T between the input signals IN1 and IN2 is output.

When the input signal IN1 goes from the high level to the low level, the charge of the node N51 is charged from the paths of the P-channel MOS transistors MP51 and MP52 that are turned on, and the input signal delayed by the time T is When IN2 falls, the electric charges of the node N51 are charged and input through the two-channel P-channel MOS transistors (P-channel MOS transistors MP51 and MP52 and P-channel MOS transistors MP53 and MP54). A falling signal corresponding to a delay time obtained by averaging the timing difference T between the signals IN1 and IN2 is output.

In the timing averaging circuit shown in Fig. 6, since the input order of the clocks IN1 and IN2 is determined in advance, from the arrangement of the clock paths, a signal arrives first and a point that needs to be input first (IN1 in Fig. 6). ) Must be connected.

That is, when the timing averaging circuit shown in FIG. 6 is used for the timing averaging circuit 10 ₁ of FIG. 5, first, the point A at which the signal arrives is set as the input terminal IN1, and the point H at which the signal arrives later is input. Connect to (IN2).

This is because in the circuit configuration shown in Fig. 6, the number of transistors turned on and off by the input IN1 and the input IN2 in the charge / discharge path is not symmetrical. For example, in two current paths (transistors MP51 and MP52, MP53 and MP54) between the power supply VCC and the internal node N52, the number of transistors turned on when the input IN1 falls is three ( MP51, MP52, and MP53 (where MP51 and MP3 function as a constant current source), whereas one transistor (MP54) turned on by the falling of the input (IN2) is connected to the input (IN1) and the input (IN2). This is because it has an asymmetrical configuration. The circuit configuration shown in FIG. 6 does not include a logic circuit for on-off control of the constant current source transistor like the timing averaging circuit shown in FIGS. 7 and 8 described later, and thus the number of elements of the transistor is reduced. can do.

7 is a diagram showing the configuration of another embodiment of the timing averaging circuit according to the present invention. In the timing averaging circuit shown in FIG. 7, even if the input order of the clock is not predetermined, it can be used, and internal transistors of NAND and NOR are used as parallel MOS transistors.

Referring to FIG. 7, a NAND circuit NAND61 that takes inputs IN1 and IN2, an inverter circuit INV61 and INV62 that inputs IN1 and IN2, respectively, and a source are connected to a power supply VCC. The drain is connected to the drain of the P-channel MOS transistor MP61 and the P-channel MOS transistor MP61 whose gate is connected to the output terminal of the NAND circuit NAND61, and the gate is connected to the output terminal of the inverter INV61. The drain is connected to the N-channel MOS transistor MN61 and the source of the N-channel MOS transistor MN61, and the drain of the N-channel MOS transistor MN62 and the P-channel MOS transistor MP61 are connected to the ground. A drain is connected to the source of the N-channel MOS transistor MN63 and the N-channel MOS transistor MN63, whose drain is connected and whose gate is connected to the output terminal of the inverter INV62, the source is connected to ground, and the gate is N. To the gate of the channel MOS transistor (MN62) It inherited N-channel and a MOS transistor (MN64).

In addition, the source is connected to the drains of the P-channel MOS transistors MP62 and MP63 and the drains of the P-channel MOS transistors MP62 and MP63 in which the source is connected to the power supply VCC and the gates are connected, and the inputs IN1 and IN2 are connected. Drains are connected to the P-channel MOS transistors MP64 and MP65 having gates connected to the output terminals of the inverters INV64 and INV63 serving as inputs, and to the drains of the P-channel MOS transistors MP64 and MP65, and the inputs IN1 and IN2. N-channel MOS transistor (MN65) having a gate connected to the output terminal of the NOR circuit (NOR61) for inputting, and the gates of the P-channel MOS transistors (MP62, MP63) are N-channel MOS transistors (MN62, MN64). Is commonly connected to the gate.

The drain of the P-channel MOS transistor MP61 is connected to the power source and the gate of the P-channel MOS transistor MP66, and the drain of the P-channel MOS transistor MP66 is the drain of the N-channel MOS transistor MN66. The gate of the N-channel MOS transistor MN66 is connected to the drain of the N-channel MOS transistor MN65, and the source is connected to ground.

The connection point of the P-channel MOS transistor MP66 and the N-channel MOS transistor MN66 is connected to the output terminal OUT through the inverter INV65, and the output of the inverter INV65 connects the inverter INV66 and INV67. Through this, the common gates of the N-channel MOS transistors MN62 and MN64 and the common gates of the P-channel MOS transistors MP62 and MP63 are connected.

The operation of the timing averaging circuit shown in FIG. 7 will be described.

In Fig. 7, the output terminal of the NAND circuit NAND61 transitions from the low level to the high level when the input signals IN1 and IN2 fall from the high level to the low level, and the P-channel MOS transistor MP61 is turned off. One side of the N-channel MOS transistors MN61, 63 whose gate inputs are the outputs of the inverters INV61, INV62 continue to be turned on, and at this time, the output OUT is still at a high level (before falling). Therefore, the output potential OUT is transmitted to the node N74 through the inverters INV67 and 66, the node N74 is at a high level, and the N-channel MOS transistors MN62 and MN64 having the node N74 as a gate input. ), The node N71 is discharged, the potential of the node N71 is lowered, the P-channel MOS transistor MP66 is turned on, the node N73 is turned high, and the inverter INV65 is turned on. Through, the falling signal from the high level to the low level is output. The output signal OUT has a delay time corresponding to the delay time 1/2 of the timing difference between the input signals IN1 and IN2 as described above. The output potential OUT of the inverter INV65 is transmitted to the node N74 through the inverters INV67 and 66. When the output potential OUT is at the low level, the N-channel MOS transistors MN62 and MN64 are turned off. The P-channel MOS transistors MP62 and MP63 are turned on.

A logic circuit of the NAND circuit NAND61 and the inverters INV61 and INV62, and a delay obtained by averaging the timing difference between the input signals IN1 and IN2 regardless of which one precedes the phase of the input signals IN1 and IN2. Of the time (the average delay time between the output when the signal with the phase out of the inputs IN1 and IN2 is input and the output when the signal with the phase out of the inputs IN1 and IN2 is input). The signal is output.

In Fig. 7, when the input signals IN1 and IN2 rise from the low level to the high level, the output terminal of the NOR circuit NOR61 transitions from the high level to the low level, the N-channel MOS transistor MN65 is turned off, Since both of the P-channel MOS transistors MP64 and MP65 that use the outputs of the inverters INV63 and INV64 as gate inputs are both turned on at this time, the output OUT is still at the low level (before rising). The output potential OUT is transmitted to the node N74 through the inverters INV67 and 66, the node N74 is at a low level, and the N-channel MOS transistors MP62 and MP63 having the node N74 as a gate input. Is turned on, so that the node N72 is charged, the potential of the node N72 rises, the N-channel MOS transistor MN66 is turned on, the node N73 is brought to the low level, and the inverter INV65 is The rising signal from the low level to the high level is output. The output signal OUT has a delay time corresponding to the delay time 1/2 of the timing difference between the input signals IN1 and IN2 as described above. The output potential OUT of the inverter INV65 is transmitted to the node N74 through the inverters INV67 and 66. When the output potential OUT becomes high, the N-channel MOS transistors MN62 and MN64 are turned on. The P-channel MOS transistors MP62 and MP63 are turned off.

The NOR circuit NOR61 and the logic circuits of the inverters INV63 and INV64 are provided, and the delays obtained by averaging the timing difference between the input signals IN1 and IN2 are equal to the phases of the input signals IN1 and IN2. Of the time (the average delay time between the output when the signal of the phase ahead of the input (IN1, IN2) is input and the output when the signal of the phase out of the input (IN1, IN2) is inputted) The signal is output. The timing averaging circuit shown in FIG. 7 is used to turn on the N-channel MOS transistors MN62 and MN64 and the P-channel MOS transistors MP62 and MP63 which function as constant current sources for discharging and charging the internal nodes N71 and NN72, respectively. Although the control signal (gate voltage) for controlling the off is obtained from the logic value of the output signal OUT, the internal node is not limited to this feedback configuration but based on the first and second input signals IN1 and IN2. In discharging (N71), the N-channel MOS transistors MN62 and MN64 functioning as constant current sources are turned on, and the P-channel MOS transistors functioning as constant current sources in charging the internal node N72 ( Various configurations are possible as long as MP62 and MP63 are set to ON.

FIG. 8 is a diagram illustrating an example of a modification of the timing averaging circuit shown in FIG. 7. Referring to FIG. 8, a NAND circuit NAND71 that takes inputs IN1 and IN2, an inverter circuit INV71 and INV72 that inputs IN1 and IN2, respectively, and a source are connected to a power supply VCC. N-channel having a gate connected to a drain of the P-channel MOS transistor MP71 and a drain of the P-channel MOS transistor MP71 connected to the NAND circuit NAND71, and a gate connected to an output terminal of the inverter INV71. A drain is connected to the source of the MOS transistor MN71 and the N-channel MOS transistor MN71, and a drain is connected to the drain of the N-channel MOS transistor MN72 and the P-channel MOS transistor MP71 whose source is connected to the ground potential. Is connected, the drain is connected to the source of the N-channel MOS transistor MN73 and the N-channel MOS transistor MN73 whose gate is connected to the output terminal of the inverter INV72, the source is connected to the ground potential, Connected to the gate of the N-channel MOS transistor MN72. The N-channel MOS transistor MN74 is provided.

In addition, the source is connected to the power supply, the source is connected to the drains of the P-channel MOS transistors MP72 and MP73 and the P-channel MOS transistors MP72 and MP73 having gates connected thereto, and the inputs IN1 and IN2 are input. The drains are connected to the drains of the P-channel MOS transistors MP74 and MP75 and the drains of the P-channel MOS transistors MP74 and MP75, respectively, whose gates are connected to the output terminals of the inverters INV74 and INV73, respectively. An N-channel MOS transistor (MN75) having a gate connected to an output terminal of the NOR circuit (NOR71) for inputting the gate, and the gates of the P-channel MOS transistors (MP72, MP74) are N-channel MOS transistors (MN72, MN73). It is connected in common with the gate of.

The drain of the P-channel MOS transistor MP71 is connected to the gate of the P-channel MOS transistor MP76 whose source is connected to the power supply, and the drain of the P-channel MOS transistor MP76 is the drain of the N-channel MOS transistor MN76. The gate of the N-channel MOS transistor MN66 is connected to the drain of the N-channel MOS transistor MN65, and the source is connected to ground.                     

The connection point of the P-channel MOS transistor MP76 and the N-channel MOS transistor MN76 is connected to the output terminal OUT through the inverter INV75.

The operation of the timing averaging circuit shown in FIG. 8 will be described.

In Fig. 8, the output terminal of the NAND circuit NAND71 transitions from the low level to the high level when the input signals IN1 and IN2 fall from the high level to the low level, and the P-channel MOS transistor MP71 is turned off. One of the N-channel MOS transistors MN71 and 73 whose outputs of the inverters INV71 and INV72 serve as gate inputs is subsequently turned on to discharge the node N81, and the potential of the node N81 is lowered to P. The channel MOS transistor MP76 is turned on, the node N83 becomes high level, and the rising signal from the low level to the high level is output through the inverter INV75. The output signal OUT has a delay time corresponding to the delay time 1/2 of the timing difference between the input signals IN1 and IN2 as described above.

8, when the low level of the input signals IN1 and IN2 rises from the high level, the output terminal of the NOR circuit NOR71 transitions from the high level to the low level, the N-channel MOS transistor MN65 is turned off, One of the P-channel MOS transistors MN74 and 75 having the output of the inverters INV73 and INV74 as gate inputs is turned on continuously, both of them charge the node N82, and the potential of the node N82 rises to increase the N-channel MOS. The transistor MN76 is turned on, the node N83 is set at the low level, and the falling signal from the high level to the low level is output through the inverter INV75. The output signal OUT has a delay time corresponding to the delay time 1/2 of the timing difference between the input signals IN1 and IN2 as described above.

9 to 13, a third embodiment of the present invention will be described. This embodiment enables the present invention to be applied to the case where the delay amount on the clock propagation path is longer than the clock period tCK as shown in FIG. In recent years, due to high functionalization of semiconductor integrated circuit devices, the length of the entire clock path is also long, and the speed of the operating frequency is remarkable. For this reason, for example, in the configuration of the above embodiment shown in Fig. 1, when the delay amount on the clock propagation path is longer than the clock period tCK, as an example, it is most separated from the return point 11 ₃ of the clock propagation path. When the delay time 2a of the A point of the path _{1 1} and the H point of the return path _{1 1 2} of the clock propagation path at one position becomes longer than the clock period tCK, the clocks from the A and H points In the timing averaging circuit 10 ₁ , which inputs the signal at the first and second input terminals, the clock of the next clock cycle is input to the point A before the clock inputted to the first clock path reaches the H point and is input to the second input terminal. As a result, the desired average value cannot be output. The third embodiment of the present invention makes it possible to realize a desired operation when the delay amount on the clock propagation path is longer than the clock period tCK.

Referring to FIG. 9, the clock divided by the division circuit 14 from the input buffer 2 is supplied to the clock propagation path (path 1111, return point _{1 1 3} , and return 11 ₁ ).

The clock signal of the clock period tCK from the input buffer 12 is divided in the frequency divider circuit 14, and the clock input to the clock propagation path 11 returns the clock propagation path, and two points A and H are provided. Clock signals are input to the timing averaging circuit 10 ₁ , the output signal L of the average delay time of the two timing differences is input to the multiplication circuit 15 ₁ , multiplied, and the signal P is outputted, Two clock signals of point B and point G are input to the timing averaging circuit 10 ₂ , and the output signal K of the average delay time of the two timing differences is input to the multiplication circuit 15 ₂ and multiplied. 0 is output, two clock signals of point C and F are input to the timing averaging circuit 10 ₃ , and the output signal J of the average delay time of the two timing differences is supplied to the multiplication circuit 15 ₃ . the input signal and the multiplier (N) are output, the two clock signals of the D point and E point are input to the timing averaging circuit (10, ₄₎ , The output signal (I) of the two timing differences of the average delay time of the multiplier and the input to the multiplier circuit (15, ₄₎ the signal (M) is output.

10 is a timing chart of the circuit shown in FIG. The clock is divided by the division circuit 14, the divided clock is supplied to the clock propagation path 11, and then returned to be a bidirectional clock transmission line, and the timing averaging circuit 10 is used to timing clock pulses. Is taken, and the output of the timing averaging circuit 10 is multiplied by the multiplication circuit 15 and output.

In the present invention, the multiplication circuit is performed by a combination of timing averaging circuits (timing difference dividing circuits). This multiplication circuit 15 can use the structure etc. which this inventor proposed to Unexamined-Japanese-Patent No. 09-157042 (Japanese Patent Application Laid-Open No. 11-004148), Japanese Patent Application No. 09-157028 (Japanese Patent Application Laid-Open No. 11-004145), etc. have.

In this embodiment, when the delay amount on the clock propagation path 11 is longer than the clock period tCK, the delay amount of the clock propagation path can be trimmed only by the timing averaging circuit without using the feedback circuit.

With reference to FIGS. 11-15, one example of the structure of the multiplication circuit 15 which is one Embodiment of this invention is demonstrated. This multiplication circuit divides the clock once as shown in FIG. 11, performs timing averaging between two consecutive phases of the divided multi-phase clock, and outputs a new clock. The clock multiplication is performed by doubling the number of phases by combining the clock output with the clock of the output which has not been timing averaged, and then synthesizing it.

More specifically, referring to FIG. 11, the multiplication circuit 15 inputs and divides the clock 1 (the output of the timing difference averaging circuit in one embodiment of the present invention) to generate a multiphase clock 3. It consists of a multi-phase clock multiplier circuit 5 which inputs the period 2, the output 3 of the divider 2, a fixed stage ring oscillator and a counter, and the ring oscillator in one period of the clock 1 A cycle detection circuit 6 for counting the number of oscillations of the clock to detect the period of the clock 1 and a clock synthesis circuit 8 for synthesizing the output of the multiphase clock multiplication circuit 5 to generate a multiplication clock 9; Equipped. The multiphase clock multiplication circuit 5 includes a plurality of timing difference dividing circuits 4a for outputting a signal obtained by dividing (dividing) the timing difference (phase difference) of two inputs, and a plurality of multiplexing outputs of two timing difference dividing circuits. The multiplexing circuit 4b is provided.

The plurality of timing difference dividing circuits 4a includes a timing difference dividing circuit for inputting a clock of the same phase and a timing difference dividing circuit for inputting two neighboring clocks. The cycle detection circuit 6 outputs the control signal 7, adjusts the load capacity of the timing difference dividing circuit 4a in the multiphase clock multiplication circuit 5, and controls the clock cycle.

12 is a diagram illustrating a specific example of the configuration of a multiplication circuit that generates a four-phase clock as one example of the multiplication circuit 15. And 4 to the input clock 205 frequency divider as shown four-phase clock 1/4 frequency divider 201 for outputting (Q1 to Q4) in Fig. 12, n-stage cascade-connected four-phase clock multiplication circuits (202 ₁ To 202 _n ), a clock synthesizing circuit 203, and a period detecting circuit 204. In the four-phase clock multiplication circuit 202 _n of the last stage, the four-phase clocks Qn1 to Qn4 multiplied by 2n are output, synthesized by the clock synthesis circuit 203, and the multiplication clock 207 is output. The number n of stages of the four-phase clock multiplication circuit is arbitrary.

The quarter divider 201 divides the input clock 205 into quarters, generates four-phase clocks Q1, Q2, Q3, and Q4, and divides these clocks Q1, Q2, Q3, and Q4 into four. in-phase clock multiplication circuit (201 _1), a four-phase clock (Q11, Q12, Q13, Q14) for generating and, similarly, four-phase clock multiplication circuit (202 _n) multiplication in, 2n multiple of a four-phase clock (Qn1, Qn2, Qn3, Qn4) are obtained.

The cycle detection circuit 204 includes a fixed stage ring oscillator and a counter, and counts the number of oscillations of the ring oscillator as a counter during the cycle of the clock 1, and outputs a control signal 206 according to the count number. The load in the four-phase clock multiplication circuit 202 is adjusted. This period detection circuit 206 eliminates the clock cycle operation range and device characteristic variations.

The four-phase clock is set to eight-phase by the four-phase clock multiplication circuit 202 of FIG. 12, and the multiplication is continuously performed by returning to the four-phase.

FIG. 13 is a diagram illustrating an example of the configuration of the four-phase clock multiplication circuit 202 _n shown in FIG. 12. In addition, all four-phase clock multiplication circuits 202 ₁ to 202 _n shown in FIG. 12 have the same configuration.

Referring to FIG. 13A, the four-phase clock multiplication circuit 202 _n includes eight sets of timing difference dividing circuits 208 to 215, eight pulse correction circuits 216 to 223, and four sets of multiplexing circuits 224. To 227). Fig. 13B is a diagram showing the configuration of the pulse width correction circuit, which is composed of a signal returned from the inverter INV of the second input T23 and a NAND circuit of which the first input T21 is input.

Fig. 13C is a diagram showing the configuration of the multiplexing circuit, which is composed of two input NAND circuits.

FIG. 14 is a signal waveform diagram showing a timing operation of the four-phase clock multiplication circuit 202 shown in FIG. The rise of the clock T21 is determined by the delay of the internal delay of the timing difference dividing circuit 208 from the rise of the clock Q (n-1) 1, and the rise of the clock T22 is the clock Q (n−). 1) It is determined by the timing division in the timing difference dividing circuit 209 and the delay of the internal delay in the timing of the rise of 1 and the rise of clock Q (n-1) 2, and the rise of clock T23 is The timing division in the timing difference dividing circuit 209 between the rise of the clock Q (n-1) 1 and the rise of the clock Q (n-1) 2 is determined by the delay between the timing division and the internal delay. Similarly, the rise of the clock T26 is equal to the timing division in the timing difference dividing circuit 213 of the rise of the clock Q (n-1) 3 and the rise of the clock Q (n-1) 4. Determined by the delay of the internal delay, the rise of the clock T27 is determined by the delay of the internal delay in the timing difference dividing circuit 214 at the timing of the rise of the clock Q (n-1) 4, and the clock Rising of T28 is rising of clock Q (n-1) 4. It is determined by the timing division and internal delay of the delay minutes of the clock (Q (n-1) 1) Timing The timing difference division circuit 215 of the rise of the.

The clocks T21 and T23 are input to the pulse width correction circuit 216, and the pulse width correction circuit 216 has a falling edge determined by the clock T21 and a pulse P21 having a rising edge determined by the clock T23. ) The pulses P22 to P28 are generated in the same order, and the clocks P21 to P28 become pulse groups of eight phases having a duty of 25% shifted in phase by 45 degrees. The clock P25, which is 180 degrees out of phase with the clock P21, is multiplexed and returned from the multiplexing circuit 224, and output as a clock Qn1 having a duty of 25%. Similarly, clocks Qn2 to Qn4 are generated. The clocks Qn1 to Qn4 become a pulse group of four phases having a duty of 50% shifted in phase by 90 degrees, and the periods of the clocks Qn1 to Qn4 are clocks Q (n-1) 1 to Q (n-1) 4. In the process of generating the clocks Qn1 to Qn4 from, the frequency is doubled.

15A and 15B are diagrams each showing an example of the configuration of the timing difference dividing circuits 208 and 209 shown in FIG. These circuits have the same configuration, and it differs whether two inputs are the same signal or two adjacent signals are input. That is, the same input Q (n-1) 1 is input to the two-input NOR circuit NOR14 in the timing difference dividing circuit 208, and Q (n-1) 1 and Q in the timing difference dividing circuit 209. The timing difference dividing circuit has the same configuration except that (n-1) 2 is input to the two input 2NOR circuit NOR14. The two-input NOR14 is connected in series between the power supply VDD and the output terminal, and is connected in parallel between the two P-channel MOS transistors for inputting the input signals IN1 and IN2 to the gate, and in parallel between the output terminal and the ground. It consists of two N-channel MOS transistors which input (IN1, IN2) to the gate, respectively.

The internal node N51 (N61), which is an output node of the two-input NOR14, is connected to an input terminal of the inverter INV15, and a circuit in which an N-channel MOS transistor MN51 and a capacitor CAP51 are connected in series between the internal node and ground, A circuit in which the N-channel MOS transistor MN52 and the capacitor CAP52 are connected in series and a circuit in which the N-channel MOS transistor MN53 and the capacitor CAP53 are connected in series are connected in parallel, and each N-channel MOS transistor MN51, The control signals 7 from the periodic detection circuit 6 are connected to the gates of the MN52 and MN53, respectively, and are controlled on-off. The gate width and capacitances CAP51, TCAP52, and TCAP53 of the N-channel MOS transistors MN51, MN52, and MN53 have a size ratio, for example, 1: 2: 4, and are output from the period detection circuit 6. Based on the signal 7, the clock period is set by adjusting the load connected to the common node in eight steps.

Regarding the timing difference dividing circuit 208, the rising edge of the clock Q (n-1) 1 causes the charge of the node N51 to be drawn out through the N-channel MOS transistor of NOR14, and the potential of the node N51. Reaches the threshold of inverter INV15, clock T21, which is the output of inverter INV15, rises. The charge of the node N51 that needs to be drawn out to reach the threshold of the inverter INV15 is set to CV (where C is the capacitance and V is the voltage), and the discharge current of the N-channel MOS transistor of NOR14 is set to I. In this case, the charge amount of CV is discharged as the current value 2I from the rise of the clock Q (n-1) 1. As a result, the time CV / 2I becomes the clock Q (n-1) 1. The timing difference (overall delay time) from the rising edge of to the rising of the clock T21 is shown. When the clock Q (n-1) 1 is at the low level, the output node N51 of the two-input NOR14 is charged high, and the output clock T21 of the inverter INV15 is at the low level.

Regarding the timing difference dividing circuit 209, the charge of the node N61 is drawn to NOR14 during the period after the time tCKn (tCKn = polyphase clock period) from the rising edge of the clock Q (n-1) 1, and the time ( After tCKn, from the rising edge of the clock Q (n-1) 2, the edge of the clock T22 rises where the potential of the node N61 reaches the threshold of the inverter INV15. If the charge of the node N61 is CV and the discharge current of the NMOS transistor of the two-input NOR14 is I, the charge amount of CV is discharged to the current of the period I of tcKn from the rise of the clock Q (n-1) 1. , As a result of drawing the rest of the period into the current (2I),

tCKn + (CV best tCKn · I) / 2I

 = CV / 2I + tCKn / 2

Indicates the timing difference between the rising edge of clock Q (n-1) 1 and the rising edge of clock T22.

That is, the timing difference between the rise of the clock T22 and the clock T21 is tCKn / 2.

When the clocks Q (n-1) 1 and Q (n-1) 2 are both at low level, and the output node N61 of the two-input NOR14 is charged to the high level from the power supply through the P MOS transistor of NOR14. , Clock T22 rises. The same applies to the clocks T22 to T28, and the timing difference of the rise of the clocks T21 to T28 is tcKn / 2, respectively.

The pulse width correction circuits 216 to 223 generate pulse groups P21 to P28 of eight phases having a duty of 25% having a phase shift of 45 degrees.

The multiplexing circuits 224 to 227 generate pulse groups Qn1 to Qn4 of four phases having a duty of 50% shifted in phase by 90 degrees.

Next, a fourth embodiment of the present invention will be described with reference to Figs. Also in this embodiment, the present invention is applied to the case where the delay amount on the clock path is longer than the clock period tCK.

Referring to FIG. 16, in the fourth embodiment of the present invention, the clock is first supplied to the return bidirectional clock propagation path, and each point (pair) near the path 11 ₁ and the return path _{1 1 2} of the clock propagation path. In the timing averaging circuits 100 ₁ to 100 ₄ having the function of dividing a clock at, the frequency averaging is performed once, and the timing of the clock pulses is averaged using the timing averaging circuit for the divided clocks. Synthesized at (16 ₁ to 16 ₄ ). The clock input to the clock propagation path 11 returns the clock propagation path, and two clock signals, A and H, are input to the timing averaging circuit 100 ₁ having the division function, and the two clocks of the divided clocks are input. The output signals L1 to L4 of the average delay time of the timing difference are output, L1 to L4 are synthesized by the synthesis circuit 16 ₁ , and the signal P is output, and two clock signals of point B and G are output. Is input to a timing averaging circuit 100 ₂ having a frequency division function, and output signals K1 to K4 having an average delay time of two timing differences of the divided clocks are output, and K1 to K4 are synthesized circuits 16 _2. ) Is synthesized, and the signal O is outputted, and two clock signals of point C and F are inputted to the timing averaging circuit 100 ₃ having a division function, and the delay of the average of the two timing differences of the divided clocks. Output signals J1 to J4 of time are output, and J1 to J4 are synthesized in the synthesis circuit 16 ₃ . Signal N is outputted, and two clock signals, D and E, are input to a timing averaging circuit 100 ₄ having a frequency division function, and an output of an average delay time between two timing differences of the divided clocks. The signals I1 to I4 are output, the I1 to I4 are synthesized in the synthesis circuit 16 ₄ , and the signal M is output.

FIG. 17 is a diagram showing the configuration of a timing averaging circuit 100 ₁ having a frequency division function shown in FIG. The timing averaging circuits 100 ₂ to 100 ₄ having other division functions have the same configuration. The signals A1, A2, A3, and A4 obtained by dividing the clock at the point A on the clock propagation path 11 by the division circuit 101 ₁ are supplied to the timing averaging circuits 102 ₁ to 102 ₄ , and the clock propagation path ( 11, the signals B1, B2, B3, and B4 obtained by dividing the clock at the point H on the division circuit 101 ₂ are supplied to the timing averaging circuits 102 ₁ to 102 ₄ , and the timing averaging circuit 102 ₁ The signal L1 of the intermediate value of the timing difference between A1 and B1 is output, and the timing averaging circuit 102 ₂ outputs the signal L2 of the intermediate value of the timing difference between A2 and B2. Thus, the timing averaging circuit ( 102 ₄ ) outputs the signal L4 of the intermediate value of the timing difference between A4 and B4, and the synthesis circuit 16 synthesizes the signals L1 to L4 and outputs the signal P.

As described above, in the present embodiment, the clocks of the respective points of the trailing path _{1 1 1} and the return path _{1 1 2} of the clock propagation path are respectively divided by the division circuits 101 ₁ and 101 ₂ to generate a four-phase clock. The four signals obtained by averaging the timing difference in the timing averaging circuit are combined into one signal P in the synthesizing circuit 16, and the output of the synthesizing circuit 16 is connected to the multiplication output. Since it is equivalent, the delay amount of the clock path can be trimmed only by the timing averaging circuit having the frequency division function even when the delay amount on the division clock path is longer than the clock period. In the present embodiment having no configuration, the circuit scale can be reduced compared with the third embodiment.

18 is a timing chart showing the operation of the fourth embodiment of the present invention.

The division circuits 101 ₁ and 101 ₂ for inputting signals of the points A and H output the signals A1 to A4 and B1 to B4 divided into four, and the timing averaging circuit 102 ₁ provides the signals A1 and B1. A signal obtained by averaging the timing difference of the? Is output, and the timing of the combined output signals M to P is trimmed.

Next, referring to Figs. 19 and 20, a fifth embodiment of the present invention will be described. Also in this embodiment, the present invention is applied to the case where the delay amount on the clock propagation path is longer than the clock period tCK.

As shown in Fig. 19, in the fifth embodiment of the present invention, the input clock 13 is divided once by the division circuit 14, and a plurality of polyphase clocks (four phase clocks) output from the division circuit 14 are plural. To the clock wirings 11-1 to 11-4. Each clock wire by the number of clock phases is used as a return bidirectional clock transfer line, and the timing average of the clock pulses is obtained by using the timing averaging circuit TM with respect to the clocks of the wirings of each phase, and then synthesized thereafter. Synthesis in circuit 16 is performed.

The clock signal divided into four by the division circuit 14 is inputted to the clock propagation paths 11-1 to 11-4 and returned, and the path A1-1 of the path of the same clock propagation paths 11-1 to 11-4 is returned. Four timing averaging circuits TM for inputting A4) and the return points H1-H4 in pairs and outputting the output signals L1-L4, and L1-L4 are combined to output the signal P. A synthesizing circuit (16 ₁ ) for outputting a pair of input paths (B1-B4) and return points (G1-G4) of the same clock propagation paths (11-1 to 11-4), respectively, as input and outputting Four timing averaging circuits TM for outputting signals K1-K4, synthesis circuits 16 ₂ for synthesizing K1-K4 and outputting the output signal O, the same clock propagation paths 11-1 to 11 Four timing averaging circuits TM for inputting the return paths C1-C4 and the return points F1-F4 of -4) and outputting the output signals J1-J4, respectively, and J1. -Synthesis for outputting output signal (N) by synthesizing J4 The circuit 16 ₃ is a pair of input points D1-D4 and return points E1-E4 of the same clock propagation paths 11-1 to 11-4, respectively, as inputs and output signals I1-. and I4) 4 of the timing averaging circuit (TM) for outputting, and a combining circuit (16, ₄₎ to synthesize the I1-I4 and outputting the output signal (M). In the embodiment of the present invention, the phases of the outputs M to P are arranged.

In the present embodiment, as in the fourth embodiment, when the delay amount on the clock propagation path is longer than the clock period, it is possible to trim the delay amount of the clock path only by the timing averaging circuit without using a multiplication circuit. Done. In the fourth embodiment, one timing averaging circuit having a frequency division function is provided with two frequency divider circuits. In this embodiment, the input clock 13 is divided into four clock propagation paths 11-. Only the frequency divider 14 to be supplied to 1 to 11-4 is provided, so that the delay amount of the clock path can be trimmed in fewer frequency divider circuits than in the fifth embodiment. That is, the number of wirings for the clock propagation path is increased, but the circuit scale can be reduced as compared with the fourth embodiment.

Next, a sixth embodiment of the present invention will be described. 21 is a diagram showing the configuration of a sixth embodiment of the present invention. In the sixth embodiment of the present invention, the clock front line is supplied in a mesh shape by using two layers of circuits that average the timing of clock pulses using the timing averaging circuit TM. As shown in FIG. 21, timing averaging circuits 110 ₁ to 110 ₄ that take an average of timing with respect to a predetermined point of the return path and the return path of the clock propagation path 111 propagating the clock from the input buffer 112 are shown. Of the buffers 113 ₁ to 113 ₄ for inputting the outputs of the timing averaging circuits 110 ₁ to 110 _{4 in the} vertical direction, firstly provided on one side of the chip, and then vertically arranged in a straight line. An output is input, and the circuit which averages the timing of a clock pulse is arrange | positioned in parallel, and an output is connected in mesh shape.

In the sixth embodiment of the present invention, a clock signal in which the delay amount of the clock is arranged in a two-dimensional manner in the clock path over the entire chip in the semiconductor integrated circuit can be supplied. In other words, even if a clock use circuit such as a synchronous circuit is arranged on the layout surface of the chip, a remarkable working effect is achieved that the timing of the clock supplied to the clock use circuit can be arranged throughout the chip.

Since the timing averaging circuit of the sixth embodiment of the present invention uses the same circuit configuration as that of the fourth embodiment, it can be easily applied even when the delay amount of the clock path is longer than the clock period.

As described above, according to the present invention, in the internal circuit of the semiconductor integrated circuit device, the phase of the clock supplied by the clock supply circuit can be adjusted in a short time with respect to the clock using circuit supplied with the clock, and the clock synchronization of the large scale integrated circuit can be achieved. It is suitable for use in control. Note that the present invention is not limited to the semiconductor integrated circuit device but can be applied to the clock control of the substrate and various devices.

In addition, in this invention, embodiment described based on drawing contains the part, can select each other as needed, and it is naturally within the scope of this invention even if it uses combining two or more parts-embodiment with each other. It is.

As described above, according to the present invention, there is an effect that the delay difference can be eliminated in a short time in a circuit that detects the wiring delay in the return bidirectional clock transmission line and eliminates the delay difference in the entire clock transmission line.                     

The reason for this is that in the present invention, the timing averaging circuit is used to arrange the timing, and the PLL and the DLL are not used to solve the problem of requiring a long clock cycle until the delay difference is eliminated.

According to the present invention, there is an effect that the increase in the circuit scale can be forcibly reduced.

The reason for this is that, in the present invention, the phase comparator, the delay circuit sequence, and the like are different from those of the conventional apparatus having a plurality of phase comparators, delay circuit sequences, and the like.

Claims (17)

A first clock from a first location on the path of the clock propagation path for inputting and returning an input clock from one end, a second clock from a second location of the return path corresponding to the first location on the path; Each of two clocks is divided into two to generate a plurality of phased divided clocks of different phases, and among the clock signals divided into two clocks, the timing difference between the divided clocks of the corresponding phases is equally divided by two. A timing averaging circuit having a frequency division function for outputting a signal having a delay time And a synthesizing circuit for synthesizing and outputting a plurality of outputs of the timing averaging circuit having the division function into one signal. A frequency divider function that inputs two clocks from a first position on a path of a clock propagation path for inputting and returning an input clock from one end and from a second position of a return path corresponding to the first position of the path. With timing averaging circuit, A synthesizing circuit for synthesizing the divided outputs from the timing averaging circuit having the frequency dividing function into one output signal, First and second frequency divider circuits in which the timing averaging circuit having the frequency division function divides two clocks and outputs a plurality of phase divided clocks having different phases; A plurality of timing averaging circuits for inputting two divided clocks of corresponding phases to which the first and second divider circuits output a signal having a delay time corresponding to a time obtained by dividing the timing difference equally by two; And a synthesizing circuit for synthesizing and outputting a plurality of outputs from the plurality of timing averaging circuits into one signal. A division circuit for dividing an input clock to output a plurality of phase division clocks having different phases; A plurality of clock propagation paths for inputting and returning a plurality of divided clocks output from the division circuit, respectively, The time which inputs two clocks from the 1st position on the path | route of the said clock propagation path | route, and the 2nd position of the return path corresponding to the said 1st position of the said path | route as input, and divides the timing difference of these two clocks evenly into 2 parts. A plurality of timing averaging circuits for outputting a signal having a delay time corresponding to the plurality of clock averaging paths, And a synthesizing circuit for synthesizing and outputting a plurality of outputs of the plurality of timing averaging circuits into one signal. The two clocks from a position on the path of the first clock propagation path for inputting and returning the input clock from one end and the position of the return path corresponding to the position of the path as input are inputted. A first timing averaging circuit for outputting a signal having a delay time corresponding to a time in which the timing difference is equally divided into two; A second clock propagation path for inputting and returning a clock outputted from the first timing averaging circuit from one end; Corresponding to the time at which the two clocks from the return path of the second clock propagation path and the return path corresponding to the position of the return path are input, and the timing difference between these two clocks is equally divided into two. And a second timing averaging circuit for outputting a signal having a delay time. The method of claim 4, wherein A first timing averaging circuit for inputting a clock pair of each of the two points of the first and second paths in the first clock propagation path and outputting a signal having a delay time corresponding to a time divided equally by dividing the timing difference between the clock pairs; It is equipped with plural, A second timing averaging circuit for inputting the clock pairs of each of the two paths of the second clock propagation path and the return path and outputting a signal having a delay time corresponding to a time divided equally by dividing the timing difference between the clock pairs; And a plurality of output terminals or lines of the output signals of the first and second timing averaging circuits are provided in a mesh shape. The method of claim 1, The delay time between the first position and the return point of the clock propagation path and the delay time between the return point of the clock propagation path and the second position are equal to each other. A clock control circuit comprising a plurality along the return point of the propagation path. The method according to any one of claims 2 to 5, Regarding the delay time from when the timing averaging circuit inputs the clocks of the two clocks which are rapidly transitioned to the first and second input terminals to which the two clocks are input simultaneously, until the output signal is output. And a delay time obtained by adding a delay time corresponding to a time (T / 2) obtained by equally dividing the timing difference (T) of the two clocks into an output signal. The method according to any one of claims 2 to 5, The timing averaging circuit charges or discharges an internal node based on one of the two clocks that transitions faster, and continuously based on the other clock and the one clock that transitions later than the one clock. And an internal node connected to an input terminal, and having a buffer circuit for changing an output logic value when the internal node voltage exceeds or falls below a threshold voltage. Clock control circuit. The method according to any one of claims 2 to 5, First and second timing averaging circuits connected in parallel between a first power supply and an internal node, on when the first input and the second input are respectively the first value, and off when the second value is the second value; With a switch element, A third switch element connected between the internal node and a second power supply, the third switch element being turned on when the first input and the second input are input and the second value is input; A capacity connected between the internal node and a second power source, And a buffer circuit whose output logic value is determined by the magnitude of the potential of the internal node and a threshold value. The method according to any one of claims 2 to 5, A plurality of first switch elements connected in series between a first power supply and an internal node, a first input connected to a control terminal, and turned off when the first input is a first value; A plurality of second switch elements connected in series between the internal node and a second power supply, a first input connected to a control terminal, and turned on when the first input is a first value; A third switch element connected in series between the first power supply and the internal node, the first input connected to a control terminal, the third switch element being turned off when the first input is a first value, and a second input connected to the control terminal; A fourth switch element connected to and turned off when the second input is a first value, A fifth switch element connected in series between said internal node and said second power supply, said first input being connected to a control terminal and being turned on when said first input is a first value, and said second input being a control terminal; A sixth switch element connected to and turned on when the second input is a first value, And an inverter circuit whose output logic value is determined by the magnitude of the potential of the internal node and a threshold value. The method of claim 10, The switch element connected to the control terminal with the first input connected to the first power supply; the switch element connected with the control terminal with the second input connected to the second power supply side; A clock control circuit comprising the same number of switch elements as a load. The method according to any one of claims 2 to 5, The timing averaging circuit A first switch element connected between the first power supply and the first internal node; A first to turn on the first switch element when the first and second input signals are input, and an output terminal is connected to a control terminal of the first switch element, and the first and second input signals are both first values; Logic circuits, A second switch element connected in series between the first internal node and a second power supply, the second switch element being turned off and on when the first input signal is the first value and the second value, respectively, and the value of the output signal being the first value; A third switch element that is turned on and off when the value is the second value, A fourth switch element connected in series between the first internal node and the second power supply and turned off and on when the second input signal is the first value and the second value, respectively; A fifth switch element that is turned on and off when the first value and the second value are respectively; A sixth switch element connected between the first power source and a third internal node and inputting the first internal node to a control terminal; A seventh switch element connected between the second power supply and the second internal node, A second logic for inputting the first and second input signals and for turning on the seventh switch element when an output is connected to a control terminal of the seventh switch element and both the first and second inputs are of a second value; Circuits, An eighth switch element connected in series between the second internal node and the first power supply, the eighth switch element being turned on and off when the first input signal is the first value and the second value, respectively, A ninth switch element that is turned off and on when the value is the first value and the second value, A tenth switch element connected in series between the second internal node and the first power supply and turned on and off respectively when the second input signal is the first value and the second value, and a value of the output signal is An eleventh switch element that is turned off and on when the first value and the second value are respectively; A twelfth switch element connected between the second power supply and the third internal node and inputting the second internal node to a control terminal; An inverter circuit for inputting the third internal node to an input terminal and having an output logic value determined by the magnitude of the third internal node potential and a threshold value; A first switch element pair consisting of the third switch element and the fifth switch element based on the first and second input signals, and a second switch element pair consisting of the ninth switch element and the eleventh switch element And a circuit means for controlling on and off, respectively. The method according to any one of claims 2 to 5, The timing averaging circuit A first switch element connected between the first power supply and the first internal node; A first to turn on the first switch element when the first and second input signals are input, and an output terminal is connected to a control terminal of the first switch element, and the first and second input signals are both first values; Logic circuits, A second switch element connected in series between the first internal node and a second power supply, the second switch element being turned off and on respectively when the first input signal is the first value and the second value, and the output signal value is the first value; A third switch element turned on and off when the second value is respectively; A fourth switch element connected in series between the first internal node and the second power supply, the fourth switch element being turned off and on when the second input signal is the first value and the second value, respectively, A fifth switch element that is turned on and off when the value is the first value and the second value, respectively; A sixth switch element connected between the first power source and a third internal node and inputting the first internal node to a control terminal; A seventh switch element connected between the second power supply and the second internal node, A second logic for inputting the first and second input signals and for turning on the seventh switch element when an output is connected to a control terminal of the seventh switch element and both the first and second inputs are of a second value; Circuits, An eighth switch element connected in series between the second internal node and the first power supply, the eighth switch element being turned on and off when the first input signal is the first value and the second value, respectively, and the output signal value is the first value; A ninth switch element that is turned off and on when the value is the second value, A tenth switch element connected in series between the second internal node and the first power supply and turned on and off respectively when the second input signal is the first value and the second value, and a value of the output signal is An eleventh switch element that is turned off and on when the first value and the second value are respectively; A twelfth switch element connected between the second power supply and the third internal node and inputting the second internal node to a control terminal; An inverter circuit for inputting the third internal node to an input terminal and having an output logic value determined by the magnitude of the third internal node potential and a threshold value; The output of the buffer circuit for generating the electrostatic signal of the output signal at the same time as the output signal is output from the output terminal of the inverter circuit is the third switch element, the fifth switch element, the ninth switch element, and the 11 A clock control circuit comprising a common connection to a control terminal of a switch element. The method according to any one of claims 2 to 5, The timing averaging circuit A first switch element connected between the first power supply and the first internal node; A first to turn on the first switch element when the first and second input signals are input, and an output terminal is connected to a control terminal of the first switch element, and the first and second input signals are both first values; Logic circuits, A second switch element connected in series between the first internal node and a second power supply, and a third switch, wherein the second switch element is respectively provided when the first input signal is the first value and the second value; Being on, off, And a fourth switch element connected in series between the first internal node and the second power supply, and a fifth switch, wherein the fourth switch element has the second input signal being the first value and the second value. When each is off, on, A sixth switch element connected between the first power source and a third internal node and inputting the first internal node to a control terminal; A seventh switch element connected between the second power supply and the second internal node, A second input of the first and second input signals, the output of which is connected to a control terminal of the seventh switch element, and the seventh switch element turned on when the first and second input signals are both second values; Logic circuits, An eighth switch element and a ninth switch element connected in series between said second internal node and said first power source, said eighth switch element each having said first input signal having a first value and a second value, respectively; On and off, And a tenth switch element and an eleventh switch element connected in series between the second internal node and the first power source, wherein the tenth switch element has the first input signal being the first value and the second value. When each is on and off, A twelfth switch element connected between the second power supply and the third internal node and inputting the second internal node to a control terminal; An inverter circuit for inputting the third internal node to an input terminal and having an output logic value determined by the magnitude of the third internal node potential and a threshold value; An output of the first logic circuit is connected to control terminals of the ninth switch element and the eleventh switch element, And an output of the second logic circuit is connected to control terminals of the third switch element and the fifth switch element. The clock integrated circuit provided with the clock control circuit as described in any one of Claims 2-5, and supplies the clock output from the said clock control circuit to the clock utilization circuit which needs supply of a clock. Circuitry. The method of claim 4, wherein And first and second multiplication circuits for multiplying and outputting the output signals from said first and second timing averaging circuits, respectively. The method of claim 16, A divider for dividing a clock inputted by the multiplication circuit to generate and output a plurality of clocks (called "polyphase clocks") having different phases; A cycle detection circuit for detecting a cycle of the input clock; A multiphase clock multiplication circuit for generating a multiphase clock multiplied by the multiplied clock output from the divider as an input; A plurality of timing difference dividing circuits for outputting a signal obtained by dividing a timing difference between two inputs by said polyphase clock multiplication circuit, and a plurality of multiplexing circuits for multiplexing and outputting outputs of said two timing difference dividing circuits, And the timing difference dividing circuit includes a timing difference dividing circuit for inputting clocks of the same phase and a timing difference dividing circuit for inputting two clocks of neighboring phases.

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