KR100613387B1 - Contact Forming Method in Low Power Semiconductor Devices - Google Patents

Abstract

A method of forming a contact in a low power semiconductor device is provided. According to the present invention, a transistor device including a gate electrode and an active region of a source / drain is formed on a semiconductor substrate, and an etch stop layer covering the gate electrode and the active region is formed, wherein the etch stop layer on the gate electrode is formed. An etch stop layer is formed that is thicker than the thickness of the second portion of the etch stop layer on the active region. Forming an interlayer insulating film covering the etch stop film and selectively etching the film, using the etch stop film to etch stop to form a first contact hole exposing the gate electrode and a second contact hole exposing the active region; The second contact hole is filled to form first and second contacts respectively connected to the gate electrode and the active region.

Low Power Devices, Silicides, Etch Stops, Contacts, Active Junctions

Description

Method for forming contacts in low power semiconductor device

1 and 2 are cross-sectional views schematically illustrating a method for forming a contact in a conventional semiconductor device.

3 to 5 are cross-sectional views schematically illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to forming a contact in a low power semiconductor device using a fully non-salicided process without applying the salicide process. It is about how to.

The process of forming a contact for connection wiring in the process of manufacturing a semiconductor device is a very important process. For example, after forming a transistor element as an active element on a semiconductor substrate, an active region for electrical connection to the drain region of the transistor and the first contact in contact with the gate of the transistor. The second contact in contact with) is formed by one contact forming process. However, since there is a step between the gate and the active region, an etch stop layer is introduced in the process of forming the contact to overcome the step and simultaneously form two contact holes having different depths in one process. have.

In particular, low power semiconductor devices and low leakage current (Low Leakage Current) rather than the operating speed (speed) of the device is a key issue, the salicide process is not applied, and a completely non-salicide process is applied a lot. In such a device, since a silicide layer is not formed on the polysilicon of the gate or the active region of the substrate, the contact hole is directly formed in the active region or the gate electrode layer. Accordingly, the contact formation result is sensitively changed according to the contact hole etching depth, the doping conditions of the gate electrode and the active region. Therefore, compared to the case where the contact hole is formed in the silicide layer is introduced, the etching control is very difficult when forming the contact hole.

In the case of applying the completely non-salicide process, the sheet resistance (Rs) or the contact resistance (Rc) is increased by several orders of magnitude compared with the salicide process, but the leakage current of the device is rapidly reduced. In the formation of a contact in such a completely non-salicide process, yield and quality deterioration while the contact in the active region is etched stop in the just etch or under etch to the etch stop layer. Frequently occurs.

As the contact hole is formed directly on the active region or the gate poly without the silicide layer, the resistance is sensitively changed according to the etching depth and the doping conditions of the contacted surface. The contact hole on the active region is compared with the contact hole on the gate polysilicon. To open, a relatively long etching time is required due to the difference in interlayer insulating film thickness due to the step difference. Both the gate poly and active contact holes must be formed so that the contact holes enter the surface a little each over a slight overetch, and as described above, this depth is very important for non-salicide contacts. That is, the optimum resistance condition is found according to the contact hole depth, and the process margin is naturally narrowed compared to the contact process formed on the silicide layer.

In order to fully etch the active contact during the formation of a contact hole in a fully non-salicide process, when the etching is excessively large, the etch amount of the gate polysilicon layer becomes large, and the surface layer becomes silicon fluoride (SiF _x ). The contamination causes a problem of increasing the contact resistance on the gate polysilicon. Accordingly, when forming contact holes in a completely non-salicide process, the contact etching conditions are appropriately adjusted to find a condition in which both the gate polysilicon and the contact hole formation for the active region are satisfied. However, this process itself has no process margin depending on the thickness of the CMP (Chemical Mechanical Polishing) for the interlayer insulating film between the gate polysilicon and the metal-1 and the etching chamber conditions or the subsequent cleaning process. As a result, the contact hole of the active phase is etched only up to the etch stop layer, and then the etching stops undesirably, resulting in wafer loss due to low yield and quality deterioration.

In the case of silicon nitride (Si ₃ N ₄ ) used as an etch stop layer, under etching may occur due to a drop in etching speed due to a rise in wafer temperature caused by plasma during contact hole etching. In particular, the wafer edge region (wafer edge region) is more severe, and the higher the degree of integration of the contact hole, the more etch stop phenomenon is rapidly increased. Furthermore, in a completely non-saliside process, there is a thin oxide layer of about 150 Å between the etch stop film (or barrier layer) and active, so that the etch stop film is of course underetched. The contact resistance defects still occur even in the just etched state where all of them are etched and stopped.

1 and 2 are cross-sectional views schematically illustrating a method for forming a contact in a conventional semiconductor device.

Referring to FIG. 1, an isolation layer 12 for isolation between devices is formed on a semiconductor substrate 10 by a shallow trench isolation (STI) process. Thereafter, the gate electrode 14, the sidewall spacer 16, the active region 18 of the source / drain, the etch stop layer 20, and the interlayer insulating layer 22 are sequentially formed. .

In this case, the sidewall spacers 16 may be formed to include silicon nitride. In addition, the etch stop layer 20 may include a silicon nitride layer (SiN). The etch stop film 20 may be understood as a barrier film, which serves as an etch stop to prevent excessive etching during contact hole etching, and is used for the interlayer insulating film 22 introduced between the gate polysilicon and the metal-1. The B and P dopants of the BPSG (Boron-Phosphorus Silicate Glass) film may also serve as a barrier to prevent diffusion of the B and P dopants into the semiconductor substrate 10. The thickness of the etch stop film 20 is deposited to a thickness of about 350 kPa, which is less than half of the thickness of the sidewall spacers 16. In addition, the gate electrode 14 may use a doped polysilicon layer in consideration of the fact that the contact is formed directly without the silicide layer.

Referring to FIG. 2, the first contact 24a is formed on the gate electrode through the contact hole etching, and the second contact 24b is formed on the active region 18. 2 illustrates a case where the contact formed in the active region 18 is just etched. However, when the second contact 24b formed in the active region 18 when forming the contact hole according to the related art is etched off on the etch stop layer 20 due to the above-described problems, there is no process margin. And a high contact hole density, the probability is increased. As well as under etching in the etch stop layer 20, even in the case of just etching where the etch stops after all of the etch stop layer 20 is etched, as shown in FIG. Done.

Thus, in the normal case, the contact hole is slightly deeper into the active surface. Therefore, in the prior art, low yield and quality problems and wafer loss are always recognized as problems due to lack of process margins.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a contact for a semiconductor device capable of preventing an unwanted etch stop phenomenon frequently occurring in a contact on an active region.

One embodiment of the present invention for the above technical problem, introduces a process of inducing the thickness of the etch stop layer on the active phase to be lower than the thickness on the gate to prevent unwanted etching stop on the active region.

One embodiment of the present invention described above,

Forming a transistor device comprising a gate electrode and an active region of a source / drain on a semiconductor substrate;

Forming an etch stop layer covering the gate electrode and the active region, wherein an etch stop layer having a thickness of a first portion of the etch stop layer on the gate electrode is thicker than a thickness of a second portion of the etch stop layer on the active region;

Forming an interlayer insulating film overlying the etch stop film;

Selectively etching the interlayer insulating layer, using the etch stop layer to etch stop to form a first contact hole exposing the gate electrode and a second contact hole exposing the active region; And

Forming a first contact connected to the gate electrode by filling the first contact hole, and forming a second contact connected to the active region by filling the second contact hole; Give a way.

Here, the step of forming the etch stop film,

Forming a layer covering the gate electrode and the active region and having an etch selectivity with the interlayer dielectric layer;

Forming an etch mask that selectively exposes a portion of the layer covering the active region; And

Selectively etching the portion of the layer exposed by the etching mask to reduce the thickness.

The forming of the etch mask may include forming a photoresist layer covering the interlayer insulating layer and a layer having an etch selectivity, and exposing and developing the photoresist layer by using a mask for the gate electrode. And forming a resist pattern.

The selective etching to reduce the thickness may be performed by etching away approximately 15-25% of the thickness of the exposed layer portion.

Alternatively, the selective etching to reduce the thickness may be performed by etching away from 60 to 80 kPa when the initial thickness of the exposed layer portion is about 350 kPa.

The second portion of the etch stop layer may be formed to be about 75 to 85% thicker than the first portion of the etch stop layer.

The etch stop layer may be formed including a silicon nitride layer.

The etch stop layer may be formed by directly contacting the gate electrode and the active region without introducing a silicide layer.

The gate electrode may be formed including a conductive polysilicon layer.

The gate electrode may further include forming sidewall spacers including silicon nitride on sidewalls.

According to the present invention, it is possible to provide a method for forming a contact of a semiconductor device capable of preventing an unwanted etch stop phenomenon frequently occurring in a contact on an active region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the thickness of the etch stop layer deposited on the gate polysilicon layer is obtained by depositing the silicon nitride layer as an etch stop layer and then using a photo-etching process using an gate mask and an etching process. Suggests a slightly thinner technique. Accordingly, the process margin can be secured when forming the contact hole, and the etch stop phenomenon occurring in the contact with the active region can be prevented. Therefore, it is possible to provide a contact formation method capable of preventing contact failure from occurring in a device employing a completely non-salicide process.

3 to 5 are cross-sectional views schematically illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, an embodiment of the present invention employs a fully non-salicide process to form a transistor device. Specifically, the device isolation layer 102 for device isolation on the semiconductor substrate 100 is formed by a shallow trench device isolation (STI) process. For example, after forming the trench on the semiconductor substrate 100, an insulating film including a silicon oxide film filling the trench is formed to form the device isolation film 102.

Subsequently, a gate electrode 104 is formed along with an interface of the gate oxide film (not shown) with the semiconductor substrate 100. The gate electrode 104 may be formed to include a polysilicon film that is conductive by being doped with impurities. The sidewall spacers 106 are formed on the sidewalls of the gate electrode 104. The sidewall spacers 106 are formed by depositing a layer including a silicon nitride film and the like and then etching the spacers. Thereafter, the active region 108 of the source / drain is formed by implanting impurities into a portion of the semiconductor substrate 100 adjacent to the gate electrode 104.

Thereafter, an etch stop layer 200 is formed to cover the gate electrode 104 and the active region 108 of the source / drain. The etch stop layer 200 is formed by including a layer of a material having an etch selectivity with an interlayer insulating layer to be formed thereon, for example, a silicon nitride layer. In this case, the silicon nitride layer may be formed to a thickness of about 350Å.

After the etch stop layer 200 is formed, a portion of the etch stop layer 200 positioned on the active region 108 including the source / drain regions is selectively etched to reduce its thickness. To this end, an etch mask 300 is formed to selectively cover a portion of the etch stop layer 200 overlapping the gate electrode 104. For example, after the photoresist film is formed on the etch stop film 200, a photolithography process is performed to expose and develop the photoresist film using a gate mask used to pattern the gate electrode 104. An etching mask 300 as shown is formed. Thus, the etching mask 300 may be formed in the same pattern as the gate electrode 104.

Referring to FIGS. 3 and 4, the portion of the etch stop layer 200 exposed by the etch mask 300 is selectively etched to reduce its thickness. In this case, the etching process is performed such that only about 20% of the thickness of the portion of the etch stop layer 200 exposed by the etch mask 300 is etched away. For example, the exposed etch stop layer 200 may be etched away about 60 to 80 Å. This etching process may be performed by a dry etching process. Accordingly, the etch stop layer first portion 200a having a relatively thick thickness and the etch stop layer second portion 200b having a relatively thin thickness are formed by selective etching while maintaining the deposited thickness. The etch stop layer first portion 200a covers a portion of the gate electrode 104, and the etch stop layer second portion 200b substantially covers the active region 108 that is a source / drain region. The etch stop film second portion 200b is substantially about 75 to 85% thicker than the etch stop film first portion.

Referring to FIG. 5, an interlayer insulating film 202 including a boro-phosphosilicate glass (BPSG) film is formed on the etch stop film including the etch stop film first portion 200a and the second portion 200b. do. Thereafter, a process of forming a contact is performed, that is, a first contact 204a is formed on the gate electrode 104 through contact hole etching, and a second layer is formed on the active region 108 including the source / drain regions. Contact 204b is formed.

In this case, the first contact hole aligned on the gate electrode 104 and the second contact hole aligned on the active region 108 are formed through selective dry etching.

Then, dry etching is performed to etch stop on the etch stop layer second portion 200b existing on the active region 108 including the source / drain regions, and the etch stop layer second portion exposed after the etch stop is detected. The active region 108 is exposed by removing the 200b. In this case, the etch stop layer 200a may have a thicker thickness than that of the etch stop layer 200b, and the etch stop layer 200b may be the first portion 200a. Since the etch stop layer has a relatively thin thickness, the etch stop layer first portion 200a may be sufficiently maintained until the etch stop is detected by the etch stop layer 200b. Therefore, sufficient process margin can be secured during contact etching.

Subsequently, a conductive layer filling the first contact hole and the second contact hole, for example, a conductive polysilicon film, is formed, and then polished or patterned with CMP to form the first contact 204a and the second contact 204b. .

As described above, in the exemplary embodiment of the present invention, although the contact etching is performed under the same contact hole etching conditions as the conventional conditions, the second contact which is the first contact 204a on the gate electrode 104 and the active contact on the active region 108 is formed. The contact 204b can be formed stably. Thus, despite employing a completely non-saliside process, sufficient process margin is ensured during contact etching, which can solve the problems related to resistance of the first contact 204a and the second contact 204b of polysilicon. have.

According to the present invention described above, when the contact formation of the device to which the complete non-salicide process is applied, the etch stop layer of the remaining region except for the gate electrode is about 20% of the thickness using a photolithography and an etching process using a conventional gate mask. By etching only a thin degree, it is possible to secure a process margin that is always insufficient in the prior art at the time of contact formation. Accordingly, it is possible to solve both the etch stop of the active contact and the increase in resistance of the contact on the gate electrode during the excessive etching, which used to be a problem in the related art. Accordingly, it is possible to prevent wafer scrap due to poor contact, to improve yield and quality, and to cause a large accident in which a large amount of wafers are scraped at a time due to insufficient process margin, which always acts as anxiety factor. Can be prevented.

Although the present invention has been described through specific embodiments, the present invention may be modified in various forms by those skilled in the art within the technical spirit of the present invention.

Claims (10)

Forming a transistor device comprising a gate electrode and an active region of a source / drain on a semiconductor substrate; Forming an etch stop layer covering the gate electrode and the active region, wherein an etch stop layer having a thickness of a first portion of the etch stop layer on the gate electrode is greater than a thickness of a second portion of the etch stop layer on the active region; Forming an interlayer insulating film overlying the etch stop film; Selectively etching the interlayer insulating layer, using the etch stop layer to etch stop to form a first contact hole exposing the gate electrode and a second contact hole exposing the active region; And Filling the first contact hole to form a first contact connected to the gate electrode, and filling the second contact hole to form a second contact connected to the active region; a completely non-salicide process A method for forming a contact in a low power semiconductor device characterized by using a (fully non-salicided process). The method of claim 1, Forming the etch stop layer, Forming a layer covering the gate electrode and the active region and having an etch selectivity with the interlayer dielectric layer; Forming an etch mask to selectively expose a portion of the layer covering the active region; And Selectively etching the portion of the layer exposed by the etching mask to reduce the thickness. The method of claim 2, Forming the etching mask is, Forming a photoresist layer covering the interlayer dielectric layer and a layer having an etch selectivity; And And forming a photoresist pattern by exposing and developing the photoresist layer using a mask for the gate electrode. The method of claim 2, The selective etching to reduce the thickness removes 15 to 25% of the thickness of the exposed layer portion. The method of claim 2, The selective etching of reducing the thickness removes about 60 to 80 microseconds when the initial thickness of the exposed layer portion is approximately 350 microseconds. The method of claim 1, And a second portion of the etch stop layer is about 75 to 85% thicker than a first portion of the etch stop layer. The method of claim 1, The etch stop layer is formed in contact with the semiconductor device, characterized in that formed in the silicon nitride film. The method of claim 1, And the etch stop layer is formed in direct contact with a surface of the gate electrode and the active region. The method of claim 1, And the gate electrode comprises a conductive polysilicon film. The method of claim 1, And forming sidewall spacers on the sidewalls of the gate electrodes, including silicon nitride.

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