KR100616499B1 - 반도체소자 제조 방법 - Google Patents
반도체소자 제조 방법 Download PDFInfo
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- KR100616499B1 KR100616499B1 KR1020030083157A KR20030083157A KR100616499B1 KR 100616499 B1 KR100616499 B1 KR 100616499B1 KR 1020030083157 A KR1020030083157 A KR 1020030083157A KR 20030083157 A KR20030083157 A KR 20030083157A KR 100616499 B1 KR100616499 B1 KR 100616499B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (14)
- 기판 상에 하드마스크용 절연막/전도막 구조의 복수의 도전패턴을 형성하는 단계;상기 도전패턴을 포함하는 기판 전면에 제1절연막을 형성하는 단계;상기 제1절연막을 관통하여 상기 도전패턴 사이의 상기 기판에 콘택되며, 상기 도전패턴의 상단부로부터 상기 전도막 사이의 높이를 갖는 플러그를 형성하는 단계;상기 도전패턴의 상기 하드마스크 절연막의 상부 및 측면을 덮는 어택방지막을 형성하는 단계;상기 어택방지막 상에 제2절연막을 형성하는 단계; 및상기 제2절연막을 선택적으로 식각하여 상기 플러그를 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 플러그를 형성하는 단계는,상기 제1절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 기판을 노출시키는 오픈부를 형성하는 단계;상기 오픈부를 매립하는 플러그용 전도막을 증착하는 단계;상기 하드마스크 절연막이 노출될 때까지 상기 플러그용 전도막을 제거하여 서로 분리된 상기 플러그를 형성하는 단계; 및상기 도전패턴의 상단부로부터 상기 전도막 사이의 높이를 갖도록 상기 플러그를 리세스시키는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 2 항에 있어서,상기 플러그를 분리시키는 단계에서, 화학적기계적연마 또는 전면식각을 이용하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 2 항에 있어서,상기 플러그를 리세스시키는 단계에서,C2F6/Cl2/HBr를 이용하여 전면식각하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 플러그를 형성하는 단계는,상기 제1절연막을 선택적으로 식각하여 상기 도전패턴 사이의 상기 기판을 노출시키는 오픈부를 형성하는 단계; 및선택적 에피택셜 성장 방식을 이용하여 상기 오픈부를 매립하며 상기 도전패턴의 상단부로부터 상기 전도막 사이의 높이를 갖도록 상기 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 어택방지막을 형성하는 단계는,상기 플러그가 형성된 프로파일을 따라 어택방지막을 증착하는 단계와, 상기 도전패턴의 상기 하드마스크 절연막의 상부 및 측면에만 상기 어택방지막이 남도록 전면식각을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 6 항에 있어서,상기 어택방지막은 플라즈마 화학기상증착 방식을 적용한 질화막인 것을 특징으로 하는 반도체소자 제조 방법.
- 제 7 항에 있어서,상기 전면식각하는 단계에서, CHF3/CF4 가스를 사용하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 복수의 도전패턴을 형성하는 단계 후, 상기 복수의 도전패턴이 형성된 프로파일을 따라 식각정지막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 9 항에 있어서,상기 식각정지막은, 복수의 질화막이 적층된 구조 또는 질화막과 산화막이 적층된 구조를 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 복수의 도전패턴은, 게이트전극 패턴, 비트라인 또는 금속전극 중 어느 하나를 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서,상기 콘택홀을 형성하는 단계 후, 상기 콘택홀을 매립하며 노출된 상기 플러그와 전기적으로 연결되는 전도층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조 방법.
- 제 12 항에 있어서,상기 전도층은 스토리지노드콘택 플러그인 것을 특징으로 하는 반도체소자 제조 방법.
- 제 1 항에 있어서.상기 제2절연막은, 복수의 산화막으로 이루어진 것을 특징으로 하는 반도체소자 제조 방법.
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KR1020030083157A KR100616499B1 (ko) | 2003-11-21 | 2003-11-21 | 반도체소자 제조 방법 |
US10/880,346 US7199051B2 (en) | 2003-11-21 | 2004-06-30 | Method for fabricating semiconductor device capable of preventing damages to conductive structure |
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KR1020030083157A KR100616499B1 (ko) | 2003-11-21 | 2003-11-21 | 반도체소자 제조 방법 |
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Families Citing this family (10)
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KR100732296B1 (ko) * | 2005-06-27 | 2007-06-25 | 주식회사 하이닉스반도체 | 반도체 소자의 형성 방법 |
KR100809335B1 (ko) | 2006-09-28 | 2008-03-05 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US20080116521A1 (en) | 2006-11-16 | 2008-05-22 | Samsung Electronics Co., Ltd | CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same |
US7790631B2 (en) * | 2006-11-21 | 2010-09-07 | Intel Corporation | Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal |
US8120114B2 (en) | 2006-12-27 | 2012-02-21 | Intel Corporation | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate |
US7534678B2 (en) * | 2007-03-27 | 2009-05-19 | Samsung Electronics Co., Ltd. | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby |
KR100950470B1 (ko) * | 2007-06-22 | 2010-03-31 | 주식회사 하이닉스반도체 | 반도체 메모리소자의 스토리지전극 형성방법 |
US7902082B2 (en) | 2007-09-20 | 2011-03-08 | Samsung Electronics Co., Ltd. | Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers |
US7923365B2 (en) | 2007-10-17 | 2011-04-12 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
KR102661670B1 (ko) * | 2019-08-09 | 2024-04-29 | 삼성전자주식회사 | 블로킹 층을 갖는 반도체 소자 |
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US5840624A (en) * | 1996-03-15 | 1998-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd | Reduction of via over etching for borderless contacts |
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US6888247B2 (en) * | 1999-09-03 | 2005-05-03 | United Microelectronics Corp. | Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same |
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KR100505456B1 (ko) * | 2002-11-27 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체 소자의 랜딩 플러그 형성방법 |
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US6861754B2 (en) * | 2003-07-25 | 2005-03-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device with anchor type seal ring |
-
2003
- 2003-11-21 KR KR1020030083157A patent/KR100616499B1/ko active IP Right Grant
-
2004
- 2004-06-30 US US10/880,346 patent/US7199051B2/en not_active Expired - Lifetime
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US20050112865A1 (en) | 2005-05-26 |
US7199051B2 (en) | 2007-04-03 |
KR20050049243A (ko) | 2005-05-25 |
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