KR100615573B1 - Semiconductor Memory Device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus includes a memory cell array, a plurality of sense amplifiers for amplifying and outputting data output from the memory cell array in response to a sense amplifier enable signal in a first state, and in response to a sense amplifier enable signal in a second state. A plurality of precharge means connected to an output line pair of each of the plurality of sense amplifiers for precharging the output line pair, and generating an output signal pair in the first state in response to a control signal in the second state; And a plurality of sense amplification drivers for driving a pair of output signals output from each of the plurality of sense amplifiers in response to a control signal of one state to generate a complementary data signal pair. Therefore, it is possible to prevent the read speed delay due to the ground noise when reading data.

Description

Semiconductor Memory Device

1 is a block diagram of a semiconductor memory device of a conventional embodiment.

FIG. 2 is a circuit diagram of an embodiment of the blocks shown in FIG.

FIG. 3 is an operation timing diagram for explaining the operation in the normal operation of the circuit of the embodiment shown in FIG.

FIG. 4 is an operation timing diagram for explaining the operation when the ground noise flows in the circuit of the embodiment shown in FIG.

Fig. 5 is a block diagram of a semiconductor memory device of the embodiment of the present invention.

FIG. 6 is a circuit diagram of an embodiment of the blocks shown in FIG.

FIG. 7 is an operation timing diagram for explaining the operation in the normal operation of the circuit of the embodiment shown in FIG.

FIG. 8 is an operation timing diagram for explaining the operation at the time of inflow of ground noise of the circuit of the embodiment shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of preventing a read operation speed delay caused by ground noise.

A sense amplifier of a conventional semiconductor memory device has a small size of an NMOS transistor to which a sense amplifier enable signal is applied. This is to reduce the current consumption flowing through the sense amplifier. However, since the size of the NMOS transistor to which the sense amplifier enable signal is applied is small, the sense amplifier output signal does not drop to a sufficiently low level.

However, the ground noise generated as the semiconductor memory device becomes lower and faster, has a problem in that the read operation speed of the semiconductor memory device is delayed by delaying the speed at which the sense amplifier output signal falls to the "low" level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of preventing a read operation speed delay caused by ground noise in order to solve the problems of the prior art.

The semiconductor memory device of the present invention for achieving the above object is a memory cell array, a plurality of sense amplifiers for amplifying and outputting data output from the memory cell array in response to the sense amplifier enable signal of the first state, A plurality of precharge means connected to an output line pair of each of the plurality of sense amplifiers in response to the sense amplifier enable signal of the two states, for precharging the output line pairs, and in response to a control signal of the second state. A plurality of sense amplification drivers for generating an output signal pair in one state and driving an output signal pair output from each of the plurality of sense amplifiers in response to a control signal in a first state to generate a complementary data signal pair; Characterized in that provided.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

1 is a block diagram of an embodiment of a conventional semiconductor memory device, in which memory cell array blocks 10-1, 10-2, ..., 10-n, memory cell array blocks 10-1, 10- 2, ..., 10-n) Sense amplifiers ((12-11, ..., 12-1k), (12-21, ..., 12-) for amplifying and outputting data output from each 2k), ..., (12-n1, ..., 12-nk)), sense amplifiers ((12-11, ..., 12-1k), (12-21, ..., 12 -2k), ..., (12-n1, ..., 12-nk) Precharge circuits ((14-11, ..., 14-1k) for precharging each output signal line pair ), (14-21, ..., 14-2k), ..., (14-n1, ..., 14-nk)), sense amplifier enable signals (PSA1, PSA2, ..., PSAn Delay circuits 16-1, 16-2, ..., 16-n, and sense amplifiers 12-11, ..., 12-1k, (12- 21, ..., 12-2k), ..., (12-n1, ..., 12-nk)) Drives the signal output from each output signal line pair and the corresponding main data line pair (MDL1) / B, ..., sense for output to MDLk / B) Amplification drivers ((18-11, ..., 18-1k), (18-21, ..., 18-2k), ..., (18-n1, ..., 18-nk)) Consists of

In Fig. 1, the sense amplifier is represented by SA, the precharge circuit by PRE, the sense amplifier driver by SAD, and the delay circuit by D.

FIG. 2 is a circuit diagram of the embodiment of the block diagram of the semiconductor memory device shown in FIG. 1, and is composed of a sense amplifier 12, a precharge circuit 14, a delay circuit 16, and a sense amplifier driver 18. As shown in FIG.

The sense amplifier 12 is composed of PMOS transistors P1 and P2 and NMOS transistors N1, N2 and N3. The precharge circuit 14 is composed of PMOS transistors P3, P4, and P5. The delay circuit 16 is composed of inverters I1, I2, I3. The sense amplification driver 18 is composed of PMOS transistors P6, P7, P8, and P9, and NMOS transistors N4, N5, N6, and N7.

The operation of the circuit shown in Fig. 2 is as follows.

When no read operation is performed, the sense amplifier enable signal PSA is at the "low" level. The precharge circuit 14 turns on the PMOS transistors P3, P4, and P5 in response to the "low" level sense amplifier enable signal PSA to "high" the output signal line pair of the sense amplifier 12. Precharge to level. The delay circuit 16 inverts and delays the sense amplifier enable signal PSA at the " low " level to generate a signal PSADB at the " high " level. The sense amplification driver 18 turns on the NMOS transistors N4 and N5 in response to the "high" level signal PSADB to the "low" level signals MD and MDB to the main data line pairs MDL and MDLB. )

When performing the read operation, the sense amplifier enable signal PSA transitions to the "high" level. The precharge circuit 14 turns off the PMOS transistors P3, P4, and P5 in response to the "high" level signal PSA. The sense amplifier 12 is enabled by turning on the NMOS transistor N3 in response to the sense amplifier enable signal PSA at the "high" level. When the signal pairs LD and LDB output from the local data line pair LLD and LDLB are at the "high" level and the "low" level, the NMOS transistor N1 is turned on to turn the inverted sense amplifier output signal SASB "low". The level is set, and the PMOS transistor P2 is turned on to bring the sense amplifier output signal SAS to the "high" level. The delay circuit 16 delays and inverts the signal PSA until the sense amplifier 12 fully amplifies the sense amplifier output signal pairs SASB and SAS to generate a signal PSADB of "low" level. The sense amplification driver 18 turns on the PMOS transistors P6 and P7 in response to the signal " low " level PSADB. The PMOS transistors P8 and P9 are turned on and off in response to the inverted sense amplifier output signal SASB of the "low" level and the sense amplifier output signal SAS of the "high" level, respectively. The signal pairs MD and MDB of "high" level and "low" level are respectively output to MDL and MDLB. The NMOS transistor N7 keeps the signal MDB at the "low" level in response to the signal "MD" at the "high" level, and the NMOS transistor N6 is a signal in response to the signal MDB at the "low" level. Keep MD at "high" level.

On the contrary, the circuit shown in Fig. 2 shows the main data line pairs MDL and MDLB if the signal pairs LD and LDB output from the local data line pairs LDL and LDLB are at the "low" level and the "high" level, respectively. Output signal pairs MD and MDB of "low" level and "high" level, respectively.

That is, the conventional semiconductor memory device maintains the main data line pairs MDL and MDLB at a "low" level when not performing a read operation, and from the local data line pairs LDL and LDLB when performing a read operation. The output signal is amplified and output to the main data line pairs MDL and MDLB.

FIG. 3 is an operation timing diagram for explaining the operation in the normal operation of the circuit of the embodiment shown in FIG.

When the sense amplifier enable signal PSA transitions to the "high" level, the sense amplifier 12 is enabled so that the sense amplifier output signal pairs (SAS, SASB) are at the "high" level and "low" at the "high" level. The level is earned. The sense amplification driver 18 causes the main data pairs MD and MDB to open from the "low" level to the "high" level and the "low" level in response to the "low" level signal PSADB.

FIG. 4 is an operation timing diagram for explaining the operation when the ground noise flows in the circuit of the embodiment shown in FIG.

When the sense amplifier enable signal PSA transitions to the "high" level, the sense amplifier 12 is enabled so that the sense amplifier output signal pairs (SAS, SASB) are at the "high" level and "low" at the "high" level. The level is earned. However, the noise is introduced, the level of the ground voltage is increased by the voltage (Voise). Thus, the speed at which the sense amplifier output signal falls to the "low" level is delayed. Accordingly, the sense amplification driver 18 is delayed in the rate at which the main data pairs MD and MDB transition to the "high" level.

The sense amplifier of the conventional semiconductor memory device has a small size of the NMOS transistor N3 to which the sense amplifier enable signal PSA is applied in order to reduce current consumption flowing through the sense amplifier when a read operation is performed.

Therefore, in the conventional semiconductor memory device, the sense amplifier output signal pairs SAS and SASB do not fall to the "low" level sufficiently as shown in Fig. 3 during normal operation.

However, when noise is introduced into the ground due to the low voltage and high speed of the semiconductor memory device, the speed at which the voltage of the node A falls to the "low" level becomes slow. Accordingly, as shown in FIG. 4, the speed at which the voltages of the sense amplifier output signal pairs SAS and SASB drop to the "low" level is slowed down, thereby forming the PMOS transistors P8 and P9 constituting the sense amplifier driver 18. There was a problem in that the transition speed to the "high" level of the main data pairs MD and MDB is slowed by not being turned on quickly.

5 is a block diagram of an embodiment of the semiconductor memory device of the present invention, unlike the block diagram shown in FIG. , 20-1k), (20-21, ..., 20-2k), ..., (20-n1, ..., 20-nk)) is used as a control signal for controlling .

The signals PSD1, PSD2, ..., PSDn are enabled after the signals PSA1, PSA2, ..., PSAn are enabled, and the signals PSA1, PSA2, ..., PSAn are disabled. As a signal previously disabled, it is a signal generated using an address state transition pulse.

FIG. 6 is a circuit diagram of the embodiment of the blocks shown in FIG. 5, which is comprised of a sense amplifier 12, a precharge circuit 14, and a sense amplifier driver 20. As shown in FIG.

In FIG. 6, the configuration of the sense amplifier 12 and the precharge circuit 14 is the same as the circuit configuration shown in FIG. The sense amplification driver 20 includes a NAND gate NA1 composed of PMOS transistors P10 and P11 and NMOS transistors N8 and N9 for non-logically multiplying the inverted sense amplifier output signal SASB and the signal PSD. The NAND gate NA2 includes PMOS transistors P12 and P13 and NMOS transistors N10 and N11 for non-logically multiplying the amplifier output signal SAS and the signal PSA.

The operation of the circuit shown in Fig. 6 is as follows.

When the read operation is not performed, the sense amplifier enable signal PSA and the signal PDS are at " low " levels. The sense amplifier 12 is disabled by turning off the NMOS transistor N3, and the precharge circuit 14 responds to the "low" level sense amplifier enable signal PSA in response to the PMOS transistors P3, P4, and P5. ) Is on to precharge all sense amplifier output signal pairs to the "high" level. The sense amplification driver 20 turns on the PMOS transistors P10, P11, P12, and P13 in response to the "low" level signal PSA to bring the main data pair MD and MDB to the "high" level.

In the case of performing a read operation, the sense amplifier enable signal PSA transitions to the "high" level, and after a predetermined time, the signal PSD transitions to the "high" level. The sense amplifier 12 is enabled by turning on the NMOS transistor N3 in response to the sense amplifier enable signal PSA at the "high" level. The sense amplifier 12 switches the sense amplifier output signal pairs SAS and SASB from the "high" level to the "low" level and the "high" if the local data pairs LD and LDB are at the "high" level and the "low" level, respectively. Make it to level. The sense amplification driver 20 turns on the NMOS transistors N9 and N11 in response to the "high" level signal PSD, and sense amplifier output signal pairs (SAS and SASB) of "low" level and "high" level. ), The PMOS transistor P11 and the NMOS transistor N10 are turned on to output main data pairs MD and MDB of the "high" level and the "low" level, respectively.

On the other hand, if the signal pairs LD and LDB output from the local data line pair LDL and LDLB are at the "low" level and the "high" level, respectively, they are the "low" level as the main data line pair MDL and MDLB respectively. Outputs the "high" level main data pair (MD, MDB).

FIG. 7 is an operation timing diagram for explaining the operation during the normal operation of the circuit of the embodiment shown in FIG.

When the sense amplifier enable signal PSA transitions to the "high" level, the sense amplifier 12 is enabled so that the sense amplifier output signal pairs (SAS, SASB) are at the "high" level and "low" at the "high" level. The level is earned. The sense amplification driver 20 opens from the "low" level to the "high" level and the "low" level in response to the "high" level signal PSD. However, the voltage VA of the node A does not drop to a sufficiently low level because the size of the NMOS transistor N3 constituting the sense amplifier 12 is small.

FIG. 8 is an operation timing diagram for explaining the operation at the time of inflow of ground noise of the circuit of the embodiment shown in FIG.

When the sense amplifier enable signal PSA transitions to the "high" level, the sense amplifier 12 is enabled so that the sense amplifier output signal pairs (SAS, SASB) are at the "high" level and "low" at the "high" level. The level is earned. However, the noise is introduced, the level of the ground voltage is increased by the voltage (Voise). Thus, the speed at which the sense amplifier output signal falls to the "low" level is delayed. The sense amplification driver 20 causes the main data pairs MD and MDB to open from the "high" level to the "high" level and the "low" level in response to the "high" level signal PSD.

As can be seen from Figs. 7 and 8, the semiconductor memory device of the present invention has the same timing of generating the main data pairs MD and MDB during normal operation and when the ground noise is introduced.

That is, the sense amplification driver 20 of the present invention sets the main data pairs MD and MDB to the "high" level when no read operation is performed. When performing the read operation, one data of the main data pairs MD and MDB maintains a "high" level, and the other data transitions to a "low" level. However, the sense amplification driver 20 makes the main data transition to the "low" level in response to the sense amplifier output signal of the "high" level so that it is not affected by the ground noise.

In conclusion, the sense amplifier of the semiconductor memory device of the present invention causes the output signal of the "high" level sense amplifier to be sufficiently raised to the power supply voltage level, while the output signal of the "low" level sense amplifier is sufficiently lowered to the ground voltage level. Can't let go Thus, when the sense amplification driver transitions the main data to the "high" level in response to the output signal of the "low" level sense amplifier, the signal PSD is disabled to cause the main data to transition to the "high" level. In this case, when the sense amplifier output signal of the "low" level is applied to the sense amplifier driver 20, the main data is directly transitioned to the power supply voltage level. Therefore, the speed delay due to the inflow of ground noise does not occur.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand that you can.

The semiconductor memory device of the present invention can prevent a read operation speed delay caused by ground noise when reading data.

Claims (3)

Memory cell arrays; A plurality of sense amplifiers for amplifying and outputting data output from the memory cell array in response to a sense amplifier enable signal in a first state; A plurality of precharge means connected to an output line pair of each of the plurality of sense amplifiers in response to a sense amplifier enable signal in a second state to precharge the output line pair; And A pair of output signals in a first state is generated in response to a control signal in a second state; And a plurality of sense amplification drivers for generating a pair. The method of claim 1, wherein the control signal is And wherein the sense amplifier enable signal is enabled and enabled after a predetermined time, and is disabled before a predetermined time before the sense amplifier enable signal is disabled. The method of claim 1, wherein each of the plurality of sense amplification drivers A first NAND gate for non-logically multiplying an inverted output signal output from the sense amplifier and the control signal to generate the data signal; And And a second NAND gate for non-logically multiplying the output signal output from the sense amplifier and the control signal to generate the inverted data signal.

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