KR100608381B1 - Data output circuit of a synchronous memory device - Google Patents

Abstract

A synchronous memory device having a plurality of pipe latches having a 4-bit prefetch function is provided.

The proposed pipe latch includes data switching units 411 and 421 for receiving 4-bit data, data selecting units 412 and 422 for selecting data output from the data switching unit, and delay time of the control signal pout. The shifter 431 includes a shifter 432 for delaying data output from the data selector 422.

Description

Data output circuit of a synchronous memory device

1 is an example of a data output circuit of a general memory device.

Fig. 2 is a table for explaining the output order of data according to the lower two bits (starting column address) of the column address applied at the read command and the data output mode (interleaved or sequential mode).

3 is a specific example of the pipe latch shown in FIG.

4A and 4B are examples of the data output circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit of a synchronous memory device, and more particularly to a data output circuit that determines the output order of data output to the outside of the memory device according to a column address and burst type applied during a read command.

In general, in a synchronous memory device (hereinafter referred to as a memory device), data read from a memory cell in response to a read command is amplified by a sense amplifier, then transferred to a global bus line, and then the pipe latch and output driver It passes through the process to the outside. The present invention focuses on a method of processing data applied to a pipe latch through a global bus line in this process, which will be described in detail with reference to FIGS. 1 and 2.

1 is an example of a data output circuit of a general memory device, in particular an example of a data output circuit having a 4-bit prefetch function. Fig. 2 is a table for explaining the output order of data according to the lower two bits (starting column address) of the column address applied at the read command and the data output mode (interleaved or sequential mode).

In Fig. 1, "gio1 <0: 3>, gio2 <0: 3>, gio3 <0: 3>, gio4 <0: 3>" represent different global bus lines, each of which has four bits of Data q <0: 3> is passed to the corresponding pipe latches 101, 102, 103, 104.

Each pipe latch 101 to 104 receives the enable signals P1N1, P1N2, P1N3, and P1N4 corresponding thereto, and a plurality of control signals, respectively. That is, the pipe latch 101 receives signals (soseb0 <0>, soseb1r <0>, soseb1f <0>, rpout <0>, fpout <0>, and the pipe latch 102 receives the signal (soseb0 <1). >, soseb1r <1>, soseb1f <1>, rpout <1>, fpout <1>, and pipe latch 103 receives signals (soseb0 <2>, soseb1r <2>, soseb1f <2>, rpout <2>, fpout <2>, and the pipe latch 104 receives signals (soseb0 <3>, soseb1r <3>, soseb1f <3>, rpout <3>, fpout <3>).

The output signal of each pipe latch is input to the pre-driver 105, and the data applied to the pre-driver 105 is transferred to the output driver (not shown) in synchronization with the synchronization signals rclk_do and fclk_do. Here, the synchronization signals rclk_do and fclk_do are internal clock signals output from the DLL circuit in the synchronous memory device.

3 is a specific example of the pipe latch 101 shown in FIG. For reference, the configuration of the pipe latches 102, 103, 104 is the same as that of the pipe latch 101.

As shown in FIG. 3, the input terminal in1 receives the data q0, the input terminal in2 receives the data q1, the input terminal in3 receives the data q2, The input terminal in4 receives the data q3. Data q0 to q3 represent data applied to the pipe latch via the global bus line.

Signal (soseb0) is an abbreviation of "start odd start even bar", the logical value of the signal (soseb0) is the least significant two-bit value of the column address (hereinafter referred to as "starting column address") and data applied to the read command Determined by the output order mode (see FIG. 2). For reference, the data output order mode is a mode for determining the output order of data, which includes a sequential mode and an interleaved mode.

The enable signal PIN1 is a signal for determining whether to enable the buffer for receiving the data q0 to q3.

Signal (soseb1_r) and signal (soseb1_f) is a switching signal, the signal (soseb1_r) determines the output order of the data passing through the node (pre_rdo <0>) and the data passing through the node (pre_rdo <1>), the signal (soseb1_f) determines the output order of data passing through the node (pre_fdo <0>) and data passing through the node (pre_fdo <1>).

The signals rpout and fpout are signals for enabling the output buffer of the pipe latch, and the nodes pre_rdo <0> and (pre_rdo <1>) through the output nodes rdo and fdo of the output buffer of the pipe latch. The data on, pre_fdo <0>, (pre_fdo <1>) is output.

In operation, for example, as shown in Fig. 2, when the start address is " 00 " and in sequential mode, the signal sosb0 is low level. In this case, as can be seen from FIGS. 2 and 3, the data q0 is output through the node pre_rdo <0>, the data q2 is output through the node pre_rdo <1>, and the node pre_fdo Data q1 is output through <0>, and data q3 is output through node pre_fdo <1>.

Next, when the signal (soseb1_r) is at the low level, the data q0 on the node (pre_rdo <0>) is passed through the output buffer to the node (rdo), and after 1tCK, when the signal (soseb1_r) is at the high level, the node (pre_rdo) Data q2 on < 1 > is passed through the output buffer to node rdo. Here, 1tCK means the period of the clock signal used in the synchronous memory device.

Similarly, data q1 on node pre_fdo <0> is passed through the output buffer to node fdo when the signal sob1_f is at low level, and node pre_fdo when signal 1bCK is at high level after 1tCK. Data q3 on < 1 > is passed through the output buffer to node fdo. At this time, since the signal seb1_f is operated by a delay of 1 / 2tCK than the signal seb1_r, the data applied to the pre-driver 105 of FIG. 1 is applied in the order of q0, q1, q2, and q3. That is, when the starting column address is 0 and in the sequential mode, the data applied to the predriver is applied in the order of q0, q1, q2, and q3.

As another example, when the starting column address is 3 and in the interleaved mode, data q1 is delivered to node pre_rdo <0>, data q3 is delivered to node pre_rdo <1>, and node pre_fdo. Data q0 is delivered to <0>, and data q2 is delivered to node pre_fdo <1>. In this case, the signal "soseb1_r" maintains a high level at first and a low level after 1 tCK. In addition, the signal (soseb1_f) which is output by being delayed 1 / 2tCK than the signal (soseb1_r) also maintains a high level at first and a low level after 1tCK. Therefore, q3 and q1 are sequentially output through the node rdo, and q2 and q0 are sequentially output through the node fdo. As a result, the data applied to the predriver is applied in the order of q3, q2, q1 and q0.

The operation of the remaining pipe latches 102 to 104 shown in FIG. 1 is the same as the operation described with reference to FIG. 3. However, depending on the enable timing of the enable signals PIN2, PIN3, and PIN4 applied to the pipe latches 102 to 104, the operation timing of the pipe latches is different. In general, since the output nodes rdo and fdo of the pipe latch shown in FIG. 1 are commonly used, the enable signals PIN1 to PIN4 are sequentially enabled in a non-overlapping range to operate each pipe latch. For reference, data output from the circuit of FIG. 1 and applied to a data output buffer (not shown) is output to the outside through one data pin. Therefore, when the number of data pins is N, it means that there are N circuits in FIG.

In addition, the signals illustrated in FIG. 3 (soseb1_r, soseb1_f, rpout, and fpout) are independent signals applied to each pipe latch individually. Thus, although not shown, the circuit for generating the signals (soseb1_r, soseb1_f, rpout, fpout) transfers the signals to the pipe latch using 16 signal lines.

However, as described above, since each pipe latch constituting the conventional data output circuit described with reference to FIGS. 1 and 3 uses independent signals corresponding thereto (soseb1_r, soseb1_f, rpout, and fpout), these pipe latches transmit these signals. The arrangement of signal lines is essential. For example, if the number of data pins is N, 16 × N signal lines are arranged. This results in a problem of lowering the layout efficiency of the highly integrated memory device.

The present invention has been proposed to solve the above problems, and proposes a method of efficiently using a layout area by reducing signals used for controlling a data output circuit.

In the data output circuit of a synchronous memory device having a plurality of pipe latches having an N-bit prefetch function according to an embodiment of the present invention, each of the pipe latches receives N-bit data and is supplied with a starting column address and data applied during a read command. A data switching unit for switching the output path of the N-bit data in accordance with an output mode; A first data selector which receives half of data of the N bits of data output from the data switching unit and sequentially outputs the half data in response to a first control signal; Receives half of the data except for the half of the data applied to the first data selector among the N bits of data output from the data switching unit, and sequentially processes the remaining half of the data in response to the first control signal. A second data selection unit outputting the data; A first shifter configured to output a second control signal delayed by a first time after receiving the first control signal; A second shifter for outputting the data received from the second data selection unit after receiving the data output from the second data selection unit, delaying the first time, and outputting the data received from the second data selection unit in response to the second control signal; ; The first time corresponds to half (1/2 tCK) of the clock signal period tCK applied to the synchronous memory device, and the time point at which data is first output from the second data selector is the first data selection. A data output circuit of a synchronous memory device, characterized in that 1 / 2tCK is earlier than the time at which data is first output from the negative side.

In the present invention, the first data selector includes a first switch turned on / off by a third control signal and a first buffer configured to enable or disable the second data by the first control signal. The selector includes a second switching unit turned on / off by a fourth control signal and a second buffer configured to be enabled or disabled by the first control signal, and the first and second switching units are configured from the data switching unit. Receives data output, data passing through the first switching unit is applied to the first buffer, data passing through the second switching unit is applied to the second buffer, and the output of the first buffer is the first buffer. An output of one data selector is provided, and an output of the second buffer is an output of the second data selector.

According to an embodiment of the present invention, the apparatus may further include a pre-driver configured to receive data sequentially output through the first data selector and data sequentially output through the second shifter, and to output data from the first data selector. Data output from the second shifter is alternately applied to the predriver.

In the present invention, each of the plurality of pipe latches share the predriver.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The present invention is characterized by the configuration of the pipe latch and the signal applied to the pipe latch among the basic circuit blocks shown in FIG. In addition, unless otherwise specified, the signals used by the same reference numerals in FIGS. 3 and 4A to 4C are signals having the same function. For reference, since the pipe latch of the present invention is equally applied to the circuit block of FIG. 1, the structure and operation of the pipe latch, which is a feature of the present invention, will be described below.

4A is an example of a data output circuit according to the present invention.

In Fig. 4A, "gio1 <0: 3>, gio2 <0: 3>, gio3 <0: 3>, gio4 <0: 3>" represent different global bus lines, each of which is a 4-bit Data q <0: 3> is passed to the corresponding pipe latches 401, 402, 403, 404.

Each pipe latch 401 to 404 receives the enable signals P1N1, P1N2, P1N3, and P1N4 corresponding thereto, and a plurality of control signals, respectively. That is, the pipe latch 401 receives signals (soseb0 <0>, soseb1r <0>, soseb1f <0>, pout <0>), and the pipe latch 402 receives signals (soseb0 <1>, soseb1r <1). >, soseb1f <1>, pout <1>), pipe latch 403 receives signals (soseb0 <2>, soseb1r <2>, soseb1f <2>, pout <2>), and pipe latch 404 receives signals (soseb0 <3>, soseb1r <3>, soseb1f <3>, pout <3>). The output signal of each pipe latch is input to the pre-driver 105 (the same circuit as that of FIG. 1), and the data applied to the pre-driver 105 is synchronized with the synchronization signals rclk_do and fclk_do to output the driver (not shown). Is delivered to. Here, the synchronization signals rclk_do and fclk_do are internal clock signals output from the DLL circuit in the synchronous memory device.

4B and 4C are specific examples of the pipe latch 401 shown in FIG. 4A. For reference, the configuration of the pipe latches 402, 403, 404 is the same as that of the pipe latch 401.

4B and 4C are examples of pipe latches having a 4-bit prefetch function in accordance with the present invention.

The pipe latches of FIGS. 4B and 4C include data switching units 411 and 421, data selection units 412 and 422, and shifters 431 and 432.

The data switching unit 411 includes buffers 41 and 42, latches 43 and 44, and switches T1 to T4.

Buffer 41 receives data q0 delivered over the global bus line, and buffer 42 receives data q1 delivered over the global bus line. The buffers 41 and 42 have the function of an inverter for inverting the logic level of the input data. As illustrated, whether the buffers 41 and 42 are operated by the enable signal PIN is determined. That is, when the enable signal PIN is at the low level, the buffers 41 and 42 are enabled. When the enable signal PIN is at the low level, the buffers 41 and 42 are disabled.

The latch 43 is a circuit that receives and holds the output signal of the buffer 41. The latch 44 is a circuit that receives and holds the output signal of the buffer 42. As shown, latches 43 and 44 invert and hold the logic level of the received data.

The switches T1 to T4 are turned on / off by a signal sosb0. Here, the signal (soseb0) is the same as the signal described in the prior art. That is, the signal "soseb0" is an abbreviation of "start odd start even bar", and the logic value of the signal "soseb0" is the value of the least significant two bits of the column address applied at the read command (hereinafter referred to as "starting column address"). And the data output order mode.

As shown, the switches T1 and T4 are turned on when the signal (soseb0) is at a low level and turned off when at a high level. The switches T2 and T3 are turned on when the signal (soseb0) is at a high level and turned off when at a low level. The output node of latch 43 is connected to the input nodes of switches T1 and T3, and the output node of latch 44 is connected to the input nodes of switches T2 and T4. Output nodes of the switches T1 and T2 are commonly connected, and output nodes of the switches T3 and T4 are commonly connected. Thus, for example, when the signal sob0 is low level, the switches T1 and T4 are turned on and the switches T2 and T3 are turned off. Therefore, data stored in the latch 43 is output to the output node of the switch T1, and data stored in the latch 44 is output to the output node of the switch T2. On the other hand, when the signal sob0 is at a high level, the switches T1 and T4 are turned off and the switches T2 and T3 are turned on. Therefore, data stored in the latch 44 is output to the output node of the switch T2, and data stored in the latch 43 is output to the output node of the switch T3.

The data switching unit 421 includes buffers 51 and 52, latches 53 and 54, and switches T5 to T8.

The buffer 51 receives data q2 delivered over the global bus line, and the buffer 52 receives data q3 delivered over the global bus line. The buffers 51 and 52 have the function of an inverter for inverting the logic level of the input data. As illustrated, whether the buffers 51 and 52 are operated by the enable signal PIN is determined. That is, when the enable signal PIN is at the low level, the buffers 51 and 52 are enabled. When the enable signal PIN is at the low level, the buffers 51 and 52 are disabled.

The latch 53 is a circuit that receives and holds the output signal of the buffer 51. The latch 54 is a circuit that receives and holds the output signal of the buffer 52. As shown, latches 53 and 54 invert and hold the logic level of the received data.

The switches T5 to T8 are turned on / off by a signal sosb0. Here, signal (soseb0) is the same as the signal signed in the prior art. As shown, the switches T5 and T8 are turned on when the signal sub0 is low and turned off when the high level. The switches T6 and T7 are turned on when the signal (soseb0) is at a high level and turned off when at a low level. The output node of the latch 53 is connected to the input node of the switches T5 and T7, and the output node of the latch 54 is connected to the input node of the switches T6 and T8. Output nodes of the switches T5 and T6 are commonly connected, and output nodes of the switches T7 and T8 are commonly connected. Thus, for example, when the signal sosb0 is at the low level, the switches T5 and T8 are turned on and the switches T6 and T7 are turned off. Therefore, data stored in the latch 53 is output to the output node of the switch T5, and data stored in the latch 54 is output to the output node of the switch T6. On the other hand, when the signal sob0 is at a high level, the switches T5 and T8 are turned off and the switches T6 and T7 are turned on. Therefore, data stored in the latch 54 is output to the output node of the switch T6, and data stored in the latch 53 is output to the output node of the switch T7.

The data selector 412 includes switches T9 and T10 and a buffer 45.

The input node of the switch T9 is connected to the common output node pre_rdo <0> of the switches T1 and T2, and the input node of the switch T10 is the common output node pre_rdo <of the switches T5 and T6. 1>). The switches T9 and T10 are turned on / off by the control signal sosb1_r. That is, when the control signal (soseb1_r) is at a high level, the switch T10 is turned on and the switch T9 is turned off. When the control signal (soseb1_r) is at a low level, the switch T9 is turned on, and the switch ( T10) is turned off. The output nodes of the switches T9 and T10 are connected in common. For reference, the logic levels of the control signals sobeb_r and soseb1_f change as shown in FIG. 2.

The buffer 45 has the function of an inverter that inverts the logic level of the signal being applied. As shown in the drawing, whether the buffer 45 is operated by the enable signal pout is determined. That is, when the enable signal pout is at the low level, the buffer 45 is enabled, and when the enable signal pout is at the high level, the buffer 45 is disabled. The input node of the buffer 45 is connected to the common output node of the switches T9 and T10.

The data selector 422 includes switches T11 and T12 and a buffer 55.

The input node of the switch T11 is connected to the common output node pre_fdo <0> of the switches T3 and T4, and the input node of the switch T12 is the common output node pre_fdo <of the switches T7 and T8. 1>). The switches T11 and T12 are turned on / off by the control signal sosb1_f. That is, when the control signal (soseb1_f) is at the high level, the switch T12 is turned on and the switch T11 is turned off. When the control signal (soseb1_f) is at the low level, the switch T11 is turned on, and the switch ( T12) is turned off. The output nodes of the switches T11 and T12 are connected in common.

The buffer 55 has the function of an inverter that inverts the logic level of the signal being applied. As shown, whether the buffer 55 is operated by the enable signal pout is determined. That is, when the enable signal pout is at the low level, the buffer 55 is enabled. When the enable signal pout is at the low level, the buffer 55 is disabled. The input node of the buffer 55 is connected to the common output node of the switches T11 and T12.

The shifter 431 is composed of a buffer 61 and a latch 62.

The operation of the buffer 61 is controlled by the internal clock signal clk. Here, the internal clock signal clk is a signal synchronized with an external clock signal applied to the memory device. When the internal clock signal clk is at a high level, the buffer 61 is disabled. When the internal clock signal clk is at a low level, the buffer 61 is enabled.

A signal pout for determining whether the buffers 45 and 55 are enabled is used as an input signal of the buffer 61. The output signal of the buffer 61 is stored in the latch 62. The latch 62 inverts and holds the level of the output signal of the buffer 61.

The shifter 431 outputs the signal pout by a half clock delay. Accordingly, the output signal control of the latch 62 is a signal obtained by half-clock delaying the signal pout. Here, half clock means 1 / 2tCK, and tCK means a cycle of a clock signal used in the synchronous memory device.

The shifter 432 is composed of a latch 63 and a buffer 64.

The input node of the latch 63 is connected to the output node prefdo of the buffer 55. The latch 63 inverts and holds the logic level of the signal applied through the output node prefdo.

The buffer is a circuit having the function of an inverter. The operation of the buffer 64 is controlled by the output signal control of the latch 62. When the signal is at high level, the buffer 64 is disabled. When the signal is at the low level, the buffer 64 is enabled. The input node of the buffer 64 is connected with the output node of the latch 63.

Similar to the shifter 431, the shifter 432 also outputs the data applied through the node prefdo to the node fdo by a half clock delay.

The operation of the pipe latch shown in FIGS. 4b and 4c is the same as in FIG. 3.

For example, when the starting column address is "0" and the sequential mode, the data applied to the pipe latch is output in the order of q0, q1, q2, and 3. The time difference between the output data is half clock. That is, q0 is output through the node rdo, q1 is output through the node fdo, q2 is output through the node rdo, and q3 is output through the node fdo. In addition, when the starting column address is "3" and is in the interleaved mode, the data applied to the pipe latch is output in the order of q3, q2, q1, q0. The time difference between the output data is half clock. That is, q3 is output through the node rdo, q2 is output through the node fdo, q1 is output through the node rdo, and q0 is output through the node fdo. That is, the operation of the circuits of FIGS. 4B and 4C proceeds in the same manner as the case shown in FIG. As a result, the operation itself is the same as in the case of Figs.

Hereinafter, how the pipe latch of the present invention differs from the pipe latch described in FIG. 3 will be described in detail.

In the prior art shown in FIG. 3, two signals (rpout, fpout) are used for each pipe latch to control the operation of the last output buffer. On the other hand, in the case of the present invention shown in Figs. 4b and 4c, the operation of the buffers 45 and 55 is controlled using one signal pout. Thus, in the case of four pipe latches, the present invention can reduce four signal lines compared to the prior art in controlling the operation of the buffer. For reference, since the circuit of FIG. 1 is connected to one data pin, when the number of data pins is N, it can be seen that 4 × N signal lines can be reduced.

Next, in the prior art, the signal rpout and the signal fpout are enabled at 1 / 2tCK intervals to control the data output order. That is, it is enabled in the order of rpout-> fpout-> rpout-> fpout. However, in the present invention, the data is output to the node rdo by the signal pout, and then the half-clock shifter 431 is used to output the data through the node fdo after 1 / 2tCK. The signal pout is delayed half a clock. The signal pout is delayed by half a clock to generate a control, and then the control is used as an enable signal of another half clock shifter 432. In the case of the present invention, the signal (soseb1_f) occurs half a clock ahead of the signal (soseb1_r). As a result, the data output through the node fdo is output by a half clock delay than the data output through the node rdo. Therefore, the order of the data output through the nodes rdo and fdo is the same as in the case of FIG.

For reference, in the present invention, the half-clock shifters 431 and 432 are additionally arranged for each pipe latch, but the increase in the area occupied by these shifters is very small compared to the decrease in area due to the reduction of the control signal line.

The pipe latch of the present invention described so far is applicable to the circuit of FIG. As mentioned in the prior art, the circuit of Figure 1 corresponds to one data pin. Therefore, the data sequentially output in the circuit of the present invention is sequentially input to a data output buffer (not shown) and output to the outside through the data pin. For reference, the data output buffer is a circuit for receiving the output signal of the pre-driver described in FIG.

In the case of using the pipe latch of the present invention, the layout area can be reduced by reducing the signal line applied to the pipe latch.

Claims (4)

A data output circuit of a synchronous memory device having a plurality of pipe latches having an N bit prefetch function, Each of the pipe latches A data switching unit which receives N bit data and switches an output path of the N bit data according to a starting column address and a data output mode applied during a read command; A first data selection unit which receives half of data of the N bits of data output from the data switching unit, and sequentially outputs the half data in response to a first control signal; Receives half of the data except for the half of the data applied to the first data selector among the N bits of data output from the data switching unit, and sequentially processes the remaining half of the data in response to the first control signal. A second data selection unit for outputting A first shifter configured to output a second control signal delayed by a first time after receiving the first control signal; A second shifter for outputting the data received from the second data selection unit after receiving the data output from the second data selection unit, delaying the first time, and outputting the data received from the second data selection unit in response to the second control signal; , The first time corresponds to half (1/2 tCK) of the clock signal period tCK applied to the synchronous memory device. And a time point at which data is first output from the second data selector is 1 / 2tCK faster than a time point at which data is first output from the first data selector. The method of claim 1, The first data selector includes a first switch turned on / off by a third control signal and a first buffer configured to be enabled or disabled by the first control signal. The second data selector includes a second switch turned on / off by a fourth control signal and a second buffer configured to be enabled or disabled by the first control signal. The first and second switching unit receives the data output from the data switching unit, Data passing through the first switching unit is applied to the first buffer, Data passing through the second switching unit is applied to the second buffer, The output of the first buffer is an output of the first data selector, And the output of the second buffer is an output of the second data selector. The method of claim 2, And a pre-driver configured to receive data sequentially output through the first data selector and data sequentially output through the second shifter. And the data output from the first data selector and the data output from the second shifter are alternately applied to the pre-driver. The method of claim 3, wherein And each of the plurality of pipe latches share the pre-driver.

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