KR100605867B1 - Bus arbitration method and bus arbitration having a dynamic priority order arbitration function - Google Patents

Abstract

end. FIELD OF THE INVENTION The present invention relates to a bus arbitrator.

I. The technical problem to be solved by the present invention is to provide a bus arbiter and a method for eliminating the starvation that can occur to low priority functional blocks in a system employing a fixed priority arbitration method. have.

All. Summary of the Invention A bus arbiter in which multiple bus masters arbitrate to share one bus, the active transaction signal being counted at each bus usage arbitration, and the counted value is a preset arbitration wait count maximum count value. In case of abnormality, the dynamic priority adjusting unit generates an active remediation request signal, and activates the transaction signal at every bus use arbitration, and approves the bus use according to the designated priority when the bus use request signal is input from the masters. And an arbitration unit for approving the use of the bus to the bus master in the arbitration waiting state regardless of the priority upon inputting an active redial arbitration request signal, and an arbitration control unit for enabling the arbitration unit when the bus use request signal is input. It is characterized by.

la. Important uses of the invention: Multiple bus masters can be used in a controller that shares a bus.

Bus, arbiter

Description

BUS ARBITRATION METHOD AND BUS ARBITRATION HAVING A DYNAMIC PRIORITY ORDER ARBITRATION FUNCTION             

1 is a block diagram of a bus arbiter according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating N bus master adjustment circuits constituting the dynamic priority adjusting unit 300 of FIG. 1.

FIG. 3 is a detailed configuration diagram of one bus master adjustment circuit 330 shown in FIG. 2.

4 is an arbitration flowchart of a bus arbiter according to an embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a bus arbiter, in particular, a bus intermediary with a dynamic priority adjustment function for acknowledging priority importance and at the same time eliminating starvation that may occur in low priority devices. It's about how.

A system integrated with a single chip, such as a microcontroller, is composed of several functional blocks, and such a system generally has a structure in which data buses are shared in order to reduce chip size. In addition, systems such as microcontrollers generally include an arbiter that performs an arbitration role so that each integrated functional block can share a data bus. For bus masters sharing a bus, the bus occupancy can be divided into high and low bus shares according to their importance.The fixed priority arbitration method is used for arbitration between bus masters having different importance. This is applied a lot.

However, in the above-described fixed priority arbitration method, high priority masters have a high probability of bus occupancy, while low priority bus masters have low bus occupancy or, in the worst case, never occupy the bus. Situations may arise.

Accordingly, an object of the present invention is to recognize the priority of higher priority functional blocks and to occupy the bus resources to lower priority functional blocks in a system in which multiple functional blocks must share a single bus resource. To provide a bus arbitrator and a bus arbitration method.

It is still another object of the present invention to provide a bus arbiter and a method for eliminating starvation that may occur in functional blocks having low priority in a system employing a fixed priority arbitration method. .

The present invention for achieving the above object is a bus arbiter for arranging a plurality of bus masters to share a bus,

A dynamic priority adjustment unit for counting an active transaction signal at each bus use arbitration and generating an active remediation request signal if the counted value is greater than or equal to a preset maximum number of arbitration wait times;

The transaction signal is activated at every bus use arbitration, and the bus is approved according to the priority specified when the bus use request signal is input from the masters, and the arbitration wait expires regardless of the priority when the active remediation request signal is input. An arbitration unit that authorizes the bus master to be in use;

And an arbitration control unit for enabling the arbitration unit when the bus use request signal is input.

Hereinafter, an operation according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description, an embodiment of the present invention will be described by defining the number of bus masters as N.

FIG. 1 illustrates a block diagram of a bus arbiter according to an exemplary embodiment of the present invention, and FIG. 2 illustrates a configuration of N bus master adjusting circuits constituting the dynamic priority adjusting unit 300 of FIG. 1. 3 shows a detailed configuration diagram of one bus master adjustment circuit 330 shown in FIG. 4 illustrates an arbitration flowchart of a bus arbiter according to an embodiment of the present invention.

First, referring to FIG. 1, the arbitration controller 100 controls the arbitration start of the arbitration unit 200 in response to receiving the response signal SL_Res and the bus use request signal of the bus slaves. That is, the arbitration control unit 100 outputs an enable signal en when the response signal and the bus use request signal REQ are active, so that the arbitration operation is started. The arbitration unit 200 approves the use of the bus according to the priority specified when the bus use request signal REQ [n-1: 0] is input, and the priority when the remediation request signal reMap [n-1: 0] is active. Approve bus use in priority order. That is, the arbitration unit 200 outputs the bus use acknowledgment signal ACK [n-1: 0] according to the fixed priority arbitration result when the bus request signals REQ [n-1: 0] input from the bus masters are duplicated. When the active remediation request signal reMap [n-1: 0] is input from the dynamic priority adjusting unit 300, the bus master is granted to the bus master in the arbitration waiting period in preference to the fixed priority arbitration result. . The arbitration unit 200 outputs an active transaction signal TRAN every arbitration. The "intermediate wait expired state" is a state in which the corresponding bus master waits for the bus to the maximum count value which is set in the maximum count register 400 to be described later. When the count value is greater than or equal to the count value set in the maximum count register 400, the bus is approved regardless of priority.

The maximum count register 400 is assigned to each bus master and stores the maximum count value to be in standby after each master requests bus usage. This maximum count value may initially have a hard wire fixed value and may be programmed by a primary CPU with an external interface.

을 입력받는다. 또한 각각의 마스터 조정회로(310∼330)는 상기 중재부(200)로부터 버스사용 승인신호

와 트랜잭션(TRANsaction)신호 TRAN을 입력받는다. 이러한 마스터 조정회로 각각은 도 3에 도시한 바와 같이 앤드게이트(336)와, 카운터(332) 및 비교기(334)로 구성된다.The dynamic priority adjusting unit 300 outputs an active remediation request signal reMap (N) when the mediation count count value is equal to or greater than the maximum count value MAX_C set in the corresponding maximum count register 400, respectively. An adjusting circuit is provided. The master adjustment circuit is equal to the bus masters as shown in FIG.

Receive the input. In addition, each master control circuit (310 to 330) is a bus use approval signal from the arbitration unit (200)

And TRANsaction signal TRAN is received. Each of these master adjustment circuits includes an AND gate 336, a counter 332, and a comparator 334 as shown in FIG.

Hereinafter, referring to FIG. 3, which shows the detailed configuration of the master 0 adjustment circuit 330, a process of generating an active remediation request signal reMap0 will be described.

과 동일하거나 그 이상이면 비교 기(334)로부터는 액티브상태의 재중재요구신호 reMap0가 출력되고, 이러한 재중재요구신호 reMap0는 중재부(200)로 입력되어 미리 지정된 우선순위에 상관없이 중재대기만료상태인 버스 마스터에게 버스사용권을 부여하는데 이용된다.First, if there is no bus request from master 0, the counter 332 remains clear. If the bus usage request signal REQ0 is present (" high " state) and the bus usage approval signal ACK0 is non-active, then the AND gate 336 is used whenever the arbitration unit 200 mediates, i.e., the transaction signal TRAN. Each time it is activated, the counter 332 is up counted by one. That is, the counter 332 counts the number of arbitrations of the arbitration unit 200. As such, the value counting the number of arbitrations of the arbitration unit 200 is the maximum count value MAX_ loaded from the maximum count register 400.

Is equal to or greater than the comparator 334, the remediation request signal reMap0 in the active state is output, and the remediation request signal reMap0 is input to the arbitration unit 200 to terminate the arbitration wait regardless of the predetermined priority. It is used to grant a bus license to the bus master in status.

Hereinafter, a process of generating a bus use approval signal according to the fixed priority arbitration result of the arbitration unit 200 and a process of generating a bus use approval signal according to the remediation request signal will be described in detail with reference to FIGS. 1 to 4. Let's do it.

In the following description, it is assumed that a bus slave interprets an address and a control command output from a master authorized to use a bus, performs an operation accordingly, and outputs a response signal SL_Res in an active state at completion.

Under this assumption, when the system starts, all masters and slaves are initialized to reset, and the arbitration unit 200 waits for the input of the bus use request signal REQ from the master in step 500. When the bus use request signal REQ is input from an arbitrary master, the arbitration unit 200 performs arbitration in step 510. If the bus use request signal REQ is input from one master, the arbitration unit 200 activates only the bus use acknowledgment signal ACK assigned to the requested bus master. If several bus masters request the use of a bus, the arbitration unit 200 searches for the highest priority master among the active request signals and outputs an active bus use acknowledgment signal ACK only to the corresponding master.

과 동일하면, 마스터 0 조정회로(330)는 액티브상태의 재중재요구신호 reMap0를 발생시킨다. 이에 중재부(200)는 동적 우선순위 조정부(300)로부터 액티브상태의 재중재요구신호 reMap0을 입력받고 그에 응답하여 지정된 우선순위에 상관없이 마스터 0이 버스를 사용할 수 있도록 버스사용 승인신호 ACK0를 액티브시킨다. 따라서 버스 마스터 0은 다른 버스 마스터들에 비해 우선순위가 낮더라도 버스 사용권한을 부여받을 수 있게 되는 것이다.The above is a general arbitration method when the bus masters do not require frequent bus requests. The following describes the arbitration function of N (0, ..., N-1) bus masters. Assume that bus master N-1 and bus master N-2 continue to request the bus. And the priority of the masters is the highest master N-1, then N-1,…. The following describes the dynamic priority arbitration method assuming that master 0 has the lowest priority. First, when master 0 requests the use of a bus, master 0 coordination circuit 330 starts to count the transaction signal TRAN input from arbitration unit 200. If during the counting of the transaction signal TRAN, the median count value is loaded from the maximum count register 400 without receiving the active bus use acknowledgment signal ACK0, MAX_

If equal to, the master 0 adjustment circuit 330 generates an active remediation request signal reMap0. In response, the arbitration unit 200 receives the active remediation request signal reMap0 from the dynamic priority adjusting unit 300 and activates the bus use acknowledgment signal ACK0 so that the master 0 can use the bus regardless of the designated priority. Let's do it. Therefore, bus master 0 can be given bus permission even if the priority is lower than other bus masters.

As described above, the present invention adjusts the value of the maximum count register assigned to each bus master, so that even if the master has a low priority, bus usage rights can be granted after waiting for arbitration as many as the number of registers loaded in the register. This has the advantage of bringing fairness to arbitration.

Claims (6)

In a bus arbiter that arbitrates multiple bus masters to share a bus, A dynamic priority adjustment unit for counting an active transaction signal at each bus use arbitration and generating an active remediation request signal if the counted value is greater than or equal to a preset maximum number of arbitration wait times; The transaction signal is activated at every bus use arbitration, and the bus is authorized according to the priority specified when the bus use request signal is input from the masters, and the arbitration wait expires regardless of the priority when the active remediation request signal is input. An arbitration unit that authorizes the bus master to be in use; And an arbitration control unit for enabling the arbitration unit when the bus use request signal is input. The method of claim 1, wherein the dynamic priority adjustment unit; A counter for counting the active transaction signal after inputting a bus use request signal from a corresponding bus master among the bus masters; N (0, ..., N-1) master control circuits, each of which is configured as a comparator for generating an active remediation request signal when the output value of the counter is greater than or equal to a preset maximum number of arbitration wait times. Bus arbiter. 3. The bus arbiter of claim 2, wherein the plurality of master control circuits are equal in number to the bus masters and receive a bus use request signal from one bus master. In a bus arbiter that arbitrates multiple bus masters to share a bus, A dynamic priority adjustment unit for counting an active transaction signal at each bus use arbitration and generating an active remediation request signal if the counted value is greater than the maximum number of arbitration wait times loaded; The transaction signal is activated at every bus use arbitration, and the bus is approved according to the priority specified when the bus use request signal is input from the masters, and the arbitration wait expires regardless of the priority when the active remediation request signal is input. An arbitration unit that authorizes the bus master to be in use; A maximum count register configured to load and store a median wait count maximum count value of each bus master; And an arbitration control unit for enabling the arbitration unit whenever the bus use request signal is input. The method of claim 4, wherein the dynamic priority adjustment unit; A counter for counting the active transaction signal after inputting a bus use request signal from a corresponding bus master among the bus masters; N (0, ..., N-1) master control circuits, each of which is configured as a comparator for generating an active remediation request signal when the output value of the counter is greater than or equal to a preset maximum number of arbitration wait times. Bus arbiter. In a method of arbitrating multiple bus masters to share a bus, A first step of checking whether a bus use request signal is input from each of the bus masters; A second process of approving the use of the bus according to a predetermined priority when there is an input of a bus use request signal; Counting the active transaction signal at each bus use arbitration, and if the counted value is more than the preset maximum number of arbitration wait times, the bus master that preferentially accepts the bus use regardless of the predetermined priority is used. Bus arbitration method characterized by consisting of three steps.

Images