KR100605162B1 - PCI interface apparatus for driving window driver - Google Patents

Abstract

The present invention relates to a PCI interface device for driving a Windows driver, comprising: a PCI bus and an interface device mounted on the PCI bus and capable of high speed data communication; A logic cell device connected to the PCI bus, a PCI bridge for controlling and interfacing a 32-bit PCI bus between the logic cell device and the PCI bus, and a memory for executing a configuration program for the logic cell device; The logic cell device includes an A / D converter for converting a control signal and an external analog signal generated from the logic cell device into a digital signal to input an analog signal of 8 channels with a sampling rate of 100 kHz, and the control signal and data generated from the logic cell device. D / A converter that converts signals into analog signals and outputs 8 channels of analog signals at 10μsec high-speed sampling, digital input / output section capable of 24 bits of simultaneous input / output, and 16-bit counting timer with 3 channels Design the logic of the counter; Directly generate digital input / output signals and timer / counter signals, generate A / D and D / A control signals to control the A / D converter and D / A converter to overcome the shortcomings of the ISA bus of PC Data acquisition board that runs on one PCI bus enables high-speed data transmission and reception.

Windows, Driver, PCI, Interface

Description

PC interface device for driving window driver

1 is an overall system block diagram of a PCI interface device for driving a window driver according to an embodiment of the present invention;

2 is a PCI bridge circuit diagram of the present invention;

3 is an FPGA circuit diagram of the present invention;

4 is a block diagram illustrating an FPGA internal block of the present invention;

5 is an A / D converter circuit diagram of the present invention;

6 is a circuit diagram of a D / A converter of the present invention;

7 is a view showing an external connector (Pin connectors) of the present invention,

FIG. 8 is a waveform diagram of a digital output signal pin, which is pin 10 of FIG. 3, measured with an oscilloscope;

9A and 9B are waveform diagrams of an analog signal output from the DAOUT1 pin of FIG. 6 measured with an oscilloscope.

10A to 10C are diagrams outputting an interfaced signal to a monitor when an analog signal is given to ADIN1 of FIG. 5;

11A and 11B are waveform diagrams of a counter value output from OUT0, pin 137 of FIG. 3, measured with an oscilloscope;

Explanation of symbols on the main parts of the drawings

10: logic cell device 20: PCI bridge

30: memory 40: PCI bus

11: A / D Converter 13: D / A Converter

15: digital input / output 17: timer / counter

The present invention relates to a PCI interface device for driving a Windows driver, and more particularly, to a PCI interface device for driving a Windows driver to interface to a Peripheral Component Interconnection (PCI) bus using a simple conversion logic.

One of the challenges of the "Windows Driver Driven PCI Interface Card" is the implementation of a data acquisition board based on the PC that is in high demand.

Conventionally, the data acquisition board adopts the ISA (Industry Standard Architecture) method, so it can be used only in the Windows 95 and Windows 98 versions with low operating systems, and has a limitation in that the data processing speed is 8 MHz. It had disadvantages that were unsuitable for the multimedia system PC.

In addition, since the ISA bus method is no longer supported on a PC main board, most PC-based interface cards have recently been replaced by a PCI (Parallel Component Interface) bus type.

At present, most of the industrial field devices are controlled by a programmable logic controller (PLC). However, in order to build a Graphic User Interface (GUI), which is required by workers, a graphic monitor function must be added to the PLC, which requires a lot of investment in development cost. Recently, a PC-based controller is used in building such a GUI environment. In the Windows environment of the PC, beautiful graphics can be realized, and the fast processing speed of the PC enables calculation processing that was previously impossible to realize.

Accordingly, an object of the present invention is to provide a PCI driver for driving a Windows driver that transmits and receives data at high speed by implementing a data acquisition board operating on a PCI bus that overcomes the shortcomings of the ISA bus of a PC.

In other words, it provides a PCI interface device (card) that runs in a Windows environment.

(1) Development of PCI Bus based Multi-Function Data Acquisition Board

Built-in digital input / output signal, digital / analog converter, analog / digital converter, and hardware interrupt device.

(2) Effects of replacing ISA bus-based control devices with PCI buses

The ISA bus is not gradually adopted in PCs, and the maximum speed of existing ISA bus-based data acquisition cards is limited to 8 MHz and 16 bits. In contrast, PCI has a 32-bit data rate of 33MHz.

(3) Windows device driver (Vxd, WDM) development

In the Windows GUI environment, the event occurrence time of the application program is maximum 10㎳ unless configured as a device driver, so it cannot show a quick response to an external signal. Designed as device drivers, the data acquisition board responds quickly to responses with up to 2ms of event processing time.

(4) Realize user-friendly environment by designing interface environment as GUI environment

The biggest advantage of PC-based cards is that you can easily design GUI environment. A GUI environment is realized so that system users can easily acquire data.

According to an aspect of the present invention, there is provided a PCI driver for driving a Windows interface according to the present invention, which includes: a PCI bus and an interface device mounted on the PCI bus and capable of high speed data communication; A logic cell device connected to the PCI bus, a PCI bridge for controlling and interfacing a 32-bit PCI bus between the logic cell device and the PCI bus, and a memory for executing a configuration program for the logic cell device; The logic cell device includes an A / D converter for converting a control signal and an external analog signal generated from the logic cell device into a digital signal to input an analog signal of 8 channels with a sampling rate of 100 kHz, and the control signal and data generated from the logic cell device. D / A converter that converts signals into analog signals and outputs 8 channels of analog signals at 10μsec high-speed sampling, digital input / output section capable of 24 bits of simultaneous input / output, and 16-bit counting timer with 3 channels Design the logic of the counter; A digital input / output signal and a timer / counter signal are generated directly, and A / D and D / A control signals are generated to control the A / D converter and the D / A converter.

The logic cell device is a high speed FPGA, and the memory is 514 Kbytes of SRAM.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall system block diagram of a PCI interface device for driving a window driver according to an embodiment of the present invention, Figure 2 is a PCI bridge circuit diagram of the present invention, Figure 3 is an FPGA circuit diagram of the present invention.

As shown in FIG. 1, the PCI interface device for driving a window driver of the present invention is a data acquisition board mounted on a PCI bus of a PC and capable of data communication at high speed, and includes a logic cell device 10. And a PCI bridge 20 and a programmable memory 30.

The logic cell device 10 is a high-speed Field Programmable Gate Array (FPGA) device, which internally includes a digital input / output 15 and a timer / counter 17 module, and an analog / digital converter 11; An analog-to-digital converter (ADC) and a digital-to-analog converter 13 (DAC), directly generating digital input / output signals and timer / counter signals, and generating control signals of D / A and A / D to convert the A / D converter 11; ADC) and D / A converter 13 (DAC).

The PCI bridge 20 is a chipset (PCI 9050: PLX) that efficiently interfaces with the logic cell device 10 and the PCI bus (40; 32 bits) on the PC board to enable data input and output. With plug and play, the maximum throughput is 33MHz.

The memory 30 is an SRAM used to execute a configuration program for the PCI bridge 20. A total capacity of 514 Kbytes is available, and data bits of the configuration program designed as the PCI bridge 20 are automatically supplied when power is supplied. It is sent serially.

The PCI bus 40 is a passage for inputting and outputting data in a PCI manner on a PC board.

The interface between the logic cell device 10 and the PCI bus 40 is an address / data bus (AD) and PCI bus 40 control signal commonly used for the transfer of address and data through the PCI bridge 20. Made by them.

The CLK signal is input to all devices on the PCI bus 40 as a clock to provide timing for data transfer.

RST is a reset signal. When this signal is generated, all PCI signals are in a high impedance state.

The FRAME signal controls the start and end of bus transmission and reception. C / BE is a bus command and byte enable signal and determines the type of data transmission and reception.

The IDSEL signal acts as the initial device selection signal, and the DEVSEL signal acts as the current device selection signal. The IRDY and TRDY signals are signals indicating the ready state of the master and the slave, and the PAR signal is a signal indicating the parity check state.

FIG. 4 is a block diagram of an FPGA according to the present invention. Referring to FIG. 4, it is understood that three timer / counter outputs and 24 digital inputs / outputs are located in the right signal group by the control signal group on the left side. Can be.

5 is an A / D converter circuit diagram of the present invention. Referring to FIG. 5, the A / D converter 11 has a conversion maximum sampling time for an analog input of 100 s and an input specification of 10 volts of positive / negative voltage. The resolution (the ability to convert analog data values to minimal digital values) is a 16-bit AD7805, which converts the control and external analog signals generated by the logic cell device 10 into digital signals and an external multiplexer. 8 channels of analog signals can be input.

FIG. 6 is a circuit diagram of a D / A converter of the present invention. Referring to FIG. 6, the D / A converter 13 has two latches, and a high-speed analog output by fast conversion, a resolution of 16 bits, and a positive / negative voltage 10 A DAC712U having a volt output and a 10 kHz sampling time, the control signal and the data signal generated by the logic cell device 10 can be converted into an analog signal to output 8 channels of analog signals through an external multiplexer.

The digital input / output unit 15 is all 24 (24bit) simultaneous input and output, the voltage is a digital I / O of 5V TTL level, the timer / counter 17 has three channels 16 bits (2 ¹⁶ - 1 to) the counting available Timer & Counter.

FIG. 7 is a diagram illustrating an external pin connector of the present invention. FIG. 7A is a 30-pin layout view of a connector capable of connecting a 24-bit digital input / output with an external device. FIG. 7B is a D / A diagram. 40 pin layout of the connector for connecting the output of the converter 13, the A / D converter 11, the timer / counter 17 to the outside, and FIG. 7C shows the signals of FIGS. 7A and 7B at the same time. A 50-pin D-sub pin layout is shown.

In addition, analog and digital triggering, compact size (Compact size, half-size PCB), power supply (core: 2.5 volts, input / output: 5 volts, analog voltage: 12 volts), installation operating system (OS: Windows 98) , 2000, ME, XP), and operating applications (Visual Basic, Visual C).

Hereinafter, operation effects of the PCI driver for driving a Windows driver configured as described above will be described.

First, the logic cell device 10 reads an input / output read (RD) and an input / output write (RD) in response to the PCI bus 40 enable signal of one of control signals provided from the PCI bus 40 through the PCI bridge 20. WR), a memory read signal, and a memory write signal are generated to operate by receiving an address or data signal provided through the address / data bus AD of the PCI bus 40.

The PCI interface card has the functions of measuring digital input and analog input from outside, transmitting to external interrupt signal PC, internal timer, counter operation, etc., and analog input has 16-bit resolution of bipolar 10 volt with 100 샘플링 sampling. Have The analog output outputs a bipolar 10 volt voltage at 16 bits of resolution for 10ms high-speed sampling. The analog input and output channels consist of eight channels using an analog multiplex. The 24 lines of digital inputs and outputs are compatible with TTL series ICs. Three built-in 16-bit timers / counters can be used by dividing their clock 2.45MHz. The clock frequency can be arbitrarily changed by the user. By providing 514K bytes of RAM in the board, it can be used as FIFO memory to increase the processing speed when executing a large amount of applications. There are two types of connectors for connecting external devices: 50-pin SCSI connectors and 30- and 40-pin flat cable connectors (supplied). When only one of the two connectors is connected, both input and output signals are available.

FIG. 8 is a waveform diagram of a digital output signal pin, which is pin 10 of FIG. 3, measured by an oscilloscope.

Referring to FIG. 8, the output of two waveforms among 24 signal waveforms and a digital input / output signal is shown. The waveform of channel 1 is port PA0 with digital value "1", and channel 2 is port PA1 with digital value "0". Channel 1 shows 5 [V] and channel 2 shows 0 [V].

9A and 9B are waveform diagrams measuring an analog signal output from the DAOUT1 pin of FIG. 6 with an oscilloscope.

9A and 9B, the D / A converter 13 shows the waveform of the result of the conversion. Specifically, FIG. 9A is an analog value outputted when the 7FFFH, the largest value of the digital value, is given to the program. ] Is displayed. 9B is an output waveform when 4000H is given to the program to obtain analog output 5 [V].

10A to 10C are diagrams outputting an interfaced signal to a monitor when an analog signal is applied to ADIN1 of FIG. 5.

Referring to FIGS. 10A to 10C, an analog signal having an externally given voltage is illustrated in a program through an A / D converter. Specifically, FIG. 10A shows a 7FFFH value without error when an external 10 [V] voltage is applied. Shows. FIG. 10B shows a case where a voltage of about 5 [V] is applied, and FIG. 10C shows a value when 0 [V] is input. The reason why the voltage is 0 [V] but the value of 30H seems to be the reason that the noise and compensation cable are not used.

11A and 11B are waveform diagrams of a counter value output from OUT0, which is the 137 pin of FIG. 3, measured with an oscilloscope.

Referring to Figs. 11A and 11B, the result waveforms for the timer 17 in the board are shown. Timer 0 counters the waveform of approximately 2.4 MHz occurring in the board and outputs the signal. Timer 2 counters. Channel 1 of FIG. 11A represents the output of timer 0 and channel 2 represents the output of timer 2. FIG. As shown in the photograph, waveforms of FIG. 11A are divided into two and FIG. 11B are divided into four according to a user's input.

As described above, according to the PCI interface device for driving a window driver according to the present invention, a PLC network by transmitting and receiving data at high speed by implementing a data acquisition board operating on a PCI bus that overcomes the disadvantages of the ISA bus of a PC It is proposed to solve the problems caused by the implementation of the GUI environment of the device and will be extended to the GUI environment PLC system after being connected with the network module.

What has been described above is just one embodiment for implementing the PCI interface device for driving a Windows driver according to the present invention, the present invention is not limited to the above-described embodiment, it is usually within the technical spirit of the present invention Of course, various modifications are possible by those who have the knowledge of.

Claims (3)

A PCI bus and an interface device mounted on the PCI bus and capable of high speed data communication; A logic cell device connected to the PCI bus, A PCI bridge that controls and interfaces a 32-bit PCI bus between the logic cell device and the PCI bus; A memory for executing a configuration program for the logic cell device; The logic cell device includes an A / D converter for converting a control signal and an external analog signal generated from the logic cell device into a digital signal to input an analog signal of 8 channels with a sampling rate of 100 kHz, and the control signal and data generated from the logic cell device. D / A converter that converts signals into analog signals and outputs 8 channels of analog signals at 10μsec high-speed sampling, digital input / output section capable of 24 bits of simultaneous input / output, and 16-bit counting timer with 3 channels With a counter; A PCI interface for driving a Windows driver, which generates a digital input / output signal and a timer / counter signal, and generates control signals of A / D and D / A to control the A / D converter and the D / A converter. Device. The method of claim 1, And said logic cell device is a high speed FPGA. The method of claim 1, And the memory is a 514 Kbyte SRAM.

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