KR100599654B1 - Plasma display device and driving method thereof - Google Patents

Abstract

The present invention relates to a plasma display device for controlling address power consumption and a driving method thereof. According to the present invention, the current applied to the address electrode is measured and summed, the APC level corresponding to the summed address current is determined, and the corresponding data gain value is multiplied by the data of the image signal. That is, by measuring the address current to determine the address power consumption and thereby limit the address power consumption, it is possible to more accurately limit the address power consumption. In addition, when the summed address current exceeds a predetermined threshold, the protection operation of the address driver is performed, thereby protecting the address buffer and the like from the surge current.

APC, protection operation, address, power consumption

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a diagram showing image data at full white.

FIG. 2 is a switching waveform diagram of FIG. 1.

3 is a diagram illustrating dot pattern image data.

4 is a switching waveform diagram of FIG. 3.

5 is a diagram illustrating an electrode arrangement diagram of a plasma display device according to an exemplary embodiment of the present invention.

6 is a schematic plan view of a plasma display device according to a first embodiment of the present invention.

7 is a schematic block diagram of a controller of a plasma display device for reducing address power consumption according to a first embodiment of the present invention.

8 is a diagram illustrating an internal configuration of an address APC unit according to an exemplary embodiment.

9 is a diagram illustrating a gain value according to the address APC level of FIG. 8.

10 is a block diagram illustrating an internal configuration of an address APC unit according to an embodiment of the present invention.

11 is a schematic plan view of a plasma display device according to a second embodiment of the present invention.

12 is a schematic block diagram of a controller of a plasma display device according to a second embodiment of the present invention.

13 is a block diagram showing an internal configuration of an address APC unit of a control unit according to the second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a driving method thereof, and more particularly, to a plasma display device for controlling address power consumption and a driving method thereof.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display have been actively developed. Among these flat panel display devices, the plasma display device has advantages of higher luminance and luminous efficiency and a wider viewing angle than other flat panel display devices. Therefore, the plasma display panel is in the spotlight as a display device to replace a conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

In the DC plasma display device, the electrode is exposed without the discharge space insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, in the AC plasma display device, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

In general, the driving method of the AC plasma display device includes a reset period, an address period, and a sustain period.

The reset period is a period for initializing the state of each cell in order to smoothly perform an addressing operation on the cell. The address period is an address voltage for a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. It is a period of time to perform the operation of accumulating wall charge by applying a. The sustain period is a period in which a discharge for actually displaying an image in the addressed cells by applying a sustain discharge pulse is performed.

Here, when each operation of each subfield is performed in the above manner, the discharge space between the scan electrode and the sustain electrode, the surface on which the address electrode is formed and the surface on which the scan and sustain electrode are formed act as a capacitive load. There is capacitance in the panel. Therefore, in order to apply the waveform for addressing, a lot of reactive power for charge injection that generates a predetermined voltage in capacitance other than power for address discharge is required. At this time, when the number of switching of the address electrodes is large, address power is consumed even more.

As described above, the address power is generated more due to the number of switching of the address electrode, which will be described in detail below.

1 is a diagram showing image data at full white.

Referring to FIG. 1, when full white, all data is 1, there is little data fluctuation of the address electrode, there is little pulse switching, and power consumption increases in proportion to the number of switching, so there is little charge / discharge reactive power. The driving waveform at this time is as shown in FIG. As shown in FIG. 2, in full white, only one switching is required for one column indicated by a thick solid line in FIG. 2.

By the way, the dot pattern image data is as follows.

3 is a diagram illustrating dot pattern image data.

Referring to FIG. 3, since data continuously changes from 1 to 0 and 0 to 1, a lot of switching occurs, and a driving waveform at this time is shown in FIG. 4.

As shown in FIG. 4, in the dot pattern, data variation of the address electrode is large, and pulse switching of the driving waveform occurs frequently, thereby increasing power consumption. In addition, not only the dot pattern image data but also the line image data in which the image pattern fluctuates for each line, the data fluctuates for each line, so the number of switching increases and the address power consumption increases.

As in the above process, as the difference between the pixels (cells) of all the lines and the pixels (cells) of the current line in the address data increases, switching occurs more frequently, which increases power consumption.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the related art, and to provide a plasma display device and a driving method thereof for controlling address power consumption.

A driving method of a plasma display device according to a feature of the present invention for achieving the above object is

In the method of driving a plasma display device comprising a plurality of first and second electrodes formed side by side, and a plurality of third electrodes formed in a direction crossing the first and second electrodes,

(a) measuring a current applied to the third electrode; (b) summing the measured currents in predetermined units; (c) correcting image signal data corresponding to the summed currents; And (d) generating address data corresponding to the corrected image signal data and applying the same to the third electrode. In addition, the driving method of the plasma display apparatus further includes performing an operation of protecting a driving circuit for driving the third electrode when the summed current exceeds a predetermined threshold. Here, the data gain is inversely proportional to the sum of the currents.

Plasma display device according to another aspect of the present invention

A plasma panel including a plurality of first and second electrodes and a plurality of third electrodes crossing the first and second electrodes; An address current detector configured to measure a current applied to the third electrode; Compensating the image signal data according to the sum of the measured currents and the sum of the currents, and generating a control signal for generating the address data corresponding to the corrected image signal data so that the address data is applied to the third electrode. Control unit; And an address driver which drives the third electrode according to a control signal of the controller. The controller may include: an address automatic power controller including a current adder configured to add the measured currents in a predetermined unit, and a gain determiner configured to output a data gain value corresponding to the added currents; And generating the corrected data by multiplying the data gain value by the image signal data, generating address data corresponding to the corrected data, and transmitting an address driving control signal to the address driver so that the address data is applied to the third electrode. And an address data generating unit for transmitting. The address automatic power control unit may further include a protection operation determination unit configured to generate and output a protection operation flag to protect the address driver when the summed current exceeds a predetermined threshold value, wherein the address data generation unit is configured to output the protection operation flag. When the protection operation flag is received, control is performed to block application of address data to the third electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Now, a plasma display device and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating an electrode arrangement diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 5, the electrodes of the plasma display device are arranged in a matrix of m × n. Specifically, the address electrodes A1-Am are arranged in the column direction and n rows of the scan electrodes in the row direction. Y1-Yn and sustain electrodes X1-Xn are arranged in a zigzag. In FIG. 5, a portion where the scan electrode, the sustain electrode, and the address electrode intersect forms one discharge cell 12.

6 is a schematic plan view of a plasma display device according to a first embodiment of the present invention.

As shown in FIG. 6, the plasma display device according to the first embodiment of the present invention includes a plasma panel 100, an address driver 200, a scan / hold driver 300, and a controller 400.

The plasma panel 100 includes a plurality of address electrodes A1-Am arranged in the column direction, and a plurality of scan electrodes Y1-Yn and sustain electrodes X1-Xn arranged in a zigzag pattern in the row direction. . The address driver 200 receives an address drive control signal from the controller 400 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A1-Am. The scan / hold driver 300 receives a control signal from the controller 400 and alternately inputs a sustain voltage to the scan electrodes Y1-Yn and the sustain electrodes X1-Xn to perform sustain discharge for the selected discharge cell. .

The control unit 400 receives R, G, B image signals and a synchronization signal from the outside, divides one frame into several subfields, and divides each subfield into a reset period, an address period, and a sustain discharge period (sustain period). Drive the plasma display panel. At this time, the controller 400 adjusts the number of sustain pulses in each sustain period of the subfield in one frame and supplies the necessary control signals to the address driver 200 and the scan sustain driver 300. Herein, the control unit 400 according to the first embodiment of the present invention determines the input image pattern to reduce the address power consumption and converts the image data to reduce the address power consumption.

Hereinafter, the controller 400 of the plasma display device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 7 to 10.

7 is a schematic block diagram of a controller of a plasma display device for reducing address power consumption according to a first embodiment of the present invention.

As shown in FIG. 7, the control unit 400 of the plasma display device according to the first embodiment of the present invention includes an inverse gamma correction unit 410, an error diffusion unit 420, an APC unit 430, and a sustain number generation unit. 440, the holding and scanning drive control section 450, the address APC section 460 and the address data generating section 470.

The inverse gamma correction unit 410 maps n-bit R, G, and B image input data, which is currently input image data, to an inverse gamma curve and corrects the m-bit (m≥n) image signal. In a typical plasma display panel, n is 8 and m is 10 or 12.

In this case, the image signal input to the inverse gamma correction unit 410 is a digital signal. When an analog image signal is input to the plasma display panel, the analog image signal may be converted into a digital image signal by an analog-to-digital converter (not shown). There is a need. The inverse gamma correction unit 410 may be a logic circuit for generating a lookup table (not shown) or data corresponding to an inverse gamma curve that stores data corresponding to an inverse gamma curve for mapping an image signal. (Not shown).

The error diffusion unit 420 is inversely gamma corrected by the inverse gamma correction unit 410 and error-diffuses the lower m-n bit image of the extended bit m image to surrounding pixels. Error diffusion is a method of displaying an image of a lower bit by separating an image of a lower bit to be diffused into adjacent pixels and a detailed description thereof is described in Korean Patent Laid-Open Publication No. 2002-0014766.

The APC unit (Automatic Power Control) 430 detects the load rate using the image data output from the error diffusion unit 420, calculates the APC level according to the detected load rate, and calculates the calculated APC level. The corresponding sustain pulse number and the like are calculated and output.

The sustain number generator 440 allocates the number of sustain pulses of each subfield by using the sustain pulse number information transmitted from the APC unit 330.

The sustain / scan drive control unit 450 generates a control signal corresponding to the number of sustain (sustain) discharge pulses output from the sustain number generator 440 and outputs the control signal to the sustain / scan driver 300. In this case, although the sustain number generator 460 and the sustain and scan drive controller 480 have been described separately, the two may be simultaneously implemented in one block.

The address APC unit 460 (that is, the address automatic power control unit) determines whether the data of one frame is data that consumes a lot of address power consumption from the output data of the inverse gamma correction unit 410, and thus the address power consumption is increased. In the case of a lot of consumption, that is, in the case of the dot pattern as shown in FIG. 3, in order to control the power consumption, turn on or off both the data gain value and the address data value of the lowest subfield to reset the address data. A control signal (address APC flag) is outputted to the address data generation unit 470. At this time, the address APC unit 460 even determines whether the data of one frame consumes a lot of address power or data (refers to the difference between the gray level of the previous cell and the gray level of adjacent cells in the column direction in the address electrodes of the same column). Can be determined based on whether or not each subfield data is on / off (the difference between the subfield data of the previous cell and the subfield data of the adjacent cell in the column direction at the address electrodes of the same column). Find out.

8 is a diagram illustrating an internal configuration of the address APC unit 460 according to an embodiment.

As shown in FIG. 8, the address APC unit 460 according to an exemplary embodiment of the present invention includes a line memory unit 461, an adder 462, a gain storage unit 463, a gain determination unit 464, and The mode determination unit 465 is included.

Even the sum of the address APC unit 460 adder 462 obtains even the system by comparing the gray level value of the previous line stored in the line memory unit 461 with the gray level value of the currently input line in the same column direction. Add up. That is, the sum of even the system of each line in one frame is obtained by the following equation (1).

Here, P denotes a gray scale value of a pixel, i denotes a line, j denotes a column, and Equation 1 denotes even a system of pixels between each line of image data having N lines and M columns. Represents the sum. Equation 1 may be modified in various ways, may be modified to calculate in a line unit, or may be modified to obtain a sum of all at once.

 Even the sum adding unit 462 obtains the sum of the even system between the lines in the same manner as in Equation 1 above, and outputs the sum to the gain determining unit 464.

Then, the gain determination unit 464 determines an automatic power control (APC) level corresponding to the sum S of the system, and refers to the end gain corresponding to the APC level by referring to the lookup table of the gain storage unit 463. Determine and output At this time, a value corresponding to the APC level is shown in FIG. 9, but this is not exemplary and it is apparent to those skilled in the art that the value may be changed.

Here, the gain value is inversely proportional to the sum of the gradation differences (Sum), and is between 0 and 1. A large sum of the difference means a large difference in data (gradation) between pixels, which increases power consumption, so the data difference between pixels should be reduced by multiplying the gain value.

If the sum Sum of the differences is zero, the gain value is 1, and as the sum Sum of the differences increases, the gain value becomes smaller. This gain value can be set through experimentation and stored in the form of lookup table. Such a gain value may be changed in a range that does not deform the original video signal as needed, and may be designed to be one or more.

On the other hand, the mode determining unit 465 uses the sum of the values of the lines between the lines obtained by the adder 462 to equalize the data values of the least significant bits of the address data. It is determined whether to output the address APC flag signal. In this case, the LSB data value refers to the data value of the subfield having the lowest weight value when the input video signal is converted into the address data. That is, when the sum of gray level differences between the lines is greater than or equal to the threshold value, it is determined that the address power consumption is consumed a lot, and the address APC flag signal is output. It is determined that the address APC flag signal is not output. At this time, the threshold value stores the sum value even in the case where a large amount of address power consumption is generated based on experimental data. Here, even the value between the lines is determined to be equal to or greater than the threshold value, so that the mode determining unit 465 makes the LSB data value of the address data the same (on or off at the same time). In the case of outputting the LB bit, the data value of the LSB bit is equally set at the rear end. Therefore, when the LSB bit is displayed on the plasma panel, the switching is reduced, thereby reducing the power consumption.

The address data generator 470 outputs correction data by multiplying the image signal by the data gain value output from the address APC unit 460, generates subfield data corresponding to the correction data, and displays the subfield data in a plasma display. By rearranging the address data to drive the panel, an address control signal for controlling the address driver 200 is generated and output to the address driver 200.

At this time, when the address APC flag signal is input from the mode determining unit 465 of the address data generating unit 460, the corrected data is recalibrated so that the LSB bits are the same (that is, the same is turned on or off). After generating the subfield data or generating the data corrected by the product of the gain values as the subfield data, the data of the lowest subfield corresponding to the LSB bit is the same (that is, the same on or off). do.

Thus, address power consumption can be further reduced by multiplying the gain value and simultaneously controlling the address power consumption by simultaneously turning on / off the LSB bit.

In this case, in general, even a lot of line-based systems consume a lot of power, so as in the embodiment of the present invention, the address APC unit 460 consumes a lot of address power by even the lines of lines. Although it is determined whether or not it is recognized, the address power consumption is not an accurate determination since it is directly related to address data, that is, subfield data. Therefore, a method of determining whether the address power consumption is large or small through the subfield data will be described below.

10 is a block diagram showing an internal configuration of the address APC unit 460 according to an embodiment of the present invention.

As shown in FIG. 10, the address APC unit 460 includes a line memory unit 461, a subfield data difference adder 466, a gain storage unit 463, and a gain determination unit 464. And a mode determination unit 465. Here, the address APC unit 460 according to the embodiment of the present invention includes the subfield data difference adder 466 instead of the adder 462 even in the embodiment of FIG. 8. Since it is substantially the same as the first embodiment, description of overlapping portions will be omitted below.

The subfield data difference adding unit 466 uses the signal converted into on / off data for each subfield, that is, the vertical lines adjacent to each other in the column direction using the data converted into subfield data (that is, the row line). The difference between the subfield data). At this time, it is preferable that a data processing unit (not shown in Fig. 10) is located at the front end of the subfield data difference adding unit 466. That is, the data processor converts the input video signal into on / off data for each subfield. In order to express 256 gray scales in a plasma display panel, one frame is divided into eight subfields (1SF to 8SF) having a weight of 1, 2, 4, 8, 16, 32, 64, and 128, respectively. Assuming that the data processing unit converts an image signal of gradation 100 into 8-bit data of "00100110", for example. In the "00100110", the numbers '0' and '1' correspond to eight subfields 1SF to 8SF in order, and '0' indicates that the discharge cells (dots) do not discharge (off) in the corresponding subfields. '1' indicates that the discharge cell discharges (on) in the corresponding subfield.

The subfield data difference adding unit 466 sums the difference between subfield data values of adjacent up and down lines (meaning a row line) from the video signal converted into on / off data for each subfield in the day processing unit, and adds up each of the summed values. The values for the subfields are summed over all the subfields in one frame. The change in the switching state that generates a large amount of address power consumption occurs when one of the two discharge cells adjacent to each other in the column direction (vertical direction in FIG. 3) is on and the other discharge cell is off, so the subfield data difference is summed. The unit 466 may calculate a sum of the difference between the on / off data of two discharge cells adjacent in the column direction as a subfield, as shown in Equation (2).

Here, R _ij , G _ij , and B _ij are on / off data of R (red), G (green), and B (blue) discharge cells of i rows and j columns, respectively. At this time, the subfield data difference adding unit 466 obtains the value of each subfield by using Equation 2, and adds the values of each subfield to all subfields forming one frame. In this case, Equation 2 represents the sum of the subfield data differences for each subfield. As shown in Equation 2, the sum of the subfield data differences for each subfield may be used to determine whether the address power consumption is large or small. The sum of the values obtained as shown in Equation 2 for the subfield may determine whether the address consumption power is large or small.

In general, since the image signals are serially inputted in a row order, a line memory 461 is included as shown in FIG. 10 to store one row of image signals in order to calculate a difference between on / off data of two adjacent discharge cells. When on / off data for each subfield of a row (line) video signal is input through the line memory unit 461, the subfield data difference adder 466 stores the data sequentially. The difference of on / off data is calculated for each subfield in two adjacent discharge cells by reading the data of the previous row (line) stored in. In addition, the address power consumption determiner 420 may calculate a difference between on / off data for each subfield in two discharge cells by using an exclusive OR (XOR) operation of the on / off data.

The gain determination unit 464 then determines an automatic power control (APC) level (step) corresponding to the sum of the on / off differences between the lines of the mode subfield (or each subfield) of one frame, and the APC level. The corresponding end gain is determined by referring to the lookup table of the gain storage unit 463 and output.

If the value determined by the subfield data difference adding unit 466 is greater than or equal to the threshold value, the mode determining unit 465 generates an address APC flag signal and outputs the address APC flag signal. It is determined that the address power consumption is low, and no address APC flag signal is generated. At this time, the threshold value is obtained by storing the value corresponding to the sum of the subfield data difference between the lines in the case where a lot of address power consumption occurs based on experimental data. At this time, as described above, as shown in Equation 2, the mode determining unit 465 may determine whether the address APC flag signal is generated through the sum of the on / off difference of the subfield data for each subfield.

The address data generator 470 outputs correction data by multiplying the image signal by the data gain value output from the address APC unit 460, generates subfield data corresponding to the correction data, and displays the subfield data in a plasma display. By rearranging the address data to drive the panel, an address control signal for controlling the address driver 200 is generated and output to the address driver 200. At this time, when the address APC flag signal is input from the mode determining unit 465 of the address data generating unit 460, the corrected data is recalibrated so that the LSB bits are the same (that is, the same is turned on or off). When the field data is generated or the correction data is generated as the subfield data, the data of the subfield having the lowest weight corresponding to the LSB bit is the same (that is, the same is turned on or off).

In this case, the address APC unit 460 may include a data processing unit (not shown in FIG. 10) for converting the input image signal into subfield data by itself. Using the generated subfield data, the sum of subfield data differences may be obtained as shown in Equation 2.

Here, although the address APC unit 460 according to the exemplary embodiment of the present invention shown in FIGS. 8 and 10 is shown in a different block from the address data generating unit 460, it may be included in the same block and implemented as one. Self-explanatory by

At this time, in the exemplary embodiment of the present invention, the value of the input image signal data is changed using the gain determiner 464, but the LSB bits are the same using only the mode determiner 465 except for the gain determiner 464. Control to reduce power consumption.

In addition, although the address APC unit 460 determines whether power consumption is large or small as described above, the output signal of the error diffusion unit 420 may be determined using the output data of the inverse gamma correction unit 410. It can be used to determine the magnitude of power consumption.

In addition, when the mode determining unit 465 determines that the power consumption is high as in the exemplary embodiment of the present invention, the address data generator 470 uses only the LSB bit (ie, the lowest weighted subfield data). As described above, the lower few bits can be made the same so as not to affect the gradation.

Meanwhile, although the power consumption of the display image that sharply increases the power consumption through the plasma display device according to the first embodiment of the present invention described above may be limited to a certain level, the surge output from the address driver 200 may be limited. Due to this current, the address buffer included in the address driver 200 may be damaged. That is, since the plasma display device according to the first embodiment of the present invention determines whether the address power consumption is large or small based on an indirectly input pattern, it does not measure the actual address power consumption. It does not solve the problem of address power rise due to a defect. Hereinafter, a method of solving such a problem will be described with reference to FIGS. 11 to 13.

11 is a schematic plan view of a plasma display device according to a second embodiment of the present invention. As shown in FIG. 11, in the plasma display device according to the second embodiment of the present invention, an address current detector 500 is added unlike the first embodiment, and thus the function of the controller 400 ′ is somewhat different. The description will be omitted.

The address current detector 500 detects a current (hereinafter referred to as an address current) output from the address driver 200 to the address electrodes A1-Am and transmits the same to the controller 400 ′. The address driver 200 includes data drivers (not shown) for applying an address data voltage. Currents outputted from the data drivers (not shown) to the address electrodes A1-Am are converted into address currents. The detection unit 500 detects. In this case, a specific method of measuring the current using the address current detector 500 can be easily understood by those skilled in the art, and thus the detailed description thereof will be omitted. Meanwhile, although the address current detector 500 is illustrated separately from the address driver 200 in FIG. 12, the address current detector 500 may be included in the address driver 200.

The controller 400 ′ adds up the address current transmitted from the address current detector 500 in subfield units or in a predetermined number (M) subfield units, in one frame unit or in a predetermined number (N) frames, The control signal is generated so that the image signal data is multiplied by a gain according to the summed address current, and a control signal is generated so that the corrected image signal data (which is changed to data that can reduce address power consumption by multiplying the data gain) is applied to the address electrode. To print. On the other hand, when the value of the summed current exceeds a predetermined threshold, it controls so as not to apply an address voltage (address data) in order to protect the driving circuit (ie, address buffer) in the address driver 200.

Hereinafter, the controller 400 ′ correcting the image signal data according to the summed address current and performing the protection circuit operation will be described in more detail with reference to FIGS. 12 and 13.

FIG. 12 is a schematic block diagram of a controller 400 'of a plasma display device according to a second embodiment of the present invention, and FIG. 13 is an address APC portion of the controller 400' according to the second embodiment of the present invention. 460 'is a block diagram showing the internal configuration.

As shown in FIG. 12, the control unit 400 ′ according to the second embodiment of the present invention is identical to the first embodiment of the present invention shown in FIG. 7 except for the address APC unit 460 ′. Is omitted. The address APC unit 460 ′ receives the amount of address current received from the address current detector 500, adds the address currents, and resets the address data to the address data generator 470 according to the summed current. Outputs In addition, the address APC unit 460 'outputs a protection operation flag to the address data generator 470 when the sum of the current values exceeds a predetermined threshold.

Referring to FIG. 13, the address APC unit 460 ′ of the controller 400 ′ according to the second embodiment of the present invention includes a current summing unit 462 ′, a gain storage unit 463 ′, and a gain determination unit 464. ') And a protection operation determination unit 465'.

The current summing unit 462 'sums up the address currents transmitted from the address current detector 500 in subfield units or in a predetermined number (M) subfield units, in one frame unit, or in a predetermined number (N) frame units. The added address current is transmitted to the gain determining unit 464 'and the protection operation determining unit 465'.

The gain determiner 464 'determines an automatic power control (APC) level corresponding to the summed address current transmitted from the current adder 462', and gain-stores a data gain value corresponding to the APC level. The lookup table of the section 463 'is determined and output to the address data generator 470. The APC level has a higher step as the summed address current is larger. Here, only the end gain corresponding to each APC level is stored in the gain storage unit 463 ', but the start gain (not shown) and the holding time (not shown) are also shown in FIG. It is stored together. Therefore, the gain determining unit 464 'outputs a start gain according to each APC level, maintains the start gain for the sustain period, and outputs the end gain at a predetermined interval and then maintains it again. Repeat. Here, as in the first embodiment, the data gain has a lower value as the APC level is higher, so the data gain is inversely proportional to the summed address current.

On the other hand, the protection operation determining unit 465 'determines whether the summed address current transmitted from the current adding unit 462' exceeds a predetermined threshold, and if the protection operation flag is determined to exceed the predetermined threshold, the protection operation flag is addressed. Output to the data generating unit 200. Here, the predetermined threshold is a current that can destroy an address buffer (not shown) included in the address driver 200, and a surge current corresponds to the predetermined threshold. Is set.

Here, the address data generator 470 outputs correction data by multiplying the data gain value output from the address APC unit 460 'by the image signal data, generates subfield data corresponding to the correction data, and generates a subfield. The data is rearranged into address data for driving the plasma display panel to generate an address control signal for controlling the address driver 200, and output the address control signal to the address driver 200.

In addition, when the address operation generator 470 receives the protection operation flag from the address APC unit 460 ', the address data generator 470 generates an address control signal so as not to apply address data to protect the address driver 200, thereby generating an address driver ( 200). That is, when the protection data flag is received, the address data generation unit 200 generates an address control signal for not applying the address data, and outputs the address control signal to the address driver 200. The address driver 200 outputs the address control signal. By not applying address data to the address electrodes A1-Am, the address buffer in the address driver 200 is protected.

Here, as another method of performing the protection operation of the address driver 200, the protection operation flag output from the address APC unit 460 ′ is transmitted to a power supply (not shown), and the address driver 200 is supplied from the power supply. It is possible to avoid supplying the address voltage to the.

As described above, in the plasma display device according to the second exemplary embodiment of the present invention, the address power consumption is determined by measuring the address current, thereby limiting the address power consumption, thereby more accurately limiting the address power consumption. In addition, the address buffer in the address driver can be protected by measuring the address current and cutting off the surge current.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the presence or absence of address power consumption is determined by using the difference between the line-based systems or the line-by-line subfield data values, and the data of the subfield having the minimum weight according to the determined power consumption. By controlling to be the same, address power consumption can be improved in a double manner.

In addition, by measuring the address current to determine the address power consumption through the address power consumption through it, it is possible to more accurately limit the address power consumption. In addition, by performing the protection operation of the address driver by measuring the address current, the address buffer and the like can be protected from the surge current.

Claims (9)

In the method for driving a plasma display device comprising a plurality of first and second electrodes, a plurality of third electrodes formed in a direction crossing the first and second electrodes, (a) measuring a current applied to the third electrode; (b) summing the measured currents in predetermined units; (c) correcting image signal data corresponding to the summed currents; (d) generating address data corresponding to the corrected image signal data and applying the same to the third electrode; And and (e) blocking the application of address data to the third electrode to protect the driving circuit when the summed current exceeds a predetermined threshold value. delete delete The method of claim 1, Step (c) is, Outputting a data gain corresponding to the sum of the currents; And And correcting the image signal data by multiplying the image signal by the data gain.  The method of claim 4, wherein And the data gain is inversely proportional to the summed currents. A plasma panel including a plurality of first and second electrodes and a plurality of third electrodes crossing the first and second electrodes; An address current detector configured to measure a current applied to the third electrode; Compensating the image signal data according to the sum of the measured currents and the sum of the currents, and generating a control signal for generating the address data corresponding to the corrected image signal data so that the address data is applied to the third electrode. Control unit; And An address driver configured to drive the third electrode according to a control signal of the controller, And the control unit controls to block application of address data to the third electrode when the sum current exceeds a predetermined threshold.  The method of claim 6, The control unit, An address automatic power controller including a current adder configured to add the measured currents in a predetermined unit, and a gain determiner configured to output a data gain value corresponding to the summed currents; And The data gain value is multiplied by the image signal data to generate corrected data, and address data corresponding to the corrected data is generated to transmit an address driving control signal to the address driver so that the address data is applied to the third electrode. A plasma display device comprising an address data generator. delete The method of claim 7, wherein And the data gain value is inversely proportional to the sum of the currents.

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