KR100582724B1 - display device for applying flat panel display device and organic electroluminescence display device for applying thereof and method for fabricating display device - Google Patents

Abstract

According to the present invention, when a display device for controlling an image to be displayed on a flat panel display device is manufactured by a semiconductor process, a pattern mask required is shortened to shorten a manufacturing process of the display device and display characteristics of the display device are improved. The present invention relates to a display element for a flat panel display device and a method of manufacturing the same. According to the present invention, an LDD structure or an offset structure in which a flat panel display element used in a liquid crystal display device or an organic electroluminescent device improves electrical characteristics. It is possible to reduce the number of pattern masks required to manufacture the same while having a to reduce the process required for manufacturing.

Flat Panel Display, Ion Stopper Layer, Gate, Organic Electroluminescence

Description

Display device for applying flat panel display device and organic electroluminescence display device for applying application and method for fabricating display device}

1 is a cross-sectional view of a display element for a conventional flat panel display device.

2 is an equivalent circuit of a display element for a flat panel display device according to the present invention.

3 is a perspective view illustrating that a buffer layer and a semiconductor layer are formed on a substrate.

4 is a cross-sectional view of FIG.

FIG. 5 is a perspective view illustrating an ion stopper layer and an anode electrode formed on a substrate; FIG.

6 is a cross-sectional view of FIG.

7 is a cross-sectional view showing that a high concentration ion doped region is formed by high concentration ion implantation.

8 is a cross-sectional view showing that a gate thin film for forming a gate is formed.

9 is a cross-sectional view showing a gate formed by patterning a gate thin film.

10 to 11 are cross-sectional views illustrating that an anode electrode protective photoresist is formed by white exposure.

12 is a cross-sectional view showing a low concentration ion doped region formed by low concentration ion implantation.

FIG. 13 is a cross-sectional view illustrating a gate line and a first electrode formed by patterning a gate thin film; FIG.

14 is a cross-sectional view illustrating that a contact hole is formed after forming a source / drain insulating film.

15 is a perspective view illustrating a source / drain electrode in a contact hole;

16 is a cross-sectional view of FIG. 15.

17 or 18 are cross-sectional views illustrating that the planarization film and the anode electrode are exposed.

19 to 23 is a process chart showing another embodiment of the present invention.

24 to 26 is a process diagram showing another embodiment according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of displays, and more particularly, when fabricating a display device for controlling an image to be displayed in a flat panel display by a semiconductor process, a gate electrode may be formed of a double structure of a transparent electrode and a gate metal. The present invention relates to a display device for a flat panel display device and a method of manufacturing the same, which reduce the required pattern mask by implementing an LDD region or an offset region to shorten the manufacturing process of the display device and further improve display characteristics of the display device.

The present invention also relates to an organic electroluminescent device fabricated using a display element for a flat panel display device with a reduced pattern mask and improved display device characteristics.

In general, the display device may be defined as a kind of interface device existing between the user and the information processing device so that the user may recognize the processing result generated by the information processing device processing the data input by the user.

Such display devices are the first developed and commonly used CRT-type ray tube type display devices, liquid crystal display devices (LCDs), and organic electroluminescence display devices. It may be classified into a flat panel display device such as a flat panel display device.

Such a flat panel display device has advantages of low volume, light weight, high brightness and high resolution as compared to a CRT display device. The flat display device has been developed as a display device of a portable display device and a small information processing device as well as a general office information processing device. And prevalence is increasing rapidly.

In such a flat panel display device, a part of a substrate having a predetermined area is a small area (for example, a unit area obtained by uniformly dividing the entire area of the substrate by 600 × 400 × 3 when the resolution is 600 × 400). In a state partitioned by a thin film transistor, thin film transistors (hereinafter referred to as TFTs) and signal lines, which are display elements, are output to each partitioned display area by a TFT substrate and a thin film transistor formed in a matrix manner by a semiconductor manufacturing process. And an image display means for controlling the output signal to display an image.

In this case, in the case of the liquid crystal display device, the tilt angle of the liquid crystal is conceptually controlled by the output signal output from the thin film transistor of the TFT substrate, thereby controlling the fine light amount of the light as well as blocking / supplying the light. The light stimulates the color filter so that the desired image is displayed.

In the case of an organic electroluminescent display device, an organic light emitting material which emits self-emission according to an output signal output from a thin film transistor expresses a predetermined color, and the density of the expressed color is determined by an output signal output from the thin film transistor. To be displayed.

Through this, in the case of the liquid crystal display device and the organic electroluminescent display device, it can be seen that the manufacturing of the thin film transistor is essential for image control. Recently, many developments have been made to simplify the manufacturing process and improve the performance of the thin film transistor for flat panel display devices. It is becoming.

1, a conventional conventional structure of a thin film transistor used in such a flat panel display is shown.

First, an amorphous silicon layer previously formed through a first pattern mask in a state in which amorphous silicon or polysilicon is formed to a predetermined thickness on one surface of the substrate 1 having a predetermined area or The polysilicon layer is patterned into a predetermined shape to form a "semiconductor layer" or "channel layer". This is hereinafter referred to as semiconductor layer 3.

Subsequently, a gate insulating film 5 having a very high electrical resistance is deposited on the entire surface of the semiconductor layer 3 to a predetermined thickness, and a conductive gate thin film having a very low electrical resistance is deposited on the upper surface of the gate insulating film 5. Is patterned so that only a portion of the gate thin film corresponding to the top surface of the semiconductor layer 3 remains in a predetermined area through a second pattern mask, thereby forming a gate 9.

At this time, a gate signal line (not shown) to be connected to the gate 9 is formed together in the process of forming the gate 9.

At this time, the source region 3b is formed on the right side of the semiconductor layer 3 shown in FIG. 1, and the drain region 3a is formed on the left side of the gate 9.

Subsequently, a source / drain insulating film 7 having a very high electrical resistance over the entire area is formed on the upper surface of the gate 9 again, and thereafter, the gate insulating film 5 and the source / drain are formed through the third pattern mask. Contact holes are formed so that a portion of the source region 3b and the drain region 3a of the semiconductor layer 3 wrapped by the insulating film 7 is opened to the outside.

Thereafter, the source / drain electrodes 11 having a predetermined shape are formed in the open source region 3b and the drain region 3a by a conductive material having a low electrical resistance. In the process of forming, a fourth pattern mask is used.

Thereafter, a contact is made to the drain electrode by the fifth pattern mask so that the drain electrode covered by the insulating film 13 is exposed on the upper surface of the source / drain electrode 11 again while the insulating film 13 is deposited to a predetermined thickness over the entire surface. The hole 13a is formed again.

Thereafter, a conductive electrode 15 having a predetermined shape is formed on the drain electrode by the sixth pattern mask.

In this case, the conductive electrode 15 becomes a pixel electrode facing the common electrode in the case of the liquid crystal display, and in the case of the organic electroluminescent device, the conductive electrode functions as an anode electrode on which an organic material layer and a cathode electrode are to be formed.

In the organic electroluminescent device among them, the seventh pattern mask is used unlike the liquid crystal display device because after the conductive electrode is formed, a planarization film is formed over the entire surface, and only the conductive electrode portion of the planarization film must be opened to the outside.

As described above, in order to manufacture a thin film transistor for a flat panel display device, six or seven pattern masks must be generally used.

In recent years, a portion of the semiconductor layer 3 has a lightly doped drain (LDD) structure having a high concentration doping, a low concentration doping region, or an off-free doping region without a leakage current from the gate 9 of the semiconductor layer 3. OFFSET structures have been developed and used.

Recently, at least two or more pattern masks are additionally used to improve display performance with such LDD structures and off-set structures. Thus, eight or nine pattern masks are typically used in the manufacturing process for manufacturing thin film transistors. The number of processes increases.

In addition, when a thin film transistor for a flat panel display device having such a structure is implemented in an organic electroluminescent device, light generated in an organic light emitting layer (not shown) may be formed of a plurality of thin films already formed under the conductive electrode, for example, the conductive electrode 15. ) And the insulating film 13, the source / drain insulating film 7, the gate insulating film 5, and the substrate 1 to insulate the source / drain electrode 11.

On the other hand, when a thin film transistor for a flat panel display device having such a structure is implemented in a liquid crystal display device, light generated from a backlight assembly (not shown) disposed under the substrate 1 may be exposed to the substrate 1-the gate insulating film 5-. After passing through the source-drain insulating film 7-insulating film 13 and the conductive electrode 15, the display is performed while passing through the liquid crystal (not shown).

However, in the case of the thin film transistor having such a structure, in both the liquid crystal display device or the organic electroluminescent display device, since light passes through different media, the light transmission efficiency is extremely reduced in this process, resulting in a decrease in luminance. Another problem arises in that display degradation occurs.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to significantly shorten the manufacturing process of the thin film transistor used in the flat panel display device and to improve the performance of the thin film transistor.                         

Other objects of the present invention will become more apparent from the following detailed description of the invention.

The display device for a flat panel display according to the present invention for realizing the object of the present invention includes a pixel region formed in the intersection region of the first and second signal lines arranged in a matrix form, and the first and second signal lines; At least one thin film transistor and a pixel electrode to apply a specified output signal to the pixel region, is formed to have a first area at a predetermined position of the substrate, the first doped region is formed in a band shape along the edge, A semiconductor layer in which a second doped region is formed in a band shape inside the doped region, a first insulating film covering the semiconductor layer, and a top surface of the first insulating film corresponding to the semiconductor layer, and formed at a position corresponding to the inside of the second doped region. A gate electrode formed on the ion stopper layer, a pixel electrode formed on the first insulating film spaced apart from the ion stopper layer by a predetermined distance, and an upper surface of the ion stopper layer One side is connected to one of the first signal line connected to the gate, one of the first doped regions of the semiconductor layer, and the other end thereof is connected to the source electrode connected to the second signal line, and the other side of the first doped region of the semiconductor layer. And the other side includes a drain electrode connected to the pixel electrode.

In addition, a method of manufacturing a thin film transistor for a flat panel display device according to an embodiment of the present invention includes a pixel region and a pixel formed in an intersection region of first and second signal lines arranged in a matrix form and first and second signal lines. At least one thin film transistor and a pixel electrode are applied to apply a specified output signal to the region, and a semiconductor material is formed by coating a semiconductor material on a predetermined region of the substrate, and then patterning the semiconductor thin film using a first pattern mask to form a predetermined shape. Forming a semiconductor layer having an area of 1, forming a first insulating film on the upper surface of the semiconductor layer, and then forming a conductive transparent thin film on the upper surface of the first insulating film through the second pattern mask. An ion stopper ray patterned to have a second area smaller than the first area on the upper surface of the first insulating film corresponding to the upper portion of the semiconductor layer. Forming a pixel electrode at a predetermined distance from the ion stopper layer, and doping ions having a first concentration in a portion not covered by the ion stopper layer to form first doped regions on both sides of the semiconductor layer, A gate and a first signal line connected to the gate are formed on the upper surface of the ion stopper except for the pixel electrode with a third pattern mask as a conductive gate thin film over the entire surface of the substrate to have a third area smaller than the second area. And removing the portion of the ion stopper layer that is not covered by the gate while preventing the pixel electrode from being patterned, and then doping ions having a second concentration to the portion that is not covered by the gate to form the inside of the first doped region. After forming the second insulating film over the entire surface of the substrate in the state where the second doped region is formed, the fourth paddle Forming a contact hole to expose the first doped region by using a mask, a source electrode connected to the second signal line in the first doped region via a fifth pattern mask while a conductive thin film is formed on the upper surface of the substrate; Forming a drain electrode connected to the pixel electrode.

In addition, a method of manufacturing a display device for a flat panel display device according to an embodiment of the present invention includes a pixel area and a pixel formed at an intersection area between first and second signal lines arranged in a matrix form and first and second signal lines. A method of manufacturing a display device of a flat panel display device including at least one thin film transistor and a pixel electrode to apply a specified output signal to a region, comprising: applying a semiconductor material to a predetermined region of a substrate to form a semiconductor thin film, and then Forming a semiconductor layer having a first area by patterning the substrate into a predetermined shape by using a pattern mask; forming a first insulating film on the upper surface of the semiconductor layer, and then forming a conductive transparent thin film on the upper surface of the first insulating film Patterning the conductive transparent thin film through the second pattern mask in the first upper surface of the first insulating film corresponding to the upper portion of the semiconductor layer Forming the pixel electrode at a predetermined distance away from the ion stopper layer and the ion stopper layer formed to have a second area smaller than the area, and doping ions having a first concentration to a portion not covered by the ion stopper layer. The second thin film of the pixel electrode protection gate thin film and the ion stopper formed on the top surface of the pixel electrode through the third pattern mask while the first doped region is formed on both sides of the semiconductor layer and the conductive gate thin film is formed over the entire surface of the substrate. Forming a gate having a third area smaller than the area and a first signal line connected to the gate; and removing a portion of the ion stopper layer that is not covered by the gate, and then removing the portion of the ion stopper layer that is not covered by the gate. Doping with ions to form a second doped region inside the first doped region Forming a contact hole to expose the first doped region using a fourth pattern mask after forming the second insulating film over the entire surface of the substrate in a state; and forming a conductive thin film on the upper surface of the substrate. Forming a source electrode connected to the second signal line and a drain electrode connected to the pixel electrode in the first doped region, applying a planarization film over the entire surface of the substrate, and then applying a sixth pattern mask to the top surface of the pixel electrode. Patterning and removing the planarization film corresponding to the pixel electrode protection gate thin film covering the pixel electrode.

In addition, in the method of manufacturing a display device of a flat panel display device according to the present invention, a pixel region and a pixel region are formed in the intersection region of the first and second signal lines arranged in a matrix form and the first and second signal lines. A method of manufacturing a display device of a flat panel display device including at least one thin film transistor and a pixel electrode to apply an output signal specified by the method, the method comprising: applying a semiconductor material to a predetermined region of a substrate to form a semiconductor thin film, and then Forming a semiconductor layer having a first area by patterning the substrate into a predetermined shape using a pattern mask; and forming a first insulating film on the upper surface of the semiconductor layer, and then forming a conductive transparent thin film on the upper surface of the first insulating film. The conductive transparent thin film is patterned through a second pattern mask to form a first surface on the upper surface of the first insulating film corresponding to the upper portion of the semiconductor layer. Forming the pixel electrode at a predetermined distance away from the ion stopper layer and the ion stopper layer formed to have a smaller second area, and doping the ions having the first concentration to a portion not covered by the ion stopper layer to form a semiconductor. The first doped region is formed on both sides of the layer, and the conductive gate thin film is formed over the entire surface of the substrate so that the third pattern mask has a third area smaller than the second area on the upper surface of the ion stopper except the pixel electrode via the third pattern mask. Forming a gate and a first signal line connected to the gate, patterning the photoresist thin film so that only the pixel electrode is covered by the fourth pattern mask while the photoresist thin film is applied over the entire surface of the substrate; Mask the part of the ion stopper layer that is not covered by the gate After the second insulating film is formed over the entire surface of the substrate in a state in which a second doped region is formed inside the first doped region by doping ions having a second concentration to a portion not covered by the gate. Forming a contact hole to expose the first doped region by using a five-pattern mask, and a source connected to the second signal line in the first doped region by the sixth pattern mask while the conductive thin film is formed on the upper surface of the substrate. Forming a drain electrode connected to the electrode and the pixel electrode.

Hereinafter, a display device for a flat panel display device, an organic electroluminescent device using the same, and a method for manufacturing the display device for a flat panel display device according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 shows an equivalent circuit of the display element 700 formed in a matrix form on the flat panel display apparatus.

Specifically, the display element 700 used in the flat panel display device is, as a whole, a first thin film transistor (hereinafter referred to as a first TFT; 100), a second thin film transistor (hereinafter referred to as a second TFT; 200) and a charge. And a combination of the capacitance 300, the gate line 400, the data line 500, and the common power supply line 600.

Hereinafter, a method of manufacturing a display device according to the present invention for use in a flat panel display device will be described with reference to the accompanying drawings. In the present invention, three different embodiments of manufacturing the display device will be described.

<First Embodiment>

3 to 18 illustrate a process sequence of <First Embodiment> for forming an arbitrary display element formed in a flat panel display device having a predetermined resolution. In the first embodiment, six pattern masks are used. A display element for a flat panel display device having an LDD structure or an offset structure for preventing leakage current in the semiconductor layer is described.

The attached reference numeral 710 of FIG. 3 or FIG. 4 is a transparent substrate having a predetermined thickness in one embodiment. A transparent buffer layer 720 having a predetermined thickness is formed on one side of the substrate 710.

In this case, the buffer layer 720 may or may not be formed according to the characteristics of the substrate 710.

According to an exemplary embodiment of the present invention, the buffer layer 720 may be formed. When the buffer layer 720 includes ions that affect the characteristics of the display element 700 to be formed on the substrate 710, they may be formed. It serves as an ion barrier to prevent penetration from the substrate 710 into the display element 700 by diffusion.

However, the buffer layer 720 is not essential when the substrate 710 such as an alkali free material does not have any influence on the display device 700.

As described above, amorphous silicon is formed on the upper surface of the buffer layer 720 that serves as an ion barrier to a predetermined thickness by a semiconductor fabrication facility, and the amorphous silicon has electrical characteristics than amorphous silicon by a laser crystallization process. This excellent polysilicon changes the crystal structure. Hereinafter, this will be defined as a polysilicon thin film.

Thereafter, the polysilicon thin film deposited on the upper surface of the buffer layer 720 is again patterned by the first pattern mask to form two patterns having a predetermined area and spaced apart from each other by a predetermined interval. Hereinafter, the patterned two patterns will be defined as first semiconductor layer 110 and second semiconductor layer 210, respectively.

At this time, the formation positions of the first semiconductor layer 110 and the second semiconductor layer 210 correspond to the positions of the first and second TFTs 100 and 200 in the equivalent circuit of FIG. The shape, size, and formation position of the (110, 210) may be somewhat modified depending on the design, but in the present invention, the first and second semiconductor layers (110, 210) to have a diagonal relationship with each other on the substrate 710 in a preferred embodiment It is formed by patterning.

Subsequently, as illustrated in FIG. 5 or 6, a gate insulating layer 730 having an insulating material having a predetermined thickness on an upper surface of the substrate 710 on which the first and second semiconductor layers 110 and 210 are formed, has a high electrical resistance over its entire surface. Is formed.

Subsequently, an indium tin oxide (ITO) material, which is transparent and a conductive material, is formed on the upper surface of the gate insulating layer 730 to have a predetermined thickness to form an ITO thin film.

Thereafter, the ITO thin film is similar to the first and second semiconductor layers 110 and 210 on the top surface of the gate insulating layer 730 corresponding to the top surfaces of the first and second semiconductor layers 110 and 210 by the second pattern mask. In addition, a portion is patterned to have a somewhat smaller area than the second semiconductor layers 110 and 210.

Meanwhile, the ITO thin film positioned at a distance from the second semiconductor layer 210 is also left to be patterned to have a predetermined area.

Hereinafter, the ITO thin film patterned on the top surface of the gate insulating layer 730 corresponding to the top surfaces of the first and second semiconductor layers 110 and 210 will be defined as an ion stopper layer 120 and 220. An ITO thin film patterned to have a predetermined area spaced apart from the layer 210 by a predetermined distance will be defined as an anode electrode 740.

The ion stopper layers 120 and 220 formed as described above are formed for the purpose of forming LDD structures or offset structures to be formed on the first and second semiconductor layers 110 and 210 without a separate pattern mask, and the anode electrode 740 has light This is to prevent a decrease in luminance due to refraction and reflection occurring while passing through different media.

As described above, the process according to the second pattern mask is a process in contrast with the process of forming a gate thin film using a gate material on the upper surface of the conventional gate insulating film.

Subsequently, as illustrated in FIG. 7, the substrate 710 on which the ion stopper layers 120 and 220 and the anode electrode 740 are formed is transferred to an ion implantation facility, and thus, highly ionized doping according to a high density ion implantation process. high density ion doping) is performed.

The high concentration ion doping is a preliminary process for forming a portion of the LDD structure or the offset structure in the first and second semiconductor layers 110 and 210. In this case, the high concentration ion doping is uniformly spread over the entire surface of the substrate 710.

As a result, impurities are formed in the portions of the first and second semiconductor layers 110 and 210 in which the ion stopper layers 120 and 220 are already formed, and the first and second semiconductor layers 110 and 220 are formed by the ion stopper layers 120 and 220 and the gate insulating layer 730. However, impurities are not covered by the ion stopper layers 120 and 220, but impurities reach the portions of the first and second semiconductor layers 110 and 210 after passing through the gate insulating film 730. Doping is performed.

Hereinafter, a portion of the first and second semiconductor layers 110 and 210 in which high concentration ion doping is performed by an impurity has a rectangular band shape, which will be referred to as a high density ion doping area 112 and 212. .

Subsequently, in order to complete the LDD structure, a low concentration ion doped region (temporarily indicated by a dotted line circle) is formed in a band shape again inside the high concentration ion doped regions 112 and 212 due to impurities in the first and second semiconductor layers 110 and 210. Should be.

To implement this, there may be a method of performing a low concentration ion doping after etching a portion of the ion stopper layers 120 and 220 covering the current low concentration ion doping region by using a separate pattern mask. As an increase occurs, the present invention uses a method of performing low concentration doping in the low concentration ion doped region without using such a method.

To implement this, first, as shown in FIG. 8, the gate thin film 750 having a predetermined thickness is formed of a conductive gate material having a low electrical resistance over the entire surface of the substrate 710.

Subsequently, as shown in FIG. 9, the photoresist thin film is exposed by performing a third pattern mask exposure on the photoresist thin film formed by spin coating a photoresist material on a top surface of the gate thin film 750 using a spin coater or the like. The exposed photoresist thin film is baked and developed again to perform photoresist thin film patterning.

Specifically, as shown in FIG. 9, the patterned photoresist thin film 760 includes a top surface of the gate thin film 750 corresponding to the top surfaces of the ion stopper layers 120 and 220 and a first charge capacitance of the equivalent circuit of FIG. 2. The portion where the electrode 310 is to be formed and the gate line 755 are selectively left.

More specifically, the photoresist thin film 760 left on the gate thin film 750 corresponding to the top surfaces of the ion stopper layers 120 and 220 is left somewhat smaller than the area of the ion stopper layer 120.

Subsequently, the substrate 710 is transferred to a dry or wet etching apparatus, so that the gate thin film 750 which is not protected by the photoresist thin film is etched, and thus all of the gate thin films 750 are etched. 130,230 are formed.

Subsequently, all of the photoresist thin film remaining on the substrate 710 is removed by an ashing process or the like.

At this time, in the ion stopper layers 120 and 220 formed under the gates 130 and 230, portions protruding from the gates 130 and 230 exist, which are removed by etching using the gates 130 and 230 as masks. Low concentration ion doping is possible.

However, when the ion stopper layers 120 and 220 are etched, a problem occurs in that the anode electrode 740 without the protective thin film for the material for etching the indium tin oxide is etched together with a part of the ion stopper layers 120 and 220.

In the present invention, when the ion stopper layers 120 and 220 are etched as described above, the method of allowing the anode electrode 740 to be selectively etched without protecting the gate 130 and 230 is not etched. It is shown through.

In order to implement this, as shown in FIG. 10, a back exposure is performed while a new photoresist thin film 765 is again applied over the entire upper surface of the gates 130 and 230.

In this case, the photoresist thin film 765 uses a negative photoresist that remains when exposed to light.

When the backside exposure is performed using the negative photoresist thin film 765, a portion of the light passes through the substrate 710 and the transparent anode electrode 740, as shown in FIG. 11. The negative photoresist thin film is left on the anode electrode 740 by reaching the negative photoresist thin film 765 disposed on the upper portion, and the negative photoresist thin film located on the first and second semiconductor layers 110 and 210. 765 is not exposed or the amount of exposure is insufficient to remove all in the development process.

After the exposure-development is completed, the substrate 710 is etched to selectively etch only indium tin oxide, and the ion stopper layers 120 and 220 exposed from the gates 130 and 230 are etched using the gates 130 and 230 as masks. do.

Thereafter, as illustrated in FIG. 12, the substrate 710 is transferred to the ion implantation facility, and then low concentration ion doping is performed by the ion implantation facility.

At this time, the lightly doped ions penetrate into the portions of the first and second semiconductor layers 110 and 210 that are not covered by the gates 130 and 230 and the etched ion stopper layers 120 and 220, thereby allowing the first and second semiconductor layers 110 and 210 to be exposed. An LDD structure is formed. In this case, the lightly doped regions of the first and second semiconductor layers 110 and 210 will be referred to as the lightly doped regions 114 and 214.

Subsequently, the negative photoresist thin film 765 is removed through an ashing process to thereby form the substrate 710.

Subsequently, a source / drain insulating layer 770 is formed over the entire surface of the substrate 710 as shown in FIG. 14, and contact holes 772, 774, 776, 778, 779 are formed in the source / drain insulating layer 770 through a fourth pattern mask. do.

More specifically, the positions of the contact holes 772, 774, 776, 778, 779 should be the positions where the heavily doped regions 112, 212 of the first and second semiconductor layers 110, 210 are exposed to the outside, and the anode electrodes covered by the source / drain insulating layer 770 are exposed. It should be a location where 740 is exposed to the outside.

In this case, the source / drain insulating layer 770 positioned on the upper surface of the first electrode 310 of the charging capacitance 300 serves as a dielectric of the charging capacitance 300.

15 to 16, a conductive source / drain thin film 780 is formed on the upper surface of the source / drain insulating layer 770 on which the contact holes 772, 774, 776, 778, 779 are formed, and the source / drain thin film 780 is formed. ), The source electrode 140 of the first TFT 100, the drain electrode 150, the source electrode 240 of the second TFT 200, the drain electrode 250, and the data line of the second pattern mask are formed through a fifth pattern mask. 785, the common electrode 783, and the second electrode 320 of the charging capacitance 300 are all formed as shown in FIG. 16.

More specifically, a portion of the data line 785 is connected to the source electrode 140 of the first TFT 100, and the drain electrode 150 of the first TFT 100 is the first of the charging capacitance 300. The electrode 310 is electrically connected, the source electrode 240 of the second TFT 200 is connected to the common electrode 783, and the drain electrode 250 of the second TFT 200 is the anode electrode 740. Is connected to. In this case, the second electrode 320 of the charging capacitance 300 communicates with the common electrode 783.

Thereafter, as shown in FIG. 17, the planarization thin film 790 is formed over the entire surface of the substrate 710, and the anode electrode 740 is exposed to the outside through the sixth pattern mask, as shown in FIG. 18. The planarization thin film 790 and the source / drain insulating layer 770 are patterned to complete the manufacture of the display element for the flat panel display device.

Subsequently, an organic electroluminescent material (not shown) for generating light having a predetermined wavelength is formed on the exposed top surface of the anode electrode 740 among the display elements for the flat panel display device manufactured as described above, and the conductive surface is formed on the top surface of the organic electroluminescent material. By forming a cathode electrode (not shown), an organic electroluminescent device is manufactured.

<Example 2>

Meanwhile, in <Example 2> to be described later, a process of forming a display device using six pattern masks without protecting the anode electrode and without a negative photoresist forming process and a backside exposure process is disclosed.

19 is a continuous process after the processes of FIGS. 3 to 8 are performed. Referring to FIG. 8, the gate thin film 750 coated on the entire surface of the upper surface of the substrate 710 may be ionized on the upper surfaces of the ion stopper layers 120 and 220. After the photoresist thin film is applied to have a smaller area than the stopper layers 120 and 220 and the gate thin film 750 is left on the upper surface of the first electrode 310 and the anode electrode 740 of the charging capacitance 300. Photoresist thin film patterning is performed by the third pattern mask.

Thereafter, as illustrated in FIG. 20, the ion stopper layers 120 and 220 protruding from the gates 130 and 230 are selectively etched by a material selectively etching only indium tin oxide using the remaining photoresist thin film or the remaining gate thin film as a mask. In the state, low concentration ion doping is performed on the substrate 710.

Thereafter, as shown in FIG. 21, all the source / drain electrodes 140, 150, 240, and 250 are formed in the same manner as in FIG. 14 or 15.

Subsequently, as shown in FIG. 22, the planarization film 790 is thinly formed over the entire surface of the substrate 710 with the gate thin film remaining on the upper surface of the anode electrode 740, and then, as shown in FIG. 23. As described above, the gate thin film covering the anode electrode 740 and the planarization layer 790 of the corresponding portion are also patterned to expose the anode electrode 740 using the sixth pattern mask.

Reference numeral 755 denotes an anode electrode protection gate thin film covering the top surface of the anode electrode 740.

According to <Example 2>, a display device for a flat panel display device can be manufactured by a simpler process than in <Example 1>, and the anode electrode, which is easily damaged, is covered with the anode electrode protective gate thin film 755 to protect the same. The damage of the sensitive anode electrode 740 can be minimized by removing the anode electrode protection gate thin film 755 that covers the anode electrode 740 using the last sixth pattern mask.

<Example 3>

Unlike Example 1 and Example 2, Example 3 fabricates a display device for a flat panel display having an LDD structure using seven pattern masks. 8, the gates 130 and 230, the first electrode 130 having the charging capacitance, and the anode electrode 740 are formed on the upper surfaces of the ion stopper layers 120 and 210.

Subsequently, as shown in FIG. 25, the ion stopper layers 120 and 220 are formed using the gates 130 and 230 as masks while the photoresist thin film 820 is formed only on the upper surface of the anode electrode 740 using one pattern mask. ) Is doped with impurities by low concentration ion implantation in the patterned state as shown in FIG. 26 to form low concentration doped regions 114 and 214.

Subsequently, after removing the photoresist thin film 820 formed on the upper surface of the anode electrode 740, the remaining process including FIG. 14 is performed to fabricate a display device for a flat panel display device.

As described in detail above, a flat panel display display element used in a liquid crystal display device or an organic electroluminescent device may have an LDD structure or an offset structure that improves electrical characteristics while reducing the number of pattern masks required to fabricate the same. By doing so, it is possible to reduce the process required for manufacturing.

Claims (9)

At least one thin film transistor and a pixel electrode are provided such that the first and second signal lines arranged in a matrix form, a pixel region formed at an intersection of the first and second signal lines, and a specified output signal are applied to the pixel region. In the method for manufacturing a display element of the flat panel display device, Forming a semiconductor layer having a first area by applying a semiconductor material to a predetermined region of the substrate to form a semiconductor thin film, and then patterning the semiconductor thin film using a first pattern mask; After the first insulating film is formed on the upper surface of the semiconductor layer, the conductive transparent thin film is patterned through a second pattern mask while the conductive transparent thin film is formed on the upper surface of the first insulating film to correspond to the upper portion of the semiconductor layer. Forming an ion stopper layer formed on an upper surface of the first insulating film to have a second area smaller than the first area, and the pixel electrode at a predetermined distance from the ion stopper layer; A third pattern is formed by doping ions having a first concentration in a portion not covered by the ion stopper layer to form first doped regions on both sides of the semiconductor layer, and forming a conductive gate thin film over the entire surface of the substrate. Forming a gate and a first signal line connected to the gate to have a third area smaller than the second area on an upper surface of the ion stopper except for the pixel electrode through a mask; After removing the portion of the ion stopper layer that is not covered by the gate while preventing the pixel electrode from being patterned, the pixel electrode is doped with ions having a second concentration in the portion that is not covered by the gate to form an inner side of the first doped region. Forming a contact hole to expose the first doped region using a fourth pattern mask after forming a second insulating film over the entire surface of the substrate with the second doped region formed on the substrate; Forming a source electrode connected to the second signal line and a drain electrode connected to the pixel electrode in the first doped region with a fifth pattern mask while the conductive thin film is formed on the upper surface of the substrate. The manufacturing method of a display element. The method of claim 1, further comprising: forming a planarization film on the substrate after forming the source electrode and the drain electrode, and patterning the pixel electrode of the planarization film to be exposed using a sixth pattern mask. The manufacturing method of the display element for flat panel displays. The method of claim 1, wherein the removing of the portion of the ion stopper layer that is not covered by the gate is performed while preventing the pixel electrode from being patterned. Applying a negative photoresist over the entire surface of the substrate including the top surface of the pixel electrode; Performing a backside exposure from the backside of the substrate to the topside of the substrate and patterning the negative photoresist to remain only on the topside of the pixel electrode; And etching the ion stopper layer that is not covered by the gate using the gate as a mask. The method of claim 1, wherein the doping concentration of the first doped region is higher than the doping concentration of the second doped region. The method of claim 1, wherein a buffer layer is further formed between the semiconductor layer and the substrate such that impurities do not diffuse from the substrate to the semiconductor layer. At least one thin film transistor and a pixel electrode are provided such that the first and second signal lines arranged in a matrix form, a pixel region formed at an intersection of the first and second signal lines, and a specified output signal are applied to the pixel region. In the method for manufacturing a display element of the flat panel display device, Forming a semiconductor layer having a first area by applying a semiconductor material to a predetermined region of the substrate to form a semiconductor thin film, and then patterning the semiconductor thin film using a first pattern mask; After the first insulating film is formed on the upper surface of the semiconductor layer, the conductive transparent thin film is patterned through a second pattern mask while the conductive transparent thin film is formed on the upper surface of the first insulating film to correspond to the upper portion of the semiconductor layer. Forming an ion stopper layer formed on an upper surface of the first insulating film to have a second area smaller than the first area, and the pixel electrode at a predetermined distance from the ion stopper layer; A third pattern is formed by doping ions having a first concentration in a portion not covered by the ion stopper layer to form first doped regions on both sides of the semiconductor layer, and forming a conductive gate thin film over the entire surface of the substrate. Forming a gate thin film for protecting the pixel electrode formed over the entire surface of the pixel electrode through a mask, a gate having a third area smaller than the second area of the ion stopper, and a first signal line connected to the gate; After removing a portion of the ion stopper layer that is not covered by the gate, a portion of the ion stopper layer that is not covered by the gate is doped with ions having a second concentration to form a second doped region inside the first doped region. Forming a contact hole to expose the first doped region using a fourth pattern mask after forming a second insulating film over the entire surface of the substrate in a state; Forming a source electrode connected to a second signal line and a drain electrode connected to the pixel electrode in the first doped region using a fifth pattern mask while a conductive thin film is formed on the upper surface of the substrate; After applying the planarization film over the entire surface of the substrate, patterning and removing the planarization film corresponding to the upper surface of the pixel electrode and the pixel electrode protection gate thin film covering the pixel electrode through a sixth pattern mask; The manufacturing method of the display element for flat panel displays. At least one thin film transistor and a pixel electrode are provided such that the first and second signal lines arranged in a matrix form, a pixel region formed at an intersection of the first and second signal lines, and a specified output signal are applied to the pixel region. In the method for manufacturing a display element of the flat panel display device, Forming a semiconductor layer having a first area by applying a semiconductor material to a predetermined region of the substrate to form a semiconductor thin film, and then patterning the semiconductor thin film using a first pattern mask; After the first insulating film is formed on the upper surface of the semiconductor layer, the conductive transparent thin film is patterned through a second pattern mask while the conductive transparent thin film is formed on the upper surface of the first insulating film to correspond to the upper portion of the semiconductor layer. Forming an ion stopper layer formed on an upper surface of the first insulating film to have a second area smaller than the first area, and the pixel electrode at a predetermined distance from the ion stopper layer; A third pattern is formed by doping ions having a first concentration in a portion not covered by the ion stopper layer to form first doped regions on both sides of the semiconductor layer, and forming a conductive gate thin film over the entire surface of the substrate. Forming a gate and a first signal line connected to the gate to have a third area smaller than the second area on an upper surface of the ion stopper except for the pixel electrode through a mask; Patterning the photoresist thin film so that only the pixel electrode is covered by a fourth pattern mask while the photoresist thin film is applied over the entire surface of the substrate; After removing the portion of the ion stopper layer that is not covered by the gate with the gate as a mask, the portion of the ion stopper layer that is not covered by the gate is doped with ions having a second concentration to form the inside of the first doped region. Forming a contact hole to expose the first doped region using a fifth pattern mask after forming a second insulating film over the entire surface of the substrate in a state where the second doped region is formed; Forming a source electrode connected to the second signal line and a drain electrode connected to the pixel electrode in the first doped region by using a sixth pattern mask while the conductive thin film is formed on the upper surface of the substrate. The manufacturing method of a display element. At least one thin film transistor and a pixel electrode are provided such that the first and second signal lines arranged in a matrix form, a pixel region formed at an intersection of the first and second signal lines, and a specified output signal are applied to the pixel region. In the display element of the flat panel display device, A semiconductor layer formed to have a first area at a predetermined position of the substrate, and having a first doped region formed in a band shape along an edge thereof, and having a second doped region formed in a band shape inside the first doped region; A first insulating film covering the semiconductor layer; An ion stopper layer formed at a position corresponding to an inside of the second doped region among upper surfaces of the first insulating layer corresponding to the semiconductor layer; A pixel electrode formed on the first insulating film spaced apart from the ion stopper layer by a predetermined distance; A gate formed on an upper surface of the ion stopper layer; The first signal line connected to the gate; A source electrode having one side connected to one of the first doped regions of the semiconductor layer and the other side connected to the second signal line; And a drain electrode connected to the other one of the first doped regions of the semiconductor layer and the other side connected to the pixel electrode. The display device of claim 8, wherein the ion stopper layer and the pixel electrode are made of the same material.

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