KR100577015B1 - Stacked chip package of semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a laminated chip package of a semiconductor device and a method of manufacturing the same, and in particular, the method of the present invention forms a hole penetrating between one electrode pad separated from the electrode pad disposed on the top surface of the first semiconductor chip substrate. Forming a hole wiring connected through the electrode pads separated from the hole; grinding the lower surface of the first semiconductor chip substrate until the bottom surface of the hole wiring is exposed; and a second semiconductor. Connecting the electrode pad of the chip and the lower end hole wiring of the first semiconductor chip through the connection portion, bonding the lower substrate of the second semiconductor chip to the package body, and attaching the second semiconductor chip to the lead frame of the package body. Connecting the electrode pads. Therefore, the present invention can freely change the position of the electrode pad in the semiconductor chip during the manufacturing process of the laminated chip package, and wire bonding with the external lead frame only to the lower semiconductor chip can omit the wire bonding of the upper semiconductor chip, thereby improving the accuracy of wire bonding. It can increase.

Multilayer Chip Package, First Semiconductor Chip, Second Semiconductor Chip, Grind

Description

Stacked chip package of semiconductor device and manufacturing method therefor {STACKED CHIP PACKAGE OF THE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF}             

1 to 7 are process flowcharts illustrating a manufacturing process of a laminated chip package of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: first semiconductor chip 12a: electrode pads separated from each other

14 photoresist pattern 16 holes

18: hole wiring 20: the second semiconductor chip

22 electrode pad 24 connection part

30: package body 32: adhesive

34: wire

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package of a semiconductor device and a method of manufacturing the same, and more particularly, to a laminated chip package of a semiconductor device and a method of manufacturing the same.

To meet the high density, high integration, and various functional requirements of semiconductor products, chip packages are being developed and manufactured to achieve high direct roads by embedding a large number of semiconductor chips. In recent years, SOC (System On Chip) technology has been developed to make chips with different functions in order to realize semiconductor chips with various functions. The development of a single process technology that does not give a progress but is a very difficult problem.

In order to compensate for this, a stacked chip package technology, in which two or more semiconductor chips, which are processed in different processes, are stacked on each other and manufactured into one package, has emerged. Such a laminated chip package is designed by setting the positions of the electrode pads for connection of the semiconductor chips stacked on each other in advance, and in this case, the positions of the electrode pads must be placed along the edges of the chips. Therefore, there is a difficulty in selecting the electrode pad position. In addition, a lot of effort and high accuracy are required so that wires are not staggered according to electrode pad positions during wire bonding, and there is a problem in that damage caused by impact of a lower chip is caused during wire bonding of an upper semiconductor chip.

An object of the present invention is to add a hole wiring penetrating vertically to the lower surface of the substrate of the semiconductor chip of any one of the stacked semiconductor chip in order to solve the problems of the prior art as described above, and the electrode of the other semiconductor chip The present invention provides a stacked chip package of a semiconductor device in which pads may be connected to each other to stack semiconductor chips to form a package, and thus the pad position of the semiconductor chip may be freely changed.

Another object of the present invention is to add a vertical wiring to the hole through the electrode pad of the semiconductor chip and to grind the bottom surface of the substrate so that the vertical wiring is exposed, the semiconductor chip is laminated by connecting the electrode pad and the hole wiring of another semiconductor chip The present invention provides a method for manufacturing a stacked chip package of a semiconductor device capable of freely changing a pad position in a semiconductor chip by manufacturing a package.

In order to achieve the above object, the present invention is a laminated chip package in which at least two semiconductor chips are mounted, which is disposed on an upper surface of a substrate and is connected through an electrode pad separated from each other and an electrode pad separated from each other. A first semiconductor chip having a hole wiring extending from the top surface to the bottom surface of the substrate, a second semiconductor chip having an electrode pad disposed on the top surface of the substrate, and a bottom hole wiring of the bottom surface of the first semiconductor chip; The connection part connected with the electrode pad of this invention is provided.

In order to achieve the above another object, the present invention provides a method of manufacturing a laminated chip package in which at least two semiconductor chips are mounted, comprising: between one electrode pad separated from an electrode pad disposed on an upper surface of a first semiconductor chip substrate; Forming a hole through the hole; forming a hole wiring connected through the electrode pad by embedding a metal film in the hole and planarizing the surface thereof; and forming a hole wiring on the bottom surface of the first semiconductor chip substrate. Grinding until the bottom surface of the semiconductor substrate is exposed, and connecting the electrode pad of the second semiconductor chip and the lower end hole wiring of the first semiconductor chip through the connection portion.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are flowcharts illustrating a process of manufacturing a stacked chip package of a semiconductor device according to the present invention. Referring to these drawings, the laminated chip package of the semiconductor device of the present invention is manufactured as follows.

First, as shown in FIG. 1, an electrode pad 12 for completing a manufacturing process of a semiconductor device on a silicon on insulator (SOI) substrate as a substrate 10 of a first semiconductor chip and connecting to another chip on an upper surface of the substrate To form.

As shown in FIG. 2, a photoresist pattern 14 is formed on the upper surface of the substrate 10 of the first semiconductor chip to form a photoresist pattern 14 for opening a portion of one electrode pad 12. .

As shown in FIG. 3, the electrode pad 12 exposed by the photoresist pattern 14 and the substrate under the substrate are etched to a predetermined depth to form a vertical wiring to be subsequently connected to the electrode pad of another semiconductor chip. The hole 16 is formed. For this reason, since the holes penetrate between one electrode pad 12, they are separated 12a from each other by the holes. Then, the photoresist pattern 14 is removed.

Then, as shown in FIG. 4, the metal film 18 is gap-filled in the hole of the substrate 10 of the first semiconductor chip, and the surfaces thereof are planarized by chemical mechanical polishing (CMP) to separate the metal films 18 from each other. The hole wiring 18a which penetrates and connects between one electrode pad 12a is formed.

Then, the entire bottom surface of the first semiconductor chip substrate 10 shown in FIG. 5 is ground, but the bottom surface of the hole wiring 18a is exposed or the hole wiring 18a is exposed to a predetermined position. The reason for grinding in this way is to electrically connect the electrode pad of the first semiconductor chip and the electrode pad of the other semiconductor chip through the hole wiring 18a during the packaging process of the semiconductor chips.

Although not shown in the drawings, the first semiconductor chip substrate 10 is sawed in chip units.

Next, as shown in FIG. 6, the process of manufacturing the semiconductor device is completed, and the second semiconductor chip 20 having the electrode pads 22 to be connected to other chips on the upper surface of the substrate is prepared. In this case, it is important to dispose the electrode pads 22 of the second semiconductor chip 20 to be electrically connected to the electrode pads 12 of the first semiconductor chip 10. This is because the electrode pad positions of the semiconductor chips are bumped in an aligned state when the semiconductor chips are stacked. Therefore, the electrode pad 22 of the second semiconductor chip 20 to be electrically connected to the electrode pad 12 of the first semiconductor chip 10 may be disposed outside the chip as in the prior art, but the pad may be located anywhere on the chip. have. However, in the case of an electrode pad to be electrically connected to an external lead frame of the package body, it is preferable to arrange the outer edge of the chip in a conventional manner.

In the process using a bump, the electrode pad 22 of the second semiconductor chip 20 and the lower end hole wiring 18a of the first semiconductor chip 10 are crimped with the bumps, which are the connection portions 24, to form the first. The electrode pads 12a and 22 of the semiconductor chip 10 and the second semiconductor chip 20 are electrically connected to each other.

As shown in FIG. 7, the lower surface of the second semiconductor chip 20 is adhered to the package body 30 with an adhesive 32 such as epoxy resin, wherein the package body 30 is attached to the second semiconductor chip 20. The mounting groove may be provided separately.

Then, a wire bonding process is performed on the electrode pad 22 for external connection of the second semiconductor chip 20 and the lead frame 36 of the package body 30 to perform the electrode of the second semiconductor chip 20. The pad 22 and the lead frame 36 are connected by a wire 34 to complete the stacked chip package according to the present invention. In this case, it is preferable that the electrode pad 22 of the second semiconductor chip 20 to be connected to the lead frame 36 of the package body 30 is disposed outside the region of the first semiconductor chip 10.

The stacked chip package of the semiconductor device of the present invention manufactured as described above has a hole wiring 18a vertically penetrating between one electrode pad 12a separated from each other and one electrode pad 12a separated from each other and extending to the bottom surface of the substrate. ), The first semiconductor chip 10 having the first semiconductor chip 10, the second semiconductor chip 20 having the electrode pads 22 disposed on the upper surface of the substrate, and the lower end hole wiring 18a of the first semiconductor chip 10. It is electrically connected with the upper electrode pad 22 of the 2nd semiconductor chip 20 through the bump 24 which is this connection part. The lower surface of the second semiconductor chip 20 is attached to the package body 30 by being bonded with an adhesive 32, and the outer electrode pads of the second semiconductor chip 20 on the lead frame 36 of the package body 30 ( 22 is electrically connected via wire 34.

As described above, according to the present invention, in the manufacturing process of the multilayer chip package, a hole wiring penetrating vertically through one electrode pad in one semiconductor chip and penetrating to the lower surface of the substrate is added. The electrode pads can be connected by bumps to produce a laminated chip package, and thus the position of the electrode pads in the semiconductor chip can be freely changed.

In addition, the wire bonding of the upper semiconductor chip can be omitted since wire bonding with the external lead frame is performed only on the lower semiconductor chip during wire bonding of the semiconductor chip, thereby increasing the accuracy of wire bonding and reducing the wire bonding burden and impact of the lower semiconductor chip. It can be minimized.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (14)

In a stacked chip package in which at least two semiconductor chips are mounted, A first semiconductor chip disposed on an upper surface of the substrate and having electrode holes separated from each other, and a hole wiring connected between the electrode pads separated from each other and extending from the upper surface to the lower surface of the substrate; A second semiconductor chip having an electrode pad disposed on an upper surface of the substrate; And A connection portion for connecting the lower end hole wiring of the first semiconductor chip with the electrode pad of the second semiconductor chip; And stacking electrode pads of the second semiconductor chip to be electrically connected to the electrode pads of the first semiconductor chip to be aligned with each other. delete The multilayer chip package of claim 1, wherein the electrode pads of the second semiconductor chip to be electrically connected to the electrode pads of the first semiconductor chip are arranged to be aligned with each other inside or outside the chip. The multilayer chip package of claim 1, further comprising a package body having a lead frame bonded to a lower surface of the second semiconductor chip and connected to an electrode pad of the second semiconductor chip. The multilayer chip package of claim 4, wherein a connection between the electrode pad of the second semiconductor chip and the lead frame of the package body is connected by a wire. 5. The multilayer chip package of claim 1, wherein the electrode pad of the second semiconductor chip to be connected to the lead frame of the package body is disposed in an outer region of the first semiconductor chip. 6. The multilayer chip package of claim 1, wherein the connection part is a bump. In the method of manufacturing a laminated chip package mounted with at least two semiconductor chips, Forming a hole penetrating between one pad separated from an electrode pad disposed on an upper surface of the first semiconductor chip substrate; Embedding a metal film in the hole and planarizing a surface thereof to form a hole wiring connected through the separated one electrode pad; Grinding the bottom surface of the first semiconductor chip substrate until the bottom surface of the hole wiring is exposed; And The electrode pads of the second semiconductor chip to be electrically connected to the electrode pads of the first semiconductor chip are arranged to be aligned with each other. And connecting the electrode pad of the second semiconductor chip and the lower end hole wiring of the first semiconductor chip through a connection part. delete The method of claim 8, wherein the electrode pads of the second semiconductor chip to be electrically connected to the electrode pads of the first semiconductor chip are arranged to be aligned with each other inside or outside the chip. The method of claim 8, wherein after connecting the electrode pad of the second semiconductor chip and the lower end hole wiring of the first semiconductor chip through a connection portion, Adhering the lower substrate of the second semiconductor chip to a package body; And connecting an electrode pad of the second semiconductor chip to a lead frame of the package body. 12. The method of claim 11, wherein the electrode pad of the second semiconductor chip and the lead frame of the package body are connected by wires. The method of claim 8, wherein the electrode pad of the second semiconductor chip to be connected to the lead frame of the package body is disposed in an outer region of the semiconductor chip. Way. The method of claim 8, wherein the connection part is a bump.

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