KR100561645B1 - Liquid Crystal Display Panel and Method of Fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method of manufacturing the same that can simplify the manufacturing process and improve the yield.

The present invention provides a semiconductor device comprising: a first substrate having a thin film transistor array region in which a plurality of signal lines and thin film transistors are formed, and a pad region in which pads connected to the signal lines are formed; A second substrate facing the pad region of the first substrate to be exposed; And at least two rows of materials for joining the first and second substrates together.

Description

Liquid Crystal Display Panel and Method of Fabricating the same

1 is a plan view illustrating a portion of a thin film transistor array substrate included in a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are cross-sectional views illustrating the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view schematically showing a liquid crystal display panel for explaining a technique related to an embodiment of the present invention.

FIG. 5 is a plan view illustrating a thin film transistor array substrate of the liquid crystal display panel illustrated in FIG. 4.

FIG. 6 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 5 along the line II-II ′.

7A through 7D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 6.

8 is a diagram illustrating a step of dipping a pad region in an etchant to expose a pad of a liquid crystal display panel.

9 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the liquid crystal display panel shown in FIG. 9.

         <Explanation of symbols for the main parts of the drawings>

2, 152: gate line 4,174: data line

6, 190: thin film transistor 8, 154: gate electrode

10, 162: source electrode 12,195: drain electrode

14 and 164: active layer 16: first contact hole

18 and 160 pixel electrodes 28 and 156 gate pads

184: data pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display panel and a method for manufacturing the same, which can simplify a manufacturing process and improve a yield.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal display panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

In the liquid crystal display panel, the thin film transistor array substrate includes a semiconductor process and also requires a plurality of mask processes, and thus, the manufacturing process is complicated, thereby increasing the manufacturing cost of the liquid crystal display panel. In order to solve this problem, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a thin film transistor array substrate.

FIG. 1 is a plan view of a thin film transistor array substrate employing a four mask process, for example. FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line ( And a data pad portion 34 connected to 4).

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and the source electrode 10 and the drain electrode ( 12) further comprises a channel section therebetween. An ohmic contact layer 48 for ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. do. The thin film transistor 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes the front gate line 2, the storage electrode 22 overlapping the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween. And a pixel electrode 22 which is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad lower electrode 26 is formed through the gate pad lower electrode 28 extending from the gate line 2 and the third contact hole 30 penetrating through the gate insulating layer 44 and the passivation layer 50. And a gate pad upper electrode 32 connected to (28).

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad portion 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. The data pad upper electrode 40 is formed.

A method of manufacturing a thin film transistor substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, gate patterns are formed on the lower substrate 42.

The gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate patterns including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 3B, the gate insulating layer 44, the active layer 14, the ohmic contact layer 48, and the source / drain patterns are sequentially formed on the lower substrate 42 on which the gate patterns are formed.

The gate insulating layer 44, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate patterns are formed through a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Next, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 22 are formed. Source / drain patterns including are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 48 and the active layer 14.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 3C, a passivation layer 50 including first to fourth contact holes 16, 24, 30, and 38 is formed on the gate insulating layer 44 on which the source / drain patterns are formed.

The passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 50 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 16, 24, 30, and 38. The first contact hole 16 is formed to pass through the passivation layer 50 to expose the drain electrode 12, and the second contact hole 24 is formed to pass through the passivation layer 50 to expose the storage electrode 22. do. The third contact hole 30 is formed to pass through the passivation layer 50 and the gate insulating layer 44 to expose the gate pad lower electrode 28. The fourth contact hole 38 is formed through the passivation layer 50 to expose the data pad lower electrode 36.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 94 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, transparent electrode patterns are formed on the passivation layer 50.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is immersed through a photolithography process and an etching process using a fourth mask, thereby forming transparent electrode patterns including the pixel electrode 18, the gate pad upper electrode 32, and the data pad upper electrode 40. Is formed. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16 and overlaps the shear gate line 2 through the second contact hole 24. And electrically connected. The gate pad upper electrode 32 is electrically connected to the gate pad lower electrode 28 through the third contact hole 30. The data pad upper electrode 40 is electrically connected to the data pad lower electrode 36 through the fourth contact hole 38. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same may reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four-mask process is still complicated and the manufacturing cost is limited, there is a need for a liquid crystal display panel and a method of manufacturing the same, which further simplify the manufacturing process and further reduce manufacturing costs.

On the other hand, the conventional pad portion opening process of the thin film transistor array substrate is performed by a photolithography process, which causes a complicated process.

Accordingly, an object of the present invention relates to a liquid crystal display panel and a method for manufacturing the same, which can simplify the manufacturing process and improve the yield.

In order to achieve the above object, the liquid crystal display device according to an embodiment of the present invention
A thin film transistor array substrate including an array region in which a plurality of signal lines and thin film transistors are formed, and a pad region in which pads for transmitting driving signals are located on the signal lines; And a color filter array substrate bonded to the thin film transistor array substrate using at least two rows of materials, wherein the at least two rows of materials are located between the pad area and the array area to expose the pad area to the outside. do.
The thin film transistor array region may include a passivation layer protecting the thin film transistor, and the pad region may include the passivation layer removed to expose the pad.

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The pad is characterized in that formed of a transparent conductive layer.

The pad is characterized in that formed of a double layer of a transparent conductive layer and a metal layer.
A method of manufacturing a liquid crystal display panel according to the present invention includes forming a thin film transistor array substrate having a thin film transistor array region in which a plurality of signal lines and thin film transistors are formed, and a pad region in which pads connected to the signal lines are formed; Forming a color filter array substrate facing the thin film transistor array substrate such that the pad region is exposed; Bonding the thin film transistor array substrate and the color filter array substrate to each other using at least two rows of materials positioned between the array region and the pad region to expose the pad region to the outside; And dipping the pad area in an etchant to expose the pad.

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The forming of the first substrate may include forming a first pattern including a gate line, a gate electrode, a gate pad, a data pad, and a pixel electrode using a first mask process; Forming a second pattern including a gate insulating pattern and a semiconductor pattern on the first pattern except the pixel electrode by using a second mask process; Forming a third pattern including a data line, a source electrode, a drain electrode, and a storage electrode using a third mask process; And forming a passivation layer over the pad region and the thin film transistor array region.

The exposing the pad may include removing the passivation layer from the pad area.

The etchant comprises about 20: 1 H ₂ O (water) and HF (fluoric acid).

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 10.

Prior to the detailed description of the present invention, a description will first be made of techniques directly related to the present invention.

4 is a plan view schematically illustrating a liquid crystal display panel. 5 is a plan view illustrating a thin film transistor array substrate of the liquid crystal display panel illustrated in FIG. 4, and FIG. 6 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 5 taken along line II-II ′.

4 to 6 may include a gate line 152 and a data line 174 formed on the lower substrate 151 with the gate insulating pattern 162 interposed therebetween, and formed at each intersection thereof. And a thin film transistor 190 and a pixel electrode 160 formed in a cell region provided in an intersecting structure. The thin film transistor array substrate includes a storage capacitor 192 formed at an overlapping portion of the storage electrode 180 connected to the pixel electrode 160 and the front gate line 152, and a gate pad connected to the gate line 152. 156 and a data pad 184 connected to the data line 174.

The thin film transistor 190 may include a gate electrode 154 connected to the gate line 152, a source electrode 176 connected to the data line 174, a drain electrode 195 connected to the pixel electrode 160, and the like. And an active layer 164 overlapping with the gate electrode 154 and the gate insulating pattern 162 therebetween and forming a channel between the source electrode 176 and the drain electrode 195. The ohmic contact layer 168 between the active layer 164, the source electrode 176, and the drain electrode 195 is further provided. The thin film transistor 190 keeps the pixel voltage signal supplied to the data line 174 charged and maintained in the pixel electrode 160 in response to the gate signal supplied to the gate line 152.

The gate line 152 and the gate electrode 154 have a structure in which the transparent conductive layer 153 and the gate metal layer 155 are stacked.

The pixel electrode 160 is formed on the lower substrate 151 and is connected to the drain electrode 195 of the thin film transistor 190. The pixel electrode 160 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates due to dielectric anisotropy, and transmits light incident through the pixel electrode 160 from the light source (not shown) toward the upper substrate.

The storage capacitor 192 includes a front gate line 152, a storage electrode 180 overlapping the gate line 152 and the gate insulating pattern 162, and connected to the pixel electrode 160. The storage capacitor 192 helps to maintain the pixel voltage charged in the pixel electrode 160 until the next pixel voltage is charged.

The gate line 152 is connected to a gate driver (not shown) through the gate pad 156. The gate pad 156 is formed of a transparent conductive layer.

The data line 174 is connected to a data driver (not shown) through the data pad 184. The data pad 184 is connected to the data line 174 and is formed of a transparent conductive layer.

The thin film transistor array substrate having such a configuration is formed by a three mask process. A thin film transistor array substrate manufacturing method according to an exemplary embodiment of the present invention using a three mask process includes a first mask process for forming gate patterns and a pixel electrode, and a second process for forming a gate insulating pattern, an active layer, and an ohmic contact layer. A mask process and a third mask process for forming source / drain patterns are included.

First, as shown in FIG. 7A, the transparent conductive layer 153 and the gate metal layer 155 are sequentially deposited on the lower substrate 151 through a deposition method such as a sputtering method. Subsequently, the transparent conductive layer 153 and the gate metal layer 155 are patterned by a photolithography process and an etching process using a first mask to form a gate pad having the gate line 152, the gate electrode 154, and the gate metal layer 155. 156, first patterns including the pixel electrode 160 and the data pad 184 are formed. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as a material of the transparent conductive layer. As the gate metal layer 155, copper (Cu), chromium (Cr), molybdenum (Mo), an aluminum metal, or the like is used.

The gate insulating layer, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower substrate 151 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating layer, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Subsequently, the n + amorphous silicon layer, the amorphous silicon layer, and the gate insulating layer are patterned by a photolithography process and an etching process using a second mask, thereby forming the pixel electrode 160 having the gate metal layer 155 formed thereon as shown in FIG. 7B. A second pattern including the gate insulating pattern 162 and the semiconductor pattern 147 is formed on the first pattern except for the one. The semiconductor pattern 147 has a structure in which the active layer 164 and the ohmic contact layer 168 are stacked in duplicate.

A source / drain metal layer is formed on the lower substrate 151 on which the lower substrate 151 on which the semiconductor pattern 147 is formed is formed.

Then, the photoresist is entirely coated and then a photoresist pattern is formed by a photolithography process using a third mask. In this case, a diffraction exposure mask having a diffraction exposure portion in a specific region is used as the third mask. The photoresist pattern formed by the diffraction mask exposes the gate pad 156, the pixel electrode 160, and the data pad 184 on which the gate metal layer 155 is formed, and has a different source / photoresist pattern in the channel portion of the thin film transistor. It has a lower height than the photoresist pattern of the drain pattern portion.

Subsequently, the gate metal layer 155 formed on the gate pad 156, the pixel electrode 160, and the data pad 184 is removed by an etching process using the photoresist pattern as a mask, and the source electrode 176 of the data line 174 is removed. ), Third patterns including the drain electrode 172 and the storage electrode 180 integrated with the source electrode 176 are formed.

Next, a portion of the semiconductor pattern 147 of the semiconductor pattern 147 and the storage capacitor 192 formed on the pads 156 and 184 is removed by a dry etching process using the same photoresist pattern.

Thereafter, the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 168 of the channel portion are etched by a dry etching process. Accordingly, as shown in FIG. 7C, the active layer 164 of the channel portion is exposed to separate the source electrode 174 and the drain electrode 195.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), aluminum-based metal and the like are used.

Subsequently, the passivation layer 150 is entirely formed on the lower substrate 151.

As described above, the thin film transistor array substrate formed by the three mask process is applied to the color filter array substrate such that the pad region of the thin film transistor array substrate is exposed using the material 99 after the lower alignment layer 117 is applied as shown in FIG. 7D. And coalesce. The color filter array substrate includes a black matrix 102 formed in a mattress shape on the upper substrate 100, a color filter 104 formed for each cell region divided into a black matrix 102, a black matrix 102 and a color filter. The common electrode 106 and the upper alignment layer 108 are sequentially stacked on the 104.

As described above, after the plurality of thin film transistor array substrates are formed on the lower substrate 151 by the three mask process, the plurality of liquid crystal display panels are separated by the scribing process. Liquid crystal is injected into the separated liquid crystal display panel, and the pad region 300 of the liquid crystal display panel into which the liquid crystal is injected is dipped into the etching liquid 220 by dipping as shown in FIG. 8. Accordingly, the color filter array substrate is used as a mask to remove the passivation layer 150 formed on the pads 156 and 184, thereby exposing the gate and the data pads 156 and 184. Here, a buffered oxide etchant (hereinafter referred to as "BOE") is used as an etchant. BOE is a mixture of H ₂ O (water) and HF (fluoric acid) in a ratio of about 20: 1.

As described above, the liquid crystal display panel and its manufacturing method are formed by a three mask process, and a pad portion opening process is performed by a dipping method. This makes it possible to simplify the substrate structure and the manufacturing process.

On the other hand, during the pad opening process by the dipping method, there is a problem that a defect such as contamination of the liquid crystal cells by a small amount of the etching liquid penetrates into the liquid crystal panel through the material 99 by the capillary phenomenon.

9 and 10 are cross-sectional views illustrating a liquid crystal display panel and a method of manufacturing the same according to an embodiment of the present invention.

9 and 10 have the same components except that the realities 99a and 99b are formed in two rows as compared to the liquid crystal display panels shown in FIGS. 4 and 6. Like reference numerals designate like elements and detailed descriptions thereof will be omitted.

According to an exemplary embodiment of the present invention, a liquid crystal display panel and a manufacturing method thereof include a thin film transistor array substrate and a color filter array substrate formed by a three mask process, as shown in FIG. 9, in which a pad region 300 and a thin film transistor are formed. Two rows of materials 99a and 99b between the array regions 125 and one row of materials 99 of the thin film transistor array region 125 are bonded together.

The two rows of materials 99a and 99b prevent the etchant from penetrating into the liquid crystal panel cell by a capillary phenomenon during the pad opening process by the dipping method. That is, since two rows of materials 99a and 99b are formed, even a small amount of the etching liquid penetrates through the materials 99a formed at the outside of the panel during the pad opening process, the traces of the etching liquid are blocked by the materials 99b formed inside the panel. Accordingly, as the etching solution 220 penetrates into the panel, defects such as contamination of the liquid crystal cells may be prevented.

A liquid crystal display panel and a method for manufacturing the same according to an embodiment of the present invention are the same as the manufacturing method except for forming the actual (99a, 99b) in two rows as compared to the manufacturing method of the liquid crystal display panel shown in Figs. Is formed by.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention form a thin film transistor array substrate by a three mask process, and a pad open process is performed by a dipping method. As a result, the manufacturing process can be simplified and the yield can be improved.

In addition, the thin film transistor array substrate and the color filter array substrate are bonded together by two rows of materials 99a and 99b to prevent the etching solution from penetrating into the panel during the pad opening process by the dipping method.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the embodiment of the present invention, by forming a thin film transistor by a three mask process and a pad opening process by a dipping method, the manufacturing process is simplified and the yield is improved. do.

In addition, in the liquid crystal display panel and the method of manufacturing the same according to the embodiment of the present invention, the thin film transistor array substrate and the color filter array substrate are bonded by two rows of materials. Accordingly, when the pad is opened by the dipping method, the etchant is prevented from penetrating into the panel, thereby preventing a defect such as contamination of the panel.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A thin film transistor array substrate including an array region in which a plurality of signal lines and thin film transistors are formed, and a pad region in which pads for transmitting driving signals are located on the signal lines; A color filter array substrate bonded to the thin film transistor array substrate using at least two real materials; And the at least two rows of materials are disposed between the pad area and the array area to expose the pad area to the outside. delete The method of claim 1, And wherein the array region includes a passivation layer protecting the thin film transistor, and wherein the pad region is removed to expose the pad. The method of claim 1, And the pad is formed of a transparent conductive layer. The method of claim 1, The pad is a liquid crystal display panel, characterized in that formed of a double layer of a transparent conductive layer and a metal layer. Forming a thin film transistor array substrate having a thin film transistor array region having a plurality of signal lines and thin film transistors formed therein, and a pad region having pads connected to the signal lines; Forming a color filter array substrate facing the thin film transistor array substrate such that the pad region is exposed; Bonding the thin film transistor array substrate and the color filter array substrate to each other using at least two rows of materials positioned between the array region and the pad region to expose the pad region to the outside; And dipping the pad area into an etchant to expose the pad. delete The method of claim 6, Forming the thin film transistor array substrate Forming a first pattern including a gate line, a gate electrode, a gate pad, a data pad, and a pixel electrode using a first mask process; Forming a second pattern including a gate insulating pattern and a semiconductor pattern on the first pattern except the pixel electrode by using a second mask process; Forming a third pattern including a data line, a source electrode, a drain electrode, and a storage electrode using a third mask process; And forming a passivation layer over the pad area and the array area in front of the liquid crystal display panel. The method of claim 8, Exposing the pad And removing the passivation layer from the pad area. The method of claim 6, The etchant comprises H ₂ O (water) and HF (fluoric acid) in a ratio of about 20: 1.

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