KR100560947B1 - Generating circuit for input signal of a pipe register - Google Patents

Abstract

The present invention relates to a pipe register input signal generating circuit, comprising: first logic means for inputting first and second control signals having bank information, and a first delay portion for delaying an output signal of the first logic means. A second logic means for inputting an output signal of the first logic means and an output signal of the first delay portion, a latch for outputting a pipe register input signal set by an output signal of the second logic means; A second delay unit for delaying the output signal of the latch, a third delay unit for delaying the output signal of the second delay unit, an output signal of the second delay unit and an output signal of the third delay unit; And third logic means for outputting a reset signal for resetting the latch, thereby preventing malfunction of the memory due to global loading. A pipe register input signal generation circuit is presented.

DDR, pipe resistors, global loading, delay, S / R latch, self pulse

Description

Generating circuit for input signal of a pipe register             

1 is a conventional pipe register input signal generation circuit diagram.

Fig. 2 is a waveform diagram in normal operation of a conventional pipe register input signal generation circuit.

Fig. 3 is a waveform diagram of a conventional pipe resistor input signal generation circuit in bad operation.

4 is a circuit register input signal generation circuit diagram according to the present invention;

5 is an operational waveform diagram of a pipe register input signal generation circuit according to the present invention;

<Explanation of symbols for the main parts of the drawings>

21, 24, 25, 26 and 31: NAND gates 22, 28 and 29: delay

23, 30, 32, and 33: Inverter 27: S / R latch

34: pipe register

The present invention relates to a pipe register input signal generating circuit, and more particularly, to a pipe register input signal generating circuit capable of preventing a malfunction of a memory device due to global loading.

In order to read a pipe register as an output control unit of the DDR memory device, an input signal is generated using a main amplifier control signal having bank information, and the pipe register is driven to output a predetermined signal. That is, the input signal generation circuit of the pipe resistor inputs a control signal having bank information simultaneously with the main amplifier to generate a signal. However, due to the high integration of the semiconductor devices and the increase in chip size (gigabit memory), the global loading of the control signal increases and becomes abnormal, which may cause a defect in the memory chip.

1 is a circuit diagram of a conventional pipe register input signal generator, the configuration of which is as follows.

The first NAND gate 11 has bank information, and inputs and logically combines control signals YMAEB_01 and YMAEB_23 for generating a pipe register input signal while controlling the main amplifier. The first inverter 12 inverts the output signal of the first NAND gate 11, and the output signal a of the first inverter 12 is input to one input terminal of the second NAND gate 14. The output signal of the first inverter 12 is delayed for a predetermined time through the delay unit 13 and input to the other input terminal of the second NAND gate 14. The output signal of the second NAND gate 14 becomes the pipe register 17 input signal PINSUMBT through the second and third inverters 15 and 16, and the pipe register 17 has a predetermined signal PINB <0. : 2>)

The normal driving method of the conventional pipe register input signal generation circuit configured as described above will be described with reference to FIG.

The control signals YMAEB_01 and YMAEB_23 which are generated during a read operation and have bank information and control the main amplifier and simultaneously generate a pipe register input signal are input to the first NAND gate 11 and are logically combined. The output signal of the first NAND gate 11 is inverted by the first inverter 12 and input to one input terminal of the second NAND gate 14. The output signal of the first NAND gate 11 inverted through the first inverter 12 is delayed through the delay unit 13 and input to the other input terminal of the second NAND gate 14. At this time, the output signal a of the first inverter 12 and the output signal b of the delay unit 13 have phases that differ by the delay time of the delay unit 13. The output signals of the second NAND gate 14 which inputs and logically combines the output signal a of the first inverter 12 and the output signal b of the delay unit 13 are second and third inverters 15 and. 16) to become an input signal (PINSUMBT) of the pipe register. The pipe register 17 outputs a predetermined output signal PINB <0: 2> in accordance with the input signal PINSUMBT.

However, as the memory device is highly integrated and the size of the memory chip is increased, the control signal YMAEB controlled by the bank away from the pipe register may decrease its pulse width by increasing global loading. . When this reduced pulse width control signal YMAEB passes through the pipe register input signal generating circuit, a short pulse may cause the pipe register input signal PINSUMBT to become abnormal. This causes the pipe register to malfunction and cause a failure in the read operation of the memory device. The waveform diagram at the time of the poor operation by such a short pulse input is shown in FIG. As shown in the drawing, as the control signal YMAEB is shortened, especially when the pulse width of the control signal YMAEB becomes shorter than the delay time of the delay unit 13, the pipe register input signal PINSUMBT is abnormally output. This causes the pipe register to malfunction.

As described above, the conventional pipe resistor input signal generation circuit simultaneously uses the control signal YMAEB as the control signal of the main amplifier and the pipe resistor, thereby limiting the pulse width of the control signal YMAEB due to the limitation of tCK, an AC specification of the memory device. Since the control signal YMAEB is directly used as the input signal of the pipe register, the pipe register may be malfunctioned.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pipe register input signal generating circuit which can prevent the malfunction of a pipe register due to an increase in global loading.

Another object of the present invention is to use the control signal by increasing the pulse width of the control signal by using a driver different from the main amplifier, and increasing the global loading by generating the final pipe resistor input signal with self-pulsing using the falling edge of the control signal. To provide a pipe register input signal generating circuit that can prevent the malfunction of the pipe register by the source.

The pipe register input signal generation circuit according to the present invention includes a first signal generator for inputting first and second control signals having bank information to generate a set signal having a variable pulse width, and a pipe register according to the set signal. A second signal generating unit for generating an input signal, an adjusting unit for adjusting a pulse width of the pipe register input signal, and an output signal of the adjusting unit to generate a reset signal having a variable pulse width to generate the second signal; And a third signal generator for resetting the signal generator.

The first signal generator includes a first NAND gate for inputting the first and second control signals, a first delay unit for delaying an output signal of the first NAND gate, and an output signal of the first NAND gate. And a second NAND gate for inputting an output signal of the first delay unit.

The second signal generator includes a latch set according to the set signal to output a pipe register input signal and reset according to the reset signal.

The adjuster includes a delay circuit for adjusting a pulse width by delaying the pipe register input signal.

The third signal generator includes a delay unit for delaying an output signal of the controller and a third NAND gate for inputting an output signal of the controller and an output signal of the delay unit to generate a reset signal.

On the other hand, the pipe register input signal generation circuit according to the present invention includes first logic means for inputting first and second control signals having bank information, and a first delay portion for delaying an output signal of the first logic means. A second logic means for inputting an output signal of the first logic means and an output signal of the first delay portion, a latch for outputting a pipe register input signal set by an output signal of the second logic means; A second delay unit for delaying the output signal of the latch, a third delay unit for delaying the output signal of the second delay unit, an output signal of the second delay unit and an output signal of the third delay unit; Third logic means for outputting a reset signal for resetting the latch.

The control signal has bank information and is a signal separated from the main amplifier control signal.

The first to third logic means are respectively NAND gates.

Delay times of the first and third delay units are shorter than delay times of the second delay units.

The set signal has a pulse width determined by a delay time of the first delay unit, the pipe register input signal has a pulse width determined by a delay time of the second delay unit, and the reset signal is a delay of the third delay unit. The pulse width is determined by time.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

4 is a configuration diagram of a pipe register input signal generation circuit according to the present invention.

The first NAND gate 21 inputs and combines the control signals YMAEB_01p and YMAEB_23p separated from the control signal of the main amplifier. The first delay unit 22 delays the output signal a of the first NAND gate 21, and the first inverter 23 inverts the output signal of the first delay unit 22. The second NAND gate 24 inputs and logically combines the output signal a of the first NAND gate 21 and the output signal b of the first inverter 23. The output signal set of the second NAND gate 24 is used as a set signal for setting the S / R latch 27 composed of the third and fourth NAND gates 25 and 26. Meanwhile, the third NAND gate 25 constituting the S / R latch 27 inputs an output signal set of the second NAND gate 24 and an output signal of the fourth NAND gate 26, and receives a fourth signal. The NAND gate 26 inputs an output signal of the third NAND gate 25 and an output signal reset of the fifth NAND gate 31. The second delay unit 28 delays the output signal out of the S / R latch 27. The third delay unit 29 delays the output signal of the second delay unit 28, and the second inverter 30 inverts the output signal of the third delay unit 29. The fifth NAND gate 31 receives and logically combines the output signal c of the second delay unit 28 and the output signal d of the second inverter 30. The output signal reset of the fifth NAND gate 31 is used as a reset signal for resetting the S / R latch 27. The output signal out of the S / R latch 27 becomes the input signal PINSUMBT of the pipe register via the third and fourth inverters 32 and 33, and the pipe register 34 is connected to the input signal PINSUMBT. Therefore, the output signal PINB <0: 2> is output.

On the other hand, the delay time of the first and third delay units 22 and 29 has a delay time shorter than the delay time of the second delay unit 28. In addition, the delay time of the second delay unit 28 is adjusted by a control signal in the test mode or by connecting a plurality of fuses to the second delay unit 28 and cutting the fuses.

In the above, the separation of the control signals YMAEB_01p and YMAEB_23p from the main amplifier control signal means that for example, even if the main amplifier control signal has a predetermined pulse, it has bank information without having such a predetermined pulse. . That is, conventionally, the same signal as the main amplifier control signal is used as the control signal of the pipe resistor input signal generation circuit, but the same signal is not used in the present invention.

The driving method of the pipe register input signal generation circuit according to the present invention configured as described above will be described with reference to the waveform diagram of FIG. 5.

The control signals YMAEB_01p and YMAEB_23p, which may have pulses of sufficient width because they are controlled separately from the control signals of the main amplifier, are input to the first NAND gate 21, and the first NAND gate 21 logically combines them. . The output signal of the first NAND gate 21 is delayed through the first delay unit 22 and then inverted through the first inverter 23. The output signal a of the first NAND gate 21 and the output signal b of the first inverter 23 are input to the second NAND gate 24, and the second NAND gate 24 is a logical combination thereof. Output a set signal (set). Here, the output signal b of the first inverter 23 is a signal which is delayed by the delay time by the first delay unit 22 and is in phase opposite to the output signal a of the first NAND gate 21. . Therefore, when the output signal a of the first NAND gate 21 is at a high level and the output signal b of the first inverter 23 is at a high level, the second NAND gate 24 is a set signal having a low state. Output (set) That is, the set signal is delayed during the delay time of the first delay unit 22 after the output signal a of the first NAND gate 21 transitions to a high level, and the first inverter 23 having a reversed phase. The low level is maintained while the output signal (b) of the N) is at the high level, and the set signal is maintained at the low level at the falling edge at which the output signal of the first inverter 23 transitions to the low level. The S / R latch 27 is set by the low level set signal set to output the high level output signal out. The output signal out of the high level S / R latch 27 becomes a pipe register input signal PINSUMBT via the third and fourth inverters 32 and 33, and is input to the pipe register 34, and 34 outputs a predetermined output signal PINB <0: 2>.

The output signal out of the S / R latch 27 is delayed by the second delay unit 28 and then input to one input terminal of the fifth NAND gate 31. In addition, the output signal of the second delay unit 28 is delayed by the third delay unit 29 and then inverted by the second inverter 30 and input to the other input terminal of the fourth NAND gate 31. Here, the output signal d of the second inverter 30 is a signal which is delayed by the delay time by the third delay unit 29 and is out of phase compared to the output signal c of the second delay unit 28. . Therefore, when the output signal c of the second delay unit 28 is at a high level and the output signal d of the second inverter 30 is at a high level, the fifth NAND gate 31 is a reset signal having a low state. Output (reset) That is, the reset signal reset is delayed during the delay time of the third delay unit 29 after the output signal c of the second delay unit 28 transitions to a high level, and the second inverter 30 having a reversed phase. Maintains a low level while the output signal (d) of the < RTI ID = 0.0 >) &lt; / RTI &gt; is at a high level, and the reset signal reset at the falling edge at which the output signal d of the second inverter 30 transitions to a low level. do. The S / R latch 27 is reset by the low level reset signal to output the low level output signal out. The S / R latch 27 is reset by the low level reset signal to output the low level output signal out. The output signal out of the low level S / R latch 27 becomes the pipe register input signal PINSUMBT via the third and fourth inverters 32 and 33 and is input to the pipe register 34, and 34 outputs a predetermined output signal PINB <0: 2>.

The output signal out of the S / R latch 27 is maintained at a high level while the reset signal reset is input to the low level after the set signal is input to the low level. That is, when the set signal set is input at the low level, the signal transitions to the high level, and when the next reset signal reset is input at the low level, the signal transitions to the low level. On the other hand, the output signal (out) of the S / R latch 27 is affected by the delay time of the second delay unit 28, the set signal (set) affects the delay time of the first delay unit 22. The reset signal reset is affected by the delay time of the third delay unit 29.

As described above, according to the present invention, by separating the control signal of the pipe register input signal generating circuit from the main amplifier control signal, the pulse width of the control signal can be controlled to be wide enough, and the self pulse using the S / R latch is generated This prevents shortening of the control signal due to increased global loading, thereby preventing the pipe resistors from malfunctioning. In addition, tCK can be optimized by controlling the delay time of the pipe register input signal generation circuit. Thus, yield loss can be minimized in future high density and gigabit memory device designs.

Claims (11)

A first signal generator for inputting first and second control signals having bank information to generate a set signal having a variable pulse width; A second signal generator for generating a pipe register input signal according to the set signal; An adjusting unit for adjusting a pulse width of the pipe register input signal; And And a third signal generator for inputting an output signal of the controller to generate a reset signal having a variable pulse width to reset the second signal generator. The display apparatus of claim 1, wherein the first signal generator comprises: a first NAND gate for inputting the first and second control signals; A first delay unit for delaying an output signal of the first NAND gate; And And a second NAND gate for inputting an output signal of the first NAND gate and an output signal of the first delay unit. The pipe register input signal generation circuit of claim 1, wherein the second signal generator comprises a latch set according to the set signal to output a pipe register input signal and reset according to the reset signal. The pipe register input signal generating circuit of claim 1, wherein the control unit comprises a delay circuit for adjusting a pulse width by delaying the pipe register input signal. The apparatus of claim 1, wherein the third signal generator comprises: a delay unit for delaying an output signal of the control unit; And And a third NAND gate for inputting an output signal of the control unit and an output signal of the delay unit to generate a reset signal. First logic means for inputting first and second control signals; A first delay section for delaying the output signal of the first logic means; Second logic means for inputting an output signal of the first logic means and an output signal of the first delay portion; A latch set by an output signal of the second logic means to output a pipe register input signal; A second delay unit for delaying an output signal of the latch; A third delay unit for delaying the output signal of the second delay unit; And And third logic means for inputting an output signal of the second delay section and an output signal of the third delay section to output a reset signal for resetting the latch. 7. The pipe register input signal generation circuit according to claim 6, wherein said first to third logic means each comprise a NAND gate. The pipe register input signal generation circuit of claim 6, wherein a delay time of the first and third delay units is shorter than a delay time of the second delay unit. The pulse width of the set signal is determined by the delay time of the first delay unit, the pipe register input signal is determined by the delay time of the second delay unit, and the reset signal is And a pulse width is determined by a delay time of the third delay unit. 7. The pipe register input signal generation circuit according to claim 6, wherein the second delay section is adjusted with a delay time by a control signal in a test mode. The pipe register input signal generating circuit of claim 6, wherein the second delay unit is connected to a plurality of fuses and the delay time is adjusted by cutting the fuse.

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