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KR100569509B1 - Method for fabricating of semiconductor device - Google Patents

Method for fabricating of semiconductor device Download PDF

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Publication number
KR100569509B1
KR100569509B1 KR1020020086788A KR20020086788A KR100569509B1 KR 100569509 B1 KR100569509 B1 KR 100569509B1 KR 1020020086788 A KR1020020086788 A KR 1020020086788A KR 20020086788 A KR20020086788 A KR 20020086788A KR 100569509 B1 KR100569509 B1 KR 100569509B1
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oxide film
nitride film
film
pad
semiconductor device
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KR1020020086788A
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Korean (ko)
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KR20040060245A (en
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안광호
이병철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로서, 선형 질화막을 사용하는 STI 공정에서 패드질화막 제거 후에 희생산화막의 형성 및 전면 식각 방법으로 선형 질화막을 노출되지 않도록한 후, 게이트산화막 형성 및 게이트전극 형성 공정을 실시하여 모트에 의한 식각 잔류물 생성이 방지되어 배선의 단락이 예방되므로, 공정수율 및 소자의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, wherein after a pad nitride is removed in a STI process using a linear nitride film, a gate oxide film is formed and a gate electrode is formed after the sacrificial oxide film is removed and the linear nitride film is not exposed by the entire etching method. By preventing the formation of etch residue by the mote to prevent the short circuit of the wiring, it is possible to improve the process yield and the reliability of the device.

Description

반도체소자의 제조방법{METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE} Manufacturing method of semiconductor device {METHOD FOR FABRICATING OF SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래 기술에 따른 반도체소자의 제조공정도.1A and 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2는 도 1b의 일부 단면 확대도. 2 is an enlarged view of a partial cross section of FIG. 1B;

도 3은 도 2의 반도체기판에 게이트산화막을 형성한 상태의 단면도. 3 is a cross-sectional view of a gate oxide film formed on a semiconductor substrate of FIG. 2.

도 4는 도 3에서 게이트전극을 형성한 상태의 단면도.4 is a cross-sectional view of a state in which a gate electrode is formed in FIG. 3.

도 5a 내지 도 5e는 본 발명에 따른 반도체소자의 제조공정도.5a to 5e is a manufacturing process diagram of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10,40 : 반도체기판 12,41 : 패드산화막10,40: semiconductor substrate 12,41: pad oxide film

14 : 패드질화막 16,42 : 트랜치 14: pad nitride film 16, 42: trench

18,44 : 웰 산화막 20,46 : 선형 질화막18,44: well oxide film 20,46: linear nitride film

22,48 : 필드산화막 24,50 : 골22,48: field oxide film 24,50: bone

26,54 : 게이트산화막 28 : 모트 26,54 gate oxide film 28 mort

30,56 : 게이트전극 32 : 식각 잔류물30,56 gate electrode 32 etching residue

52 : 희생산화막 52: sacrificial oxide film

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 선형 질화막을 사용하는 고밀도 소자의 얕은 트랜치 소자분리(shallow trench isolation; 이하 STI라 칭함) 공정에서의 모트(moat)에서의 잔류물에 의한 단락을 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a short circuit caused by residues in a moat during a shallow trench isolation (STI) process of a high density device using a linear nitride film. It relates to a method for manufacturing a semiconductor device that can prevent the process yield and improve the reliability of the device.

일반적으로 반도체소자는 소자가 형성되는 활성영역과, 이들을 분리하는 소자분리 영역으로 구분할 수 있으며, 소자분리영역이 소자의 전체 면적에서 차지하는 비율이 크므로 소자의 고집적화를 위해서는 소자분리영역의 축소가 필요하다. In general, semiconductor devices can be divided into active regions in which devices are formed and device isolation regions separating them, and since the device isolation region occupies a large portion of the entire area of the device, it is necessary to reduce the device isolation region for high integration. Do.

고집적 소자에서는 기판에 얕은 트랜치를 형성하고 이를 절연막으로 메우는 STI 방법이 많이 사용되고 있다. In high-integration devices, STI methods that form shallow trenches in a substrate and fill them with insulating films are widely used.

도 1a 및 도 1b는 종래 기술에 따른 반도체소자의 제조 공정도이다.1A and 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

먼저, 반도체기판(10)상에 패드산화막(12)과 패드질화막(14)을 순차적으로 형성하고, 소자분리 마스크(도시되지 않음)를 이용한 사진식각 공정으로 상기 패드질화막(14)과 패드산화막(12)을 식각하여 패드질화막(14) 패턴과 패드산화막(12) 패턴을 형성한다. First, the pad oxide layer 12 and the pad nitride layer 14 are sequentially formed on the semiconductor substrate 10, and the pad nitride layer 14 and the pad oxide layer 14 are formed by a photolithography process using an element isolation mask (not shown). 12) is etched to form a pad nitride film 14 pattern and a pad oxide film 12 pattern.

그다음 상기 패드질화막(14) 패턴에 의해 노출되어있는 반도체기판(10)을 일정 깊이 식각하여 트랜치(16)를 형성하고, 상기 트랜치(16)의 내벽에 웰 산화막(18)을 형성한 후, 상기 구조의 전표면에 선형 질화막(20)을 형성한다. (도 1a 참조). Then, the semiconductor substrate 10 exposed by the pad nitride layer 14 pattern is etched to a predetermined depth to form a trench 16, and a well oxide layer 18 is formed on an inner wall of the trench 16. The linear nitride film 20 is formed on the entire surface of the structure. (See FIG. 1A).

그 후, 상기 구조의 전표면에 필드산화막(22)을 도포하고, 평탄화시키고, 상기 패드질화막(14)과 패드산화막(12)을 제거하여 트랜치를 메운 필드 산화막(22)과 선형 질화막(20) 패턴으로 구성되는 소자분리영역을 형성한다. (도 1b 참조).Thereafter, the field oxide film 22 is applied to the entire surface of the structure, planarized, and the pad nitride film 14 and the pad oxide film 12 are removed to fill the trench, and the field oxide film 22 and the linear nitride film 20 are filled. An isolation region is formed of a pattern. (See FIG. 1B).

도 2는 도 1b의 소자분리영역 에지 부분의 확대 도면으로서, 상기 패드질화막(14) 제거 공정시 선형 질화막(20)도 함께 제거되어 필드산화막(22)의 에지 부분에 깊은 골(24)이 생긴다. FIG. 2 is an enlarged view of an edge portion of the device isolation region of FIG. 1B, in which the linear nitride film 20 is also removed during the pad nitride film 14 removal process, resulting in a deep valley 24 at the edge portion of the field oxide film 22. .

도 3은 도 2의 반도체기판(10)상에 게이트산화막(26)을 형성한 상태의 단면도로서, 크린닝 공정에서 필드산화막(22)과 평탄화 공정시 인접한 선형 질화막(20)과 웰 산화막(18) 간의 식각 선택비 차이로 인하여 선형 질화막(20)의 양측으로 모트(28)가 발생된다. FIG. 3 is a cross-sectional view of the gate oxide film 26 formed on the semiconductor substrate 10 of FIG. 2. The linear nitride film 20 and the well oxide film 18 adjacent to each other during the planarization process with the field oxide film 22 in the cleaning process are shown. Due to the difference in the etching selectivity between the mott 28 is generated on both sides of the linear nitride film (20).

도 4은 도 3의 게이트산화막(26) 상에 게이트전극(30)을 형성한 상태의 상태도로서, 상기 모트 부분에 게이트전극 물질의 식각 잔류물(32)이 남아 있다. FIG. 4 is a state diagram in which the gate electrode 30 is formed on the gate oxide layer 26 of FIG. 3, and the etch residue 32 of the gate electrode material remains on the mote portion.

상기와 같은 종래 기술에 따른 반도체 소자의 제조방법은 고집적 소자에 사용되는 선형 질화막을 이용한 STI 공정에서 산화막과 질화막과의 식각선택비차이로 인하여 필드산화막 평탄화 공정시 선형 질화막의 양측으로 모트가 발생하고 상기 모트는 후속 게이트전극 패턴닝 공정시 식각 잔류물이 남는 자리를 제공하여 게이트전극의 원활한 패턴닝을 방해하고, 라인의 단락을 유발하여 공정수율 및 소자의 신뢰성을 떨어뜨리는 문제점이 있다. In the method of manufacturing a semiconductor device according to the prior art as described above, in the STI process using the linear nitride film used for the highly integrated device, the mott is generated on both sides of the linear nitride film during the field oxide planarization process due to the difference in etching selectivity between the oxide film and the nitride film. The mortity provides a place where the etching residue remains in the subsequent gate electrode patterning process, which hinders the smooth patterning of the gate electrode, and causes a short circuit to reduce process yield and device reliability.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 선형 질화막을 이용하는 STI 공정에서 선형 질화막의 트랜치 에지측 높이를 트랜치 보다 낮게 형성하여 선형 질화막에 의한 트랜치 에지에서의 모트 발생을 방지하여 모트에 의한 후속 식각 공정에서의 식각잔류물 발생을 방지하여 라인 단락의 원을 제거하여 공정수율 및 소자의 신뢰성을 향상시킬수 있는 반도체소자의 제조방법을 제공함에 있다. The present invention is to solve the above problems, an object of the present invention is to form a trench edge side height of the linear nitride film lower than the trench in the STI process using a linear nitride film to prevent the occurrence of mort in the trench edge by the linear nitride film The present invention provides a method for manufacturing a semiconductor device capable of improving process yield and device reliability by preventing the occurrence of etch residues in a subsequent etching process by a mote to remove circles of line short circuits.

본발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본발명에 따른 반도체소자 제조방법의 특징은, The present invention is to achieve the above object, the characteristics of the semiconductor device manufacturing method according to the present invention,

선형 질화막을 사용하는 STI 방법의 반도체소자의 제조방법에 있어서, In the semiconductor device manufacturing method of the STI method using a linear nitride film,

반도체기판상에 패드산화막과 패드질화막을 순차적으로 형성하는 공정과, Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate;

상기 패드질화막과 패드산화막을 소자분리마스크를 이용한 패턴닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과, Selectively etching the pad nitride film and the pad oxide film by a patterning process using a device isolation mask to form a pad nitride film pattern exposing a predetermined portion of the semiconductor substrate as a device isolation region;

상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트랜치를 형성하는 공정과, Etching the semiconductor substrate exposed by the pad nitride layer to form a trench by a predetermined thickness;

상기 트랜치의 내벽이 웰 산화막을 형성하는 공정과, Forming a well oxide film on an inner wall of the trench;

상기 구조의 전표면에 선형 질화막을 형성하는 공정과, Forming a linear nitride film on the entire surface of the structure;

상기 구조의 전표면에 필드산화막을 형성하는 공정과, Forming a field oxide film on the entire surface of the structure;

상기 필드산화막을 평탄화시켜 상기 선형 질화막이 트랜치 내부에만 남도록하고 필드산화막을 분리시키는 공정과, Planarizing the field oxide film so that the linear nitride film remains only inside the trench and separating the field oxide film;

상기 패드질화막 패턴을 제거하는 공정과, Removing the pad nitride film pattern;

상기 구조의 전표면에 희생산화막을 형성하는 공정과, Forming a sacrificial oxide film on the entire surface of the structure;

상기 희생산화막을 전면 제거하는 공정을 구비함에 있다. And removing the entire surface of the sacrificial oxide film.

본 발명의 다른 특징은, 상기 선형 질화막의 에지는 반도체기판 표면 보다 10∼1000Å 낮게 형성되며, 선형 질화막의 두께는 10∼500Å 으로 형성하고, 상기 희생산화막을 고온산화나 LP-TEOS막으로 형성하는 것을 특징으로 한다. According to another aspect of the present invention, the edge of the linear nitride film is formed to be 10 to 1000 mW lower than the surface of the semiconductor substrate, the thickness of the linear nitride film is 10 to 500 mW, and the sacrificial oxide film is formed of high temperature oxidation or LP-TEOS film. It is characterized by.

이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명하면 다음과 같다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 5a 내지 도 5e는 본 발명에 따른 반도체소자의 제조공정도이다. 5A to 5E are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 도 2의 단계와 마찬가지로 선형 질화막를 이용한 STI 공정을 진행하면, 실리콘 웨이퍼등의 반도체기판(40)상에 형성된 소정 깊이의 트랜치(42)와, 상기 트랜치(42)의 내벽에 형성되어있는 웰 산화막(44)과, 상기 웰 산화막(44)상에 형성되어있는 선형 질화막(46) 패턴과, 상기 트랜치(42)를 메우는 필드산화막(48)과, 상기 반도체기판(40)상에 형성되어있는 패드산화막(41)을 구비하여 소자분리를 완료한다. 이때 상기 필드산화막(48)의 에지 부분에 깊은 골(50)이 형성되어 있으며, 상기 선형 질화막(46)의 에지는 반도체기판(40) 표면 보다 10∼1000Å 낮게 형성되며, 선형 질화막(46)의 두께는 10∼500Å 정도이다. (도 5a 참조). First, as in the step of FIG. 2, when the STI process using the linear nitride film is performed, the trench 42 having a predetermined depth formed on the semiconductor substrate 40 such as a silicon wafer and the well formed on the inner wall of the trench 42 are formed. The oxide film 44, the linear nitride film 46 pattern formed on the well oxide film 44, the field oxide film 48 filling the trench 42, and the semiconductor substrate 40 are formed. A pad oxide film 41 is provided to complete device isolation. At this time, the deep valley 50 is formed at the edge portion of the field oxide film 48, the edge of the linear nitride film 46 is formed 10 ~ 1000Å lower than the surface of the semiconductor substrate 40, the linear nitride film 46 The thickness is about 10-500 GPa. (See FIG. 5A).

그다음 상기 구조의 전표면에 희생산화막(52)을 고온산화나 LP-TEOS막으로 도포한다. 이때 상기 희생산화막(52)은 상기 골(50)을 완전히 메운다. (도 5b 참조). Then, the sacrificial oxide film 52 is applied to the entire surface of the structure by high temperature oxidation or LP-TEOS film. At this time, the sacrificial oxide film 52 completely fills the bone 50. (See FIG. 5B).

그후, 상기 희생산화막(52)을 건식 또는 습식식각 방법으로 전면식각하여 그 두께 만큼을 제거한다. 이때 상기 골(50)을 메운 부분은 제거되지 않는다. (도 5c 참조). Thereafter, the sacrificial oxide film 52 is entirely etched by a dry or wet etching method to remove the thickness thereof. At this time, the portion filling the bone 50 is not removed. (See FIG. 5C).

그다음 상기 패드산화막(41)을 제거하고, 반도체기판(40)상에 게이트산화막(54)을 형성한다. 이때의 클리닝 공정에서도 선형 질화막(46)이 노출되지 않아 모트가 생기지 않는다. (도 5d 참조).Then, the pad oxide film 41 is removed, and the gate oxide film 54 is formed on the semiconductor substrate 40. At this time, even in the cleaning process, the linear nitride film 46 is not exposed and no mort is generated. (See FIG. 5D).

그후 상기 게이트산화막(54)상에 게이트전극(56)을 형성한다. 여기서 모트가 없으므로 식각 잔류물로 남지 않는다(도 5e 참조). Thereafter, a gate electrode 56 is formed on the gate oxide film 54. There is no moat here so it does not remain as an etch residue (see FIG. 5E).

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은, 선형 질화막을 사용하는 STI 공정에서 패드질화막 제거 후에 희생산화막의 형성 및 전면 식각 방법으로 선형 질화막을 노출되지 않도록한 후, 게이트산화막 형성 및 게이트전극 형성 공정을 실시하여 모트에 의한 식각 잔류물 생성이 방지되어 배선의 단락이 예방되므로, 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, after the pad nitride film is removed in the STI process using the linear nitride film, the sacrificial oxide film is formed and the gate nitride film is formed after the linear nitride film is not exposed by the entire etching method. And since the gate electrode forming process is performed to prevent the formation of etch residues by the mott to prevent the short circuit of the wiring, there is an advantage that can improve the process yield and the reliability of the device.

Claims (3)

선형 질화막을 사용하는 STI 방법의 반도체소자의 제조방법에 있어서, In the semiconductor device manufacturing method of the STI method using a linear nitride film, 반도체기판상에 패드산화막과 패드질화막을 순차적으로 형성하는 공정과, Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드질화막과 패드산화막을 소자분리마스크를 이용한 패턴닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과, Selectively etching the pad nitride film and the pad oxide film by a patterning process using a device isolation mask to form a pad nitride film pattern exposing a predetermined portion of the semiconductor substrate as a device isolation region; 상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트랜치를 형성하는 공정과, Etching the semiconductor substrate exposed by the pad nitride layer to form a trench by a predetermined thickness; 상기 트랜치의 내벽이 웰 산화막을 형성하는 공정과, Forming a well oxide film on an inner wall of the trench; 상기 구조의 전표면에 선형 질화막을 형성하는 공정과, Forming a linear nitride film on the entire surface of the structure; 상기 구조의 전표면에 필드산화막을 형성하는 공정과, Forming a field oxide film on the entire surface of the structure; 상기 필드산화막을 평탄화시켜 상기 선형 질화막이 트랜치 내부에만 남도록하고 필드산화막을 분리시키는 공정과, Planarizing the field oxide film so that the linear nitride film remains only inside the trench and separating the field oxide film; 상기 패드질화막 패턴을 제거하는 공정과, Removing the pad nitride film pattern; 상기 구조의 전표면에 희생산화막을 형성하는 공정과, Forming a sacrificial oxide film on the entire surface of the structure; 상기 희생산화막을 전면 제거하는 공정을 구비하는 반도체소자의 제조방법. And removing the entire sacrificial oxide film. 제 1 항에 있어서,The method of claim 1, 상기 선형 질화막의 에지는 반도체기판 표면 보다 10∼1000Å 낮게 형성되 며, 선형 질화막의 두께는 10∼500Å 으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법. The edge of the linear nitride film is formed 10 to 1000 kHz lower than the surface of the semiconductor substrate, the method of manufacturing a semiconductor device, characterized in that the thickness of the linear nitride film is formed to 10 ~ 500Å. 제 1 항에 있어서,The method of claim 1, 상기 희생산화막을 고온산화나 LP-TEOS막으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.A method of manufacturing a semiconductor device, wherein the sacrificial oxide film is formed of a high temperature oxidation or LP-TEOS film.
KR1020020086788A 2002-12-30 2002-12-30 Method for fabricating of semiconductor device KR100569509B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990061066A (en) * 1997-12-31 1999-07-26 김영환 Method of forming device isolation film of semiconductor device
KR20010058937A (en) * 1999-12-30 2001-07-06 박종섭 Input pads of a semiconductor device
KR20020058517A (en) * 2000-12-30 2002-07-12 박종섭 Method for fabricating trench isolation film of semiconductor device
KR20020086914A (en) * 2000-03-02 2002-11-20 세키스이가가쿠 고교가부시키가이샤 Interlayer film for laminated glass and laminated glass

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990061066A (en) * 1997-12-31 1999-07-26 김영환 Method of forming device isolation film of semiconductor device
KR20010058937A (en) * 1999-12-30 2001-07-06 박종섭 Input pads of a semiconductor device
KR20020086914A (en) * 2000-03-02 2002-11-20 세키스이가가쿠 고교가부시키가이샤 Interlayer film for laminated glass and laminated glass
KR20020058517A (en) * 2000-12-30 2002-07-12 박종섭 Method for fabricating trench isolation film of semiconductor device

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