KR100565714B1 - Apparatus for video decoding and method for the same - Google Patents

Abstract

The present invention relates to a video decoding apparatus and method. In particular, an HD-level input format of SDTV, which requires a large amount of data processing speed and speed, can be down-converted by horizontal low pass filtering to perform inverse quantization independent of video display resolution. In addition, by maintaining a constant data transmission rate by elastic double buffering for the down-converted HD-class DCT coefficients, it is possible to implement an ASIC capable of stable operation at a constant speed regardless of the video input format. By storing the dequantized DCT coefficients in the coefficient buffer and using the position information of the coefficients sent from the VLD, the DCT coefficients are written one by one, and when reading, a plurality of DCT coefficients are read at the same time to output serial data in parallel. In addition, the clock speed can be lowered, thus reducing the burden on the hardware.

Description

Apparatus for video decoding and method for the same}

TECHNICAL FIELD The present invention relates to digital television (TV), and more particularly, to a video decoding apparatus and method for decoding a compressed transmitted video signal.

In general, digital TV broadcasting is currently being piloted in North America, and our country will soon enter the era of full-scale digital broadcasting through trial broadcasting. Thus, by the early 21st century, current analog broadcasting will be replaced by digital broadcasting.

Currently, digital broadcasting standards include North American and European standards, and North American standards follow the specifications of the Advanced Television Systems Committee (ATSC). The digital TV proposed by ATSC includes HDTV (High definition TV) and SDTV (Standard definition TV), and the video decoder of such digital TV is based on Moving Picture Experts Group (MPEG-2).

Here, the SDTV plays a role of a transitional TV receiver from the conventional analog TV to the HDTV, and has a structure capable of decoding the input format of all digital TVs as well as the decoding of the NTSC signal.

At this time, the video input formats of SDTV are largely 1920 × 1080, 1280 × 720, 704 × 480, 640 × 480. Among these, 1920 × 1080, 1280 × 720 are regarded as HD class input formats, and 704 × 480, 640 × 480 is considered as SD input format.

FIG. 1 is a block diagram illustrating a video decoder in a general digital TV. The video bitstream transmitted from an encoder is variable-length decoded by a variable length decoder (VLD) 101 so that motion vector, quantization value, and quantization are decoded. The quantization value and the DCT coefficient are output to the inverse quantizer (IQ) unit 102, and the motion vector is output to the motion compensator 104.

At this time, in the VLD 101, as an example, DCT coefficients are decoded at a run-level. That is, one DCT block is composed of 8x8 coefficients, and only non-zero coefficients are included in the code, so the output of the VLD 101 has a magnitude between non-zero coefficients, that is, a level between the coefficients and these coefficients. This prints out how many runs are inserted.

For example, if the first of the 64 coefficients is 10, the fourth coefficient is 3, and the second and third coefficients are 0, the run and level are (0, 10) and (2, 3), respectively.

Accordingly, the IQ unit 102 receives a run-level pair and converts the run-level pairs into 64 DCT coefficients, where the DCT coefficients are zig-zag scan at the transmitting side to increase the efficiency of the run-level code. Alternatively, since it is quantized by an alternate scan method, an inverse scan (IS) that simultaneously converts them into a raster scan method is performed. Then, the 64 DCT coefficients which are inversely scanned and output are inversely quantized according to the quantization value output from the VLD 101 and output to the inverse discrete cosine transform (IDCT) unit 103.

The IDCT unit 103 performs IDCT on the inverse quantized DCT coefficients and outputs them to the adder 105, and the adder 105 adds motion compensated data to the IDCT image signal and reconstructs the complete image. Output for At the same time, the output of the adder 105 is stored in the frame memory 106, and the motion compensator 104 uses the data stored in the frame memory 106 for the P and B pictures as a reference frame and the VLD 101 After motion estimation and motion compensation are performed using the motion vector separated from, the output is added to the adder 105.

However, the above-described general video decoder of FIG. 1 is suitable for processing data of an SD class input format, but is not suitable for processing data of an HD class input format due to insufficient processing speed.

In other words, in order to display the data of the HD input format on the SDTV, the amount of data is increased than the SD level, so the size of the memory used and the data transfer speed must be faster. This results in clock frequencies that are so high that lack of decoding time makes it nearly impossible to decode an HD input format.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a video decoding apparatus suitable for various input formats of SDTV by performing down conversion upon inverse quantization of input DCT coefficients when the input format is HD. In providing a method.

Another object of the present invention is to provide a video decoding apparatus and method for maintaining a constant data transmission rate output through IDCT regardless of an input format.

In accordance with an aspect of the present invention, a video decoding apparatus includes a VLD for decoding and output codes corresponding to DCT coefficients of an input video bitstream, and an input format for inverse quantization of DCT coefficients decoded in the VLD. A dequantizer for down-conversion according to the first and second buffers, and a buffer unit configured to parallelly output DCT coefficients which are dequantized by the dequantizer and input serially while performing double buffering according to an input format; And an IDCT unit configured to IDCT the DCT coefficients output in parallel from the buffer unit.

The VLD decodes a run-level pair for each code corresponding to a DCT coefficient among the input video bitstreams, and then, together with the level information, position information indicating how many levels of the run-level pair are 64 DCT coefficients. It is characterized by outputting.

When the format of the input DCT coefficient is HD, the inverse quantization unit down converts the dequantized DCT coefficient by horizontal low pass filtering.

The buffer unit stores the inverse quantized DCT coefficients and uses first and second buffers, which are used as a single buffer or a double buffer according to an input format, and first and second buffers using position information output from the variable length decoder. And a buffer controller for generating a write / read address and a write / read enable signal, and a multiplexer which selects output data of the first and second buffers and outputs them to IDCT.

The first and second buffers may be used as a single buffer under the control of the buffer controller when the input format is SD class, and the DCT coefficients of one decoding block may be divided.

The first and second buffers are used as double buffers under the control of the buffer controller when the input format is HD, and when one DCT coefficient is written to one buffer, the other buffer reads the DCT coefficients of the previous block. When writing the next block, it is characterized by changing the writing and reading positions.

When reading the DCT coefficients written serially in the first and second buffers, a plurality of DCT coefficients are simultaneously read under the control of the buffer controller.

According to an aspect of the present invention, there is provided a video decoding method comprising: decoding and outputting codes corresponding to DCT coefficients of an input video bitstream, and performing down conversion when the input format is HD when dequantizing the decoded DCT coefficients. And outputting the DCT coefficients in parallel when the inverse quantization is serially performed while performing double buffering when the input format is HD.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a detailed block diagram of an inverse quantizer of a video decoder according to the present invention. An inverse scan (IS) unit 201 converts an index and a level value output from a VLD in the order of a raster scan, and the IS index. An IQ unit 202 for performing inverse quantization by multiplying a quantization matrix corresponding to a level value, a quantization matrix (QM) necessary for the IQ, and storing the quantization matrix value required for IQ to the IQ unit 202. A QM memory 203 for outputting, a coefficient buffer 204 for outputting 32 DCT coefficients in parallel through a down conversion if the IQ data is HD, and 64 DCT coefficients in parallel for an SD class, and the coefficient buffer And a mismatch control unit 205 for controlling mismatch of the output of 204.

In the present invention configured as described above, the VLD decodes codes corresponding to DCT coefficients of a video bitstream and outputs them as run and level for each code. At this time, the VLD accumulates the run values of the run-level pairs, converts the run-level pairs into an index indicating how many of the 64 coefficients are, and then replaces the index and level as shown in FIG. The inverse scan unit 201 of the inverse quantizer may be output. Here, the index has one of 0 to 63 values.

That is, FIG. 2 decodes variable length coded coefficients (run, level) by a zig-zag or alternate scan at the transmitting side in the VLD of the receiving side, and outputs the index and level of the coefficients. .

The inverse scan unit 201 converts an index and a level input by a zigzag or alternate scan method into a raster scan order and outputs the raster scan order to the IQ unit 202. The IQ unit 202 restores the actual DCT coefficient by multiplying the quantization matrix corresponding to the index by the level value. Here, since the value of the quantization matrix is multiplied according to the position on the 8x8 block of the DCT coefficient, it is necessary to know which position the coefficient to be multiplied. Therefore, the IQ unit 202 reads the input index and reads the quantization matrix of the position corresponding to the index from the QM memory 203 and multiplies the level value. In this case, the IQ unit 202 does not generate 0 for the run level of the decoded coefficients, and performs IQ by searching for the position information on the 8x8 block of the decoded coefficients from the given run, thereby eliminating the need for IQ for 0. Therefore, processing time can be reduced.

At this time, since the video output format of the SDTV aims at a resolution of about 704 × 480 and 640 × 480, the HD input format can secure sufficient resolution even by down conversion. In other words, down-converting HD data results in poor image quality, but still achieves SD resolution.

Therefore, when the input format is HD, the IQ unit 202 down-converts the dequantized DCT coefficients and outputs them to the coefficient buffer 204.

3 (a) to (c) show a down conversion process in the IQ unit 202 for the HD class input format. This shows the effect of a horizontal low pass filter in the frequency domain.

The DCT coefficients dequantized by the IQ unit 202 are temporarily stored in the coefficient buffer 204 and then output to the IDCT unit 103 through the mismatch control unit 205 when the IDCT requests.

The mismatch control unit 205 prevents errors from accumulating when the DCT of the encoder and the IDCT of the decoder do not match because MPEG specifies only decoding, and for this purpose, all dequantized coefficients in one block are added. The sum is adjusted according to odd or even numbers. If it is odd, leave it as it is, and convert the last coefficient only if it is even.

On the other hand, the coefficient buffer 204 is controlled differently according to the video input format to perform efficient buffering with a small size, by enabling a similar data transfer rate in the case of HD input format or SD input format Therefore, it keeps the operation of IQ constant regardless of input.

At this time, in the HD input format, one block is composed of 32 coefficients by down-conversion in the IQ unit 202, and performs 4x8 IDCT. Here, 32 coefficients per block are half the SD class input format, and half the size of the coefficient buffer is sufficient.

In addition, since down conversion is performed by residual in the horizontal direction, motion compensation is used by downscaling the horizontal direction of the calculated motion vector. For example, motion compensation is performed by scaling the motion vector of (MVX, MVY) to (MVX / 2, MVY).

FIG. 4 is a block diagram illustrating the coefficient buffer 204. The first buffer 401, the second buffer 402, the index and the valid signal valid_in are received to store coefficients. A buffer controller 403 for generating a read / write address and a read / write enable signal to the buffers 401 and 402, and a multiplexer for selecting and outputting output data of the first buffer 401 or the second buffer 402. 404.

At this time, the writing of the coefficients into the first buffer 401 is performed one by one, that is, the serial data may be output in parallel by reading two coefficients written in the first buffer 401 at the same time.

That is, since only the non-zero DCT coefficients are output from the IQ unit 202, the amount of data is not large. However, when 0 is filled in to output to the IDCT unit, the amount of data becomes very large. Therefore, a high clock speed must be used for a very fast processing speed, which increases the burden on the hardware. At this time, the clock speed can be lowered by making the 64 coefficients filled with 0 parallel, and for this purpose, the first buffer 401 converts the serially input data into parallel and outputs the parallel.

Similarly, the second buffer 402 has the same configuration as the first buffer 401.

In FIG. 4 configured as described above, the DCT coefficients of the IQ unit 202 are converted into parallel to increase the processing speed and input to the coefficient buffer 204 to generate 64 or 32 DCT coefficients. 204 operates differently for the SD input format and the HD input format.

That is, the first and second buffers 401 and 402 in the SD class input format are used as a single buffer to divide and store 64 DCT coefficients corresponding to one decoding block, and output them to the IDCT unit 103. However, the first and second buffers 401 and 402 in the HD input format which are down converted and input are used as double buffers.

First, in the case of the SD class input format, the buffer controller 403 generates an address and a write enable signal by an index of coefficients while a valid valid signal is coming. In the reset state all buffers are initialized to '0' and only valid DCT coefficients are written to the corresponding addresses of the first or second buffers 401 or 402 that are enabled. In other words, DCT coefficients corresponding to one block are divided into first and second buffers 401 and 402. Then, when the data written to the first and second buffers 401 and 402 are transmitted to the IDCT unit 103 through the multiplexer 404, the first and second buffers 401 and 402 are filled with '0' again and the next decoding block Waiting for the write signal. In other words, since the number of nonzero coefficients in one decoding block is less than 10, sufficient IQ processing speed and data transmission rate can be maintained.

(A) to (h) of FIG. 5 are buffer read timing diagrams in the SD class input format. In the coefficients Coeff_0 and Coeff_1, numbers represent indices and the order in which the data is transmitted is arranged in a block as shown in FIG. It consists of two coefficient units in the (row) direction.

For example, when the read enable signal re_a of the first buffer 401 is turned on as shown in FIG. 5A, two coefficients Coeff_0 and Coeff_1 written in the first buffer 401 are (c) and (d Are simultaneously output, and when the read enable signal re_b of the second buffer 402 is turned on as shown in (b), two coefficients Coeff_0 and Coeff_1 written in the second buffer 402 are (e), ( f) is printed at the same time. Accordingly, the multiplexer 404 alternately selects outputs of the first and second buffers 401 and 402 and simultaneously outputs two coefficients Coeff_0 and Coeff_1 in a raster scan manner as shown in (g) and (h).

In addition, coefficients input to the buffer are decoded into serial one by one, and data to be output by IDCT is output in parallel to ensure real-time decoding performance.

On the other hand, when the DCT coefficients output from the IQ unit 202 are HD class input formats, one block is composed of 32 coefficients by down-conversion, so that the first and second buffers 401 and 402 are individually 32 It is possible to store two coefficients, while other buffers have read access while writing to one buffer. In other words, when one block coefficient is written to one buffer, the other buffer reads the previous block.

Therefore, since the HD class input format has about twice as many decoding blocks as the SD class input format, the double buffering ensures a sufficient data transfer rate, that is, the decoding time, as desired. That is, in case of HD input format, the decoding time is a little short even by down conversion, but the shortage can be eliminated by double buffering.

As in the SD class input format, the write address and the read address are generated by the buffer control unit 403. When writing, one coefficient is written to each buffer. However, the read address reads two coefficients written to each buffer at the same time. The data entered can be output in parallel. In addition, the buffer into which the data is read is filled with '0' again and waits for the write signal of the next decoding block.

6A to 6H are read timing diagrams of the coefficient buffers for the HD-level input format. In the coefficients Coeff_0 and Coeff_1, numbers represent indices and the order of transmission is down as shown in FIG. It consists of two coefficient units in the row direction in the converted block. At this time, while all the DCT coefficients of one block are read from one buffer as shown in (a) and (b) of FIG. 6, the other buffer is not read enabled, and only after reading all of the DCT coefficients of one block from one buffer. Another buffer is read enabled.

When the read enable signal re_a of the first buffer 401 is turned on as shown in FIG. 6A, two coefficients Coeff_0 and Coeff_1 written in the first buffer 401 are (c) and (d Are simultaneously output, and when the read enable signal re_b of the second buffer 402 is turned on as shown in (b), two coefficients Coeff_0 and Coeff_1 written in the second buffer 402 are (e), ( f) is printed at the same time. Therefore, in the multiplexer 404, while the read enable signal re_a of the first buffer 401 is turned on, two coefficients Coeff_0 and Coeff_1 written in the first buffer 401 are selected (g) and (h). ) And simultaneously output two coefficients Coeff_0 and Coeff_1 written to the second buffer 402 while the read enable signal re_b of the second buffer 402 is turned on.

As described above, since the DCT coefficient of the HD class input format secures sufficient decoding time by down-conversion and double buffering, the HD class input image can be displayed in the SD class in the SDTV.

As described above, according to the video decoding apparatus and method according to the present invention, by performing down-conversion on the HD-class input format of SDTV, which requires a large amount of data processing speed and speed, inverse quantization independent of video display resolution can be performed. In addition, by maintaining a constant data transfer rate with flexible double buffering for the down-converted HD-class DCT coefficient, ASIC (Application Specific Integrated Circuit), which enables stable operation at a constant speed regardless of the video input format Application specific integrated circuits).

By storing the IQ DCT coefficients in the coefficient buffer and writing the DCT coefficients one by one using the position information of the coefficients sent from the VLD, by reading a plurality of DCT coefficients simultaneously and outputting data serially in parallel, The speed of the clock can be lowered, which does not burden the hardware.

1 is a block diagram of a general video decoder

2 is a detailed block diagram of an inverse quantizer of a video decoder according to the present invention.

3 is a diagram showing an example of down-conversion of the DCT coefficients of the HD input format during inverse quantization according to the present invention.

4 is a detailed block diagram of the coefficient buffer of FIG.

5A to 5H are read timing diagrams of the coefficient buffer of FIG. 4 in the SD class input format.

6A to 6H are read timing diagrams of the coefficient buffer of FIG. 4 in the HD input format.

Explanation of symbols for main parts of the drawings

201: reverse scanning unit 202: inverse quantization unit

203: Quantization Matrix Memory 204: Coefficient Buffer

205: mismatch control unit 401, 402: first and second buffers

403: buffer control unit 404: multiplexer

Claims (8)

A variable length decoder for decoding and output codes corresponding to discrete cosine transform (DCT) coefficients of an input video bitstream; An inverse quantizer for performing down conversion according to an input format during inverse quantization of the DCT coefficients decoded by the variable length decoder; A buffer unit for outputting DCT coefficients which are inversely quantized by the inverse quantizer while performing double buffering according to an input format; And an inverse discrete cosine transform unit for inverse discrete cosine transforming the DCT coefficients output from the buffer unit. The variable length decoder of claim 1, wherein Decoded into a run-level pair for each code corresponding to the DCT coefficients of the input video bitstream, and outputting position information indicating the level coefficient of the run-level pair together with the level value indicating the 64th DCT coefficient. Video decoding apparatus. The method of claim 1, wherein the dequantization unit And if the format of the input DCT coefficient is HD, down-converting the dequantized DCT coefficient by horizontal low pass filtering. The method of claim 1, wherein the buffer unit First and second buffers for storing the dequantized DCT coefficients and used as a single buffer or a double buffer according to an input format; A buffer controller configured to generate write / read addresses and write / read enable signals to first and second buffers using position information output from the variable length decoder; And a multiplexer which selects output data of the first and second buffers and outputs the output data to the IDCT. The method of claim 4, wherein the first and second buffers If the input format is a standard (SD) class, the video decoding apparatus, which is used as a single buffer under the control of the buffer control unit for dividing the DCT coefficients of one decoding block. The method of claim 4, wherein the first and second buffers If the input format is HD, it is used as a double buffer under the control of the buffer control unit. When writing one block of DCT coefficients in one buffer, the other buffer reads the DCT coefficients of the previous block, and writes and reads each other when writing the next block. A video decoding apparatus, characterized in that for changing the position. 5. The video decoding apparatus according to claim 4, wherein a plurality of DCT coefficients are read simultaneously under the control of the buffer controller when reading DCT coefficients written serially into the first and second buffers. Decoding and outputting codes corresponding to discrete cosine transform (DCT) coefficients of an input video bitstream; Performing downconversion if the input format is high definition (HD) in dequantization of the decoded DCT coefficients; Outputting the inversely quantized DCT coefficients while performing double buffering on a block basis if the input format is HD; Inverse discrete cosine transforming the output DCT coefficients.