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KR100550636B1 - Method for forming high-dielectric capacitor in semiconductor device - Google Patents

Method for forming high-dielectric capacitor in semiconductor device Download PDF

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KR100550636B1
KR100550636B1 KR1019990062254A KR19990062254A KR100550636B1 KR 100550636 B1 KR100550636 B1 KR 100550636B1 KR 1019990062254 A KR1019990062254 A KR 1019990062254A KR 19990062254 A KR19990062254 A KR 19990062254A KR 100550636 B1 KR100550636 B1 KR 100550636B1
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film
forming
material film
tantalum
lower electrode
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KR20010064121A (en
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민우식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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Abstract

본 발명은 Ta2O5 형성 시의 고온 산화 분위기에서 하부전극 물질이 산화되는 것을 방지할 수 있는 반도체 소자의 고유전체 캐패시터 형성방법을 제공하는데 그 목적이 있다. 상기 목적을 달성하기 위한 본 발명은, 소정의 하부층 상에 하부전극 형성을 위한 제1금속계물질막을 형성하는 제1 단계; 상기 제1금속계물질막 상에 탄탈륨막을 형성하는 제2 단계; 상기 탄탈륨막 상에 하부전극 형성을 위한 제2금속계물질막을 형성하는 제3 단계; 및 산화 분위기에서 열처리를 실시하여, 상기 탄탈륨막 내의 Ta가 상기 산화 분위기에 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면으로 확산되도록 하여 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면에 Ta2O5막을 형성하는 제4 단계를 포함하여 이루어진다.An object of the present invention is to provide a method of forming a high dielectric capacitor of a semiconductor device capable of preventing the lower electrode material from being oxidized in a high temperature oxidizing atmosphere when Ta 2 O 5 is formed. The present invention for achieving the above object, a first step of forming a first metal-based material film for forming a lower electrode on a predetermined lower layer; Forming a tantalum film on the first metal material film; Forming a second metal-based material film for forming a lower electrode on the tantalum film; And heat treating in an oxidizing atmosphere so that Ta in the tantalum film diffuses to the surfaces of the first and second metal material films exposed to the oxidizing atmosphere, and the first metal material film and the first metal material film exposed. And a fourth step of forming a Ta 2 O 5 film on the surface of the bimetallic material film.

텅스텐막, 탄탈륨막Tungsten Film, Tantalum Film

Description

반도체 소자의 고유전체 캐패시터 형성방법{Method for forming high-dielectric capacitor in semiconductor device} Method for forming high-dielectric capacitor in semiconductor device             

도1a 내지 도1c는 본 발명의 일실시예인 실린더 구조의 고유전체 캐패시터의 유전체막인 Ta2O5막의 형성방법에 관한 공정도.1A to 1C are process diagrams illustrating a method for forming a Ta 2 O 5 film, which is a dielectric film of a high-k dielectric capacitor having a cylinder structure according to one embodiment of the present invention.

도2는 W-Ta 이원계 물질의 상태도.2 is a state diagram of a W-Ta binary system.

도3은 W 및 Ta의 산화물에 대한 온도에 따른 산화물 형성 자유에너지 값을 도시한 도면.FIG. 3 shows oxide formation free energy values with temperature for oxides of W and Ta. FIG.

*도면의 주요부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawings

10 : 반도체 기판 11 : 층간절연막10 semiconductor substrate 11 interlayer insulating film

12 : 콘택플러그 14a : 텅스텐막12 contact plug 14a tungsten film

14b : 텅스텐막 17 : Ta2O5막14b: tungsten film 17: Ta 2 O 5 film

본 발명은 반도체 제조기술에 관한 것으로, 특히 고유전물질인 탄탈륨 산화막(Ta3O5)을 유전체막으로 사용하는 고집적 메모리 소자의 캐패시터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor of a highly integrated memory device using a high dielectric material tantalum oxide film (Ta 3 O 5 ) as a dielectric film.

현재 반도체 메모리 소자는 크게 RAM(Random Access Memory)과 ROM(Read only Memory)로 구분할 수가 있다. 특히, RAM은 다시 다이나믹램(Dynamic RAM, 이하 DRAM이라 칭함)과 스태틱램(Static RAM)으로 나뉘지며, 이 중에서도 DRAM은 1개의 트랜지스터(transister)와 1개의 캐패시터로 1개의 단위셀(unit cell)이 구성되어 집적도에서 가장 유리하기 때문에 메모리 시장을 주도하고 있다.Currently, semiconductor memory devices can be classified into random access memory (RAM) and read only memory (ROM). In particular, the RAM is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM. Among them, a DRAM is one unit cell with one transistor and one capacitor. This configuration is leading the memory market because it is most advantageous in density.

한편, 고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 현재에는 256M이나 1G급 DRAM이 양산단계에 근접하고 있다.On the other hand, due to the progress of high integration, memory capacity has increased by four times in three years, and now 256M or 1G DRAM is approaching the mass production stage.

이와 같이 DRAM의 집적도가 높아질수록 메모리 셀의 면적은 256M DRAM의 경우 0.5㎛2, 셀의 기본구성요소 중의 하나인 캐패시터의 면적은 0.3㎛2이하로 작아져야 한다. 이러한 이유로 256M DRAM 이상에서는 종래의 반도체 공정에서 사용되는 기술이 한계를 보이기 시작하고 있다.As the integration degree of DRAM increases, the area of the memory cell should decrease to 0.5 μm 2 for 256M DRAM and the area of the capacitor, which is one of the basic components of the cell, to 0.3 μm 2 or less. For this reason, the technology used in the conventional semiconductor process is starting to show a limit above 256M DRAM.

즉, 64M DRAM에서 지금까지 사용되어 온 유전재료인 SiO2/Si3N4 등을 사용하여 캐패시터를 제조할 경우 필요한 캐패시턴스를 확보하기 위해서는 박막의 두께를 최대한 얇게 하더라도 캐패시터가 차지하는 면적은 셀 면적의 6배가 넘어야 한다.In other words, in order to obtain the required capacitance when manufacturing a capacitor using SiO 2 / Si 3 N 4 , which is a dielectric material used in 64M DRAM, the area occupied by the capacitor is the cell area even though the thickness of the thin film is as thin as possible. It should be over six times.

이러한 이유로 캐패시턴스의 확보를 위해 그 표면적을 늘리는 방안이 제시되고 지금까지 이에 대한 연구가 계속되고 있다. 캐패시터의 하부전극 표면적을 증가 시키기 위해서 3차원 구조의 스택 캐패시터 구조 또는 트렌치형 캐패시터 구조 또는 반구형 폴리실리콘막을 사용하는 기술 등 여러가지 기술이 제안된 바가 있다.For this reason, a method of increasing the surface area for securing the capacitance has been proposed and research on it has been continued until now. In order to increase the surface area of the lower electrode of the capacitor, various techniques have been proposed, such as a three-dimensional stack capacitor structure, a trench capacitor structure, or a technique using a hemispherical polysilicon film.

그러나, 256M DRAM 이상의 소자에서는 기존의 ONO(Oxide Nitride Oxide)재료의 유전물질로는 캐패시턴스를 늘이기 위해 더 이상 두께를 줄일 수도 없고, 표면적을 늘이기 위해 그 구조를 더 복잡하게 만드는 경우 공정과정이 너무 복잡하여 제조단가의 상승과 수율이 떨어지는 문제점을 수반하게 된다.However, in devices larger than 256M DRAM, the dielectric material of traditional Oxide Nitride Oxide (ONO) material can no longer reduce the thickness to increase the capacitance, and the process is too complicated to make the structure more complex to increase the surface area. This is accompanied by a rise in manufacturing cost and a drop in yield.

이와 같은 문제점을 해결하기 위해서, 유전물질로써 종래 ONO재료의 유전물질에 비해 보다 높은 유전상수를 갖는 탄탈륨 산화막(Ta2O5,

Figure 111999018153996-pat00001
r=24 ~ 26)을 캐패시터의 유전체막으로 채용하게 되었다.In order to solve such a problem, a tantalum oxide film having a higher dielectric constant than that of a conventional ONO material as a dielectric material (Ta 2 O 5,
Figure 111999018153996-pat00001
r = 24 to 26) is used as the dielectric film of the capacitor.

한편, Ta2O5를 유전체막으로 사용한 캐패시터의 하부전극 재료로써 TiN, W, WSix 등과 같은 물질이 거론되고 있다. 그러나, Ta2O5 형성 시의 고온의 산화분위기에서 하부전극 재료로 사용된 TiN, W, WSix 등의 물질이 산화되어 캐패시터 특성이 저하되는 문제점이 지적되고 있다.On the other hand, materials such as TiN, W, WSi x and the like have been mentioned as lower electrode materials of capacitors using Ta 2 O 5 as a dielectric film. However, it has been pointed out that the characteristics of the capacitors are deteriorated due to oxidation of materials such as TiN, W, WSi x and the like used as the lower electrode material in the high temperature oxidation atmosphere when Ta 2 O 5 is formed.

본 발명은 Ta2O5 형성 시의 고온 산화 분위기에서 하부전극 물질이 산화되는 것을 방지할 수 있는 반도체 소자의 고유전체 캐패시터 형성방법을 제공하는데 그 목적이 있다.
An object of the present invention is to provide a method of forming a high dielectric capacitor of a semiconductor device capable of preventing the lower electrode material from being oxidized in a high temperature oxidizing atmosphere when Ta 2 O 5 is formed.

상기 목적을 달성하기 위한 본 발명은, 소정의 하부층 상에 하부전극 형성을 위한 제1금속계물질막을 형성하는 제1 단계; 상기 제1금속계물질막 상에 탄탈륨막을 형성하는 제2 단계; 상기 탄탈륨막 상에 하부전극 형성을 위한 제2금속계물질막을 형성하는 제3 단계; 및 산화 분위기에서 열처리를 실시하여, 상기 탄탈륨막 내의 Ta가 상기 산화 분위기에 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면으로 확산되도록 하여 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면에 Ta2O5막을 형성하는 제4 단계를 포함하여 이루어진다.The present invention for achieving the above object, a first step of forming a first metal-based material film for forming a lower electrode on a predetermined lower layer; Forming a tantalum film on the first metal material film; Forming a second metal-based material film for forming a lower electrode on the tantalum film; And heat treating in an oxidizing atmosphere so that Ta in the tantalum film diffuses to the surfaces of the first and second metal material films exposed to the oxidizing atmosphere, and the first metal material film and the first metal material film exposed. And a fourth step of forming a Ta 2 O 5 film on the surface of the bimetallic material film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도1a 내지 도1c는 본 발명의 일실시예인 실린더 구조의 고유전체 캐패시터의 유전체막인 Ta2O5막의 형성방법에 관한 공정도를 나타낸 도면이다.1A to 1C are views showing a process for forming a Ta 2 O 5 film, which is a dielectric film of a high-k dielectric capacitor having a cylinder structure according to one embodiment of the present invention.

본 실시예는 우선, 도1a에 도시된 바와 같이 소정의 하부층 공정이 완료된 반도체 기판(10) 상부에 층간절연막(11)을 형성하고, 이를 선택식각하여 캐패시터 형성을 위한 콘택 플러그(12)를 형성한다. 다음으로, 전체 구조물의 상부에 제1희생막(13)을 전면 증착한 후, 이를 선택 식각한다. 계속하여, 전체 구조물의 표면을 따라 고유전체 캐패시터의 하부전극 형성을 위한 텅스텐(W)막(14a)을 형성한다. 이 때, 텅스텐막(14a)은 하부전극 형성을 위한 두께의 일부만 형성한다. 이어서, 상기 텅스텐막(14a)의 상부에 탄탈륨(Ta)막(15)을 500 ~ 800Å정도 얇게 증착한 후, 다시 하부전극에 필요한 나머지 두께의 텅스텐막(14b)을 상기 탄탈륨막(15) 상부에 형성한다. 이어서, 전체 구조물의 상부에 제2희생막(16)을 형성한다. 이때, Ta막(15)은 화학기상증착(chemical vapor deposition,CVD)법 또는 물리기상증착(physical vapor deposition,PVD)법을 사용하여 형성한다.In the present embodiment, first, as shown in FIG. 1A, an interlayer insulating film 11 is formed on a semiconductor substrate 10 on which a predetermined lower layer process is completed, and then selectively etched to form a contact plug 12 for forming a capacitor. do. Next, after depositing the first sacrificial layer 13 over the entire structure, it is selectively etched. Subsequently, a tungsten (W) film 14a for forming the lower electrode of the high dielectric capacitor is formed along the surface of the entire structure. At this time, the tungsten film 14a forms only a part of the thickness for forming the lower electrode. Subsequently, a thin tantalum (Ta) film 15 is deposited thinly on the tungsten film 14a by about 500 to 800 microns, and then a tungsten film 14b having the remaining thickness required for the lower electrode is again deposited on the tantalum film 15. To form. Subsequently, the second sacrificial layer 16 is formed on the entire structure. At this time, the Ta film 15 is formed by using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

다음으로, 도1b에 도시된 바와 같이 제1희생막(13) 상부의 제2희생막(16), 텅스텐막(14b), 탄탈륨막(15) 및 텅스텐막(14a)를 에치백 또는 화학적 기계적 연마(Chemical Mechanical Polishing, CMP)를 통해 제거하고, 제2희생막(16) 및 제1희생막(13)을 제거하여 텅스텐막(14a), Ta막(15) 및 텅스텐막(14b)의 구조물을 실린더 형태로 형성시킨다.Next, as illustrated in FIG. 1B, the second sacrificial film 16, the tungsten film 14b, the tantalum film 15, and the tungsten film 14a on the first sacrificial film 13 are etched back or chemically mechanically disposed. The structure of the tungsten film 14a, the Ta film 15, and the tungsten film 14b is removed by chemical mechanical polishing (CMP) and the second sacrificial film 16 and the first sacrificial film 13 are removed. To form a cylinder.

다음으로, 도1c에 도시된 바와 같이 미량의 산소를 포함한 500 ~ 800℃의 고온 분위기에서 열처리를 실시하여 텅스텐막(14b)의 표면에 Ta2O5막(17)이 형성된 구조를 이룬다. 이때, 산소분압은 10-1 ~ 10-10 torr 정도로 하며, N2, H2, Ar등의 가스들을 첨가가스로 사용할 수 있다.Next, as shown in FIG. 1C, a heat treatment is performed in a high temperature atmosphere of 500 to 800 ° C. containing a small amount of oxygen to form a structure in which a Ta 2 O 5 film 17 is formed on the surface of the tungsten film 14b. At this time, the oxygen partial pressure is about 10 −1 to 10 −10 torr, and gases such as N 2 , H 2 , and Ar may be used as the additive gas.

상기 Ta2O5막(17)의 형성과정을 첨부된 도면 도2 및 도3을 참조하여 보다 구체적으로 설명한다.A process of forming the Ta 2 O 5 film 17 will be described in more detail with reference to FIGS. 2 and 3.

먼저, 상기 열처리 시의 산소분압은 텅스텐까지 산화시키지 않을 정도로 충분히 낮아야 한다. 이와 같이, 열처리를 실시하게 되면, 텅스텐막(14a) 및 텅스텐 막(14b) 사이에 형성되어 있던 탄탈륨막(15)의 Ta가 W보다 산소와의 친화력이 높기 때문에 열처리 시 온도가 높아짐에 따라 텅스텐막(14b)을 통과하여 표면으로 확산하게 된다.First, the oxygen partial pressure during the heat treatment should be low enough so as not to oxidize to tungsten. In this manner, when the heat treatment is performed, since the Ta of the tantalum film 15 formed between the tungsten film 14a and the tungsten film 14b has a higher affinity with oxygen than W, the temperature during the heat treatment increases tungsten. It passes through the film 14b and diffuses to the surface.

여기서, 첨부된 도면 도2는 W-Ta 이원계 물질의 상태도를 나타낸 것으로써, 도2를 살펴보면, W와 Ta간에 중간상이 존재하지 않으며 완전 전율고용체를 형성함을 알 수 있다. 즉, 3020℃ 이상의 고온의 열처리 시에도 W과 Ta간에는 반응에 의한 중간물질을 형성하지 않음을 알 수 있다. 따라서, 텅스텐막(14a) 및 텅스텐막(14b) 사이에 탄탈륨막(15)이 형성된 구조를 만든 후 열처리하면, 탄탈륨막(15)의 Ta는 W의 결정립계를 통과해 쉽게 확산이 일어나며, 또한 텅스텐막(14b)의 표면에 산소 기체가 존재하면 Ta가 우선적으로 반응하여 고유전율의 Ta2O5가 형성된다.Here, FIG. 2 shows a state diagram of the W-Ta binary material. Referring to FIG. 2, it can be seen that an intermediate phase does not exist between W and Ta and forms a complete tremor solid solution. That is, it can be seen that even during the heat treatment at a high temperature of 3020 ° C. or higher, W and Ta do not form an intermediate material by the reaction. Therefore, when a structure in which a tantalum film 15 is formed between the tungsten film 14a and the tungsten film 14b is formed and subjected to heat treatment, Ta of the tantalum film 15 passes through the grain boundary of W and easily diffuses. When oxygen gas is present on the surface of the film 14b, Ta reacts preferentially to form Ta 2 O 5 of high dielectric constant.

첨부된 도면 도3은 W 및 Ta의 산화물에 대한 온도에 따른 산화물 형성 자유에너지 값을 도시한 도면으로써, Ta가 W보다 산소와 결합하여 산화물을 형성하는 자유에너지값이 훨씬 낮음을 알 수 있다. 즉, Ta가 W보다 산소 친화력이 우수하므로 텅스텐막(14b)의 표면에는 텅스텐과 산소와의 화합물인 WO2 및 WO3와 같은 산화물에 우선하여 Ta2O5막(17)이 형성되는 것이다.FIG. 3 is a diagram illustrating oxide formation free energy values according to temperatures of W and Ta oxides, and it can be seen that Ta has much lower free energy values combining with oxygen to form oxides. That is, since Ta has better oxygen affinity than W, the Ta 2 O 5 film 17 is formed on the surface of the tungsten film 14b in preference to oxides such as WO 2 and WO 3 which are compounds of tungsten and oxygen.

한편, 텅스텐막(14b)의 표면에 형성되는 Ta2O5막(17)의 두께는 산소분압 및 열처리 시의 온도에 의존하기 때문에 텅스텐막(14a)과 텅스텐막(14b)의 중간에 형성된 탄탈륨막(15)의 층덮힘성은 고려하지 않아도 된다는 장점이 있다. 즉, 산화 메카니즘에 따르면, Ta2O5막(17)의 두께는 초기단계에 형성된 Ta2O5막(17)으로 확산해 들어가는 산소의 확산성에 의존하며, 이는 표면의 산소분압 및 열처리 온도가 중요한 변수로 작용하기 때문에 텅스텐막(14a) 및 텅스텐막(14b) 사이에 형성된 탄탈륨막(15)의 두께가 불균일하더라도 Ta2O5막(17)은 균일한 두께를 가지게 된다.On the other hand, since the thickness of the Ta 2 O 5 film 17 formed on the surface of the tungsten film 14b depends on the oxygen partial pressure and the temperature during heat treatment, tantalum formed between the tungsten film 14a and the tungsten film 14b. The layer covering of the film 15 has the advantage that it does not need to be considered. That is, according to the oxidation mechanism, Ta 2 O 5 thickness of the film 17 is dependent on gender diffusion of oxygen diffusion to entering the Ta 2 O 5 film (17) formed in the initial stage, which is the oxygen partial pressure and the heat treatment temperature of the surface Since it functions as an important variable, even if the thickness of the tantalum film 15 formed between the tungsten film 14a and the tungsten film 14b is uneven, the Ta 2 O 5 film 17 has a uniform thickness.

이후, 상기 Ta2O5막(17) 상부에 상부전극을 형성하여 고유전체 캐패시터 형성공정을 완료한다.Thereafter, an upper electrode is formed on the Ta 2 O 5 film 17 to complete the process of forming a high dielectric capacitor.

이렇듯, 본 발명은 고유전체 캐패시터의 고유전체막 형성방법에 있어서, 하부전극으로 사용되는 텅스텐막의 사이에, 이후 형성될 고유전체막인 Ta2O5막의 모재료라 할 수 있는 Ta막을 형성한 후 미량의 산소를 포함한 고온 열처리를 실시하여 Ta를 고온의 산소분위기인 텅스텐막의 표면으로 확산시켜 고유전체막인 Ta2O5막을 형성하게 되는 것이다.As described above, in the method of forming a high dielectric film of a high dielectric capacitor, the present invention forms a Ta film, which is a mother material of a Ta 2 O 5 film, which is a high dielectric film to be formed, between the tungsten films used as the lower electrode. By performing a high temperature heat treatment containing a small amount of oxygen, Ta is diffused onto the surface of a tungsten film which is a high temperature oxygen atmosphere to form a Ta 2 O 5 film which is a high dielectric film.

이렇게 함으로써, 본 발명에서는 상기 종래기술에서의 문제점인 Ta2O5막 형성 시 발생하였던 하부전극의 산화문제를 해결할 수 있게 된다.By doing so, in the present invention, it is possible to solve the problem of oxidation of the lower electrode, which occurred when the Ta 2 O 5 film was formed.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

예컨대, 본 실시예에서는 실린더 구조의 하부전극을 가진 고유전체 캐패시터 형성에 대해 언급하였지만, 이외에도 적층구조(stacted) 또는 홈(trench)구조 등의 다양한 형태를 가진 하부전극의 형성 시에도 본 발명은 적용된다.For example, although the present embodiment refers to the formation of a high-k dielectric capacitor having a lower electrode of a cylinder structure, the present invention is also applicable to the formation of a lower electrode having various forms such as a stacked structure or a trench structure. do.

본 발명은 고유전체 캐패시터의 유전체로 사용되는 Ta2O5 형성 시 하부전극이 산화되는 현상을 방지하는 효과가 있으며, 이로 인하여 캐패시터 특성을 개선할 수 있다.The present invention has the effect of preventing the lower electrode from oxidizing when Ta 2 O 5 used as the dielectric of the high-k dielectric capacitor, thereby improving the characteristics of the capacitor.

Claims (5)

소정의 하부층 상에 하부전극 형성을 위한 제1금속계물질막을 형성하는 제1 단계;A first step of forming a first metal-based material film for forming a lower electrode on a predetermined lower layer; 상기 제1금속계물질막 상에 탄탈륨막을 형성하는 제2 단계;Forming a tantalum film on the first metal material film; 상기 탄탈륨막 상에 하부전극 형성을 위한 제2금속계물질막을 형성하는 제3 단계; 및Forming a second metal-based material film for forming a lower electrode on the tantalum film; And 산화 분위기에서 열처리를 실시하여, 상기 탄탈륨막 내의 Ta가 상기 산화 분위기에 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면으로 확산되도록 하여 노출된 상기 제1금속계물질막 및 상기 제2금속계물질막 표면에 Ta2O5막을 형성하는 제4 단계The heat treatment is performed in an oxidizing atmosphere, such that Ta in the tantalum film is diffused to the surfaces of the first metal material film and the second metal material film exposed to the oxidizing atmosphere. Fourth step of forming a Ta 2 O 5 film on the surface of the metal material film 를 포함하여 이루어지는 반도체 소자의 고유전체 캐패시터 형성방법.A method of forming a high dielectric capacitor of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1금속계물질막 및 상기 제2금속계물질막이 각각 W, Ti중 하나인 것을 특징으로 하는 반도체 소자의 고유전체 캐패시터 형성방법.And the first metal material film and the second metal material film are one of W and Ti, respectively. 제1항에 있어서,The method of claim 1, 상기 탄탈륨막의 두께는 50 ~ 200Å인 것을 특징으로 하는 반도체 소자의 고유전체 캐패시터 형성방법.The tantalum film has a thickness of 50 ~ 200 GPa, a high dielectric capacitor forming method of a semiconductor device. 제1항에 있어서, The method of claim 1, 상기 열처리는 500 ~ 800℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 고유전체 캐패시터 형성방법.The heat treatment is a high dielectric capacitor forming method of a semiconductor device, characterized in that performed at a temperature of 500 ~ 800 ℃. 제1항에 있어서,The method of claim 1, 상기 열처리 시 산소분압은 10-1 ~ 10-10torr인 것을 특징으로 하는 반도체 소자의 고유전체 캐패시터 형성방법.The heat treatment when the oxygen partial pressure is 10-1 to 10-dielectric capacitor formed in a semiconductor device, characterized in that the -10 torr.
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