KR100559226B1 - Mode detect circuit for lcd module - Google Patents

Abstract

The present invention is applied to a liquid crystal display device module to perform automatic detection of an input mode (DE mode / synchronous mode) and apply it to the timing controller so that the timing control adaptive to the input mode of the liquid crystal display module is possible. It relates to a mode detection circuit of the device module.

According to a preferred embodiment of the present invention, the first D flip-flop is connected to a clock terminal of the first mode signal (DE mode) of the mode signal applied from the graphics card, and the horizontal synchronization of the second mode signal of the mode signal is performed. The second D flip-flop whose signal is connected to the clock end, the third D flip flop whose vertical synchronization signal of the second mode signal of the mode signal is connected to the clock end, and the first to third D flip-flops An AND gate for AND processing the output of the output stage, an inverted output of the first D flip-flop, and an OR gate for processing the output of the AND gate, and a mode detection signal from the OR gate and the AND gate is the timing controller. Is output to

Preferably, the mode detection circuit is integrally formed with the liquid crystal display module.

Description

MODE DETECT CIRCUIT FOR LCD MODULE}

1 is a block diagram illustrating an example in which a mode detection circuit of a liquid crystal display device module according to the present invention is applied;

2 is a view showing a detailed configuration of a mode detection circuit of the liquid crystal display module according to the present invention shown in FIG.

3 is a view for explaining a mode detection output state of the mode detection circuit of the liquid crystal display module according to the present invention shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: graphics card, 20: liquid crystal display (LCD) module,

22: mode detection circuit section, 24: timing control section,

26: Drive IC, 30, 32, 34: D flip flop,

36: Andgate, 38: Oagate.

The present invention relates to a mode detection circuit of a liquid crystal display device module, and more particularly, to automatically detect a mode signal applied to the liquid crystal display module so that timing control of the liquid crystal display market value module can be adaptively applied to the input mode. It relates to a mode detection circuit of a liquid crystal display module to be implemented.

Currently, a liquid crystal display for reproducing an image signal by controlling an arrangement of liquid crystals is widely used based on the characteristics of low voltage driving and low power consumption.

In such a liquid crystal display device, a light transmittance of a liquid crystal is controlled by a thin film transistor formed in a matrix array form on a liquid crystal display panel to switch on / off in response to an image signal to express an image.

Therefore, displays using TFT-liquid crystal display devices are widely used in notebook computers, mobile phones, car navigation systems, and the like, and various types of DC voltages are required to drive the TFT-liquid crystal display devices. To do this, a charge pump or a DC-DC converter is used.

In addition, proper timing (i.e., sequencing) is required between the input power supply and the output voltage, image data (R / G / B), gamma voltage, etc. of the driving circuit in the corresponding TFT-liquid crystal display device.

In general, a timing control signal generated in a timing control integrated circuit for a liquid crystal display module is based on a DE (data enable) mode and a sink (H- / V-sync) mode. Here, in the DE mode, a timing control signal for driving the liquid crystal display is generated based on the data enable signal applied from the graphics card, while in the sync mode, the synchronization signal (Hsync / Vsync) provided from the graphics card is referenced. This generates a timing control signal.

That is, when the liquid crystal display module is applied to a notebook computer, timing control based on the DE mode is usually executed, whereas when the liquid crystal display module is applied to the monitor, timing control based on the synchronous mode is usually executed. do.

However, in the related art, in consideration of the practical application of the liquid crystal display module, the timing control circuit is exclusively designed to be applied to the DE mode (i.e., when using a notebook computer) or sink mode (e.g., when using a monitor). It is disadvantageous in terms of economics and time.

In view of such a point, a timing control circuit designed to support both the DE mode and the synchronous mode has been proposed for the compatible use of the liquid crystal display module. Depending on the application state, pin setting is required externally, resulting in poor productivity.

Accordingly, the present invention has been made in view of the above-described prior art, and automatically detects an input mode (DE mode / sink mode) of a liquid crystal display module and applies it to a timing control circuit according to the detected input mode. It is an object of the present invention to provide a mode detection circuit of a liquid crystal display module for allowing an adaptive timing control signal to be generated.

In order to achieve the above object, according to a preferred embodiment of the present invention, a timing controller for generating a timing control signal in response to a mode signal applied from a graphics card, and a drive IC for generating a drive signal based on the timing control signal. A liquid crystal display module comprising: a first D flip-flop having a first mode signal (DE mode) of the mode signal connected to a clock terminal, and a horizontal synchronizing signal of a second mode signal of the mode signal being clocked The second D flip-flop connected to the stage, the third D flip-flop with the vertical synchronization signal of the second mode signal of the mode signal connected to the clock stage, and the output of the output terminals of the first to third D flip-flops An AND gate for AND processing the signal, an inverted output of the first D flip-flop, and an OR gate for processing the output of the AND gate, and detecting a mode from the OR gate and the AND gate. A mode detection circuit of a liquid crystal display module in which a call is output to the timing controller is provided.

Preferably, according to the present invention, the mode detection circuit is formed integrally with the liquid crystal display module.

According to the mode detection circuit of the liquid crystal display module according to the present invention having the above-described configuration, the input mode signal applied from the graphics card is applied to the clock stages of the first to third D flip flops, and the first to third D flips. The output terminal of the flop is AND-processed by the AND gate, and the output of the 1D flip-flop and the output of the AND gate are processed by the OR gate to obtain a mode detection signal from the OR gate and the AND gate. By applying it, timing control adaptive to the input mode of the liquid crystal display device module is enabled.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

1 is a block diagram illustrating an application example of a mode detection circuit of a liquid crystal display module according to the present invention.

In the drawing, the LCD module 20 to which the present invention is applied is connected to the rear end of the graphics card 10 for the notebook computer or the monitor, and in the graphics card 10 according to the application state, the DE mode signal or the synchronous mode. The signal H / Vsync is output or the DE / sync mode signal is output.

In addition, the LCD module 20 is provided with a mode detection circuit section 22 configured according to the present invention, and the mode detection signal provided from the mode detection circuit 22 is provided at the rear end of the mode detection circuit section 22. A timing control unit (ie, a timing control circuit) 24 for generating a timing control signal is connected on the basis of the timing control unit 24. A rear end of the timing control unit 24 is adapted to drive the actual LCD module 20 based on the timing control signal. Drive ICs 26 which generate the necessary signals are connected.

Referring to FIG. 2, the mode detection circuit unit 22 includes first to third D flip flops 30, 32, and 34.

The first D flip-flop 30 has an input terminal D connected to a power supply VDD and a clock signal terminal CLK connected to the power supply VDD through a pull-up resistor R1. It is also connected to the DE mode signal DE from the graphics card 10.

The second D flip-flop 32 has its input terminal D connected to the power supply VDD and its clock signal terminal CLK connected to the power supply VDD via a pull-up resistor R2. In addition, it is also connected to the horizontal synchronization signal (Hsync) applied in the synchronization mode from the graphics card (10).

The third D flip-flop 36 has its input terminal D connected to the power supply VDD and its clock signal terminal CLK connected to the power supply VDD via a pull-up resistor R3. In addition, it is also connected to the vertical synchronization signal (Vsync) applied in the synchronization mode from the graphics card (10).

The reset stage RST of the first to third D flip-flops 30, 32, and 34 is commonly set to an active low level.

In addition, the output terminals Q of the first to third D flip flops 30, 32, and 34 are commonly connected to the AND gate 36, and an inverted output terminal of the first D flip flop 30 is provided. QB and the output of the AND gate 36 are connected to the oragate 38.

Accordingly, the mode detection signal is obtained by the output SO of the ora gate 38 and the output S1 of the AND gate 36, and is applied to the timing controller 24.

That is, when a signal corresponding to the synchronous / DE mode is output from the graphic card 10 and is applied to the mode detection circuit unit 22, the output terminals of the first to third D flip-flops 30, 32, and 34 are applied. At Q, a high level signal is output, and accordingly, a high level signal is output according to the AND processing result at the AND gate 36. Accordingly, a high level signal is output at the OR gate 38. OR) processing output is also at a high level.

Therefore, the output SO of the or gate 38 and the output S1 of the AND gate 36 become the mode high level, and are applied to the timing control circuit 24 as the synchronous / DE mode detection signal (Fig. 3). Reference).

On the other hand, when the horizontal / vertical synchronization signal (Hsync / Vsync) is provided from the graphic card 10 according to the synchronization mode, the output terminal Q of the second and third D flip-flops 32 and 34 is high. As the signal of the level is output, the output terminal Q of the first D flip-flop 30 goes low level, so that the output of the AND gate 36 goes low level, while the first D flip flop ( The high level signal is output from the ora gate 38 to which the high level is applied at the inverting output terminal QB of 30.

Therefore, the output S0 (high level) of the ora gate 38 and the output S1 (low level) of the AND gate AND are applied to the timing control circuit 24 (see FIG. 3) to enter the synchronous mode. Corresponding timing control becomes possible.

When the signal DE corresponding to the DE mode is provided from the graphic card 10, the AND gate may be applied as a high level signal is applied only at the output terminal Q of the first D flip-flop 30. The output of the circuit 36 becomes low level, and the low level is also output from the ora gate 38 connected to the inverting output terminal QB of the first D flip-flop 30.

That is, the timing of the output S0 of the ora gate 38 and the output S1 of the AND gate 36 are both set to the low level and applied to the timing control circuit 24 (see FIG. 3). The control circuit 24 generates a timing control signal in accordance with the DE mode.

On the other hand, the mode detection circuit unit 22 shown in FIG. 2 according to the present invention is more preferable if it is designed integrally with the LCD module 20 in the form illustrated in FIG.

As described above, according to the mode detection circuit of the liquid crystal display device module according to the present invention, an automatic detection of the input mode applied to the liquid crystal display device module is performed to adaptively adapt to the detected input mode. As the timing control suitable for the present invention can be achieved, it is possible to achieve an economical / time advantage for the design and production for the timing control of the liquid crystal display module.

The preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and modifications fall within the scope of the following claims. Should be seen.

Claims (2)

A liquid crystal display module comprising a timing controller for generating a timing control signal in response to a mode signal applied from a graphics card, and a drive IC for generating a drive signal based on the timing control signal. A first D flip-flop connected to a clock terminal of the first mode signal (DE mode) of the mode signal, A second D flip-flop in which the horizontal synchronization signal of the second mode signal of the mode signal is connected to a clock terminal; A third D flip-flop in which the vertical synchronization signal of the second mode signal of the mode signal is connected to a clock terminal; An AND gate for processing an output of an output terminal of the first to third D flip flops, A liquid crystal display device comprising an inverted output of the first D flip-flop and an ore gate for processing the output of the and gate, and outputting a mode detection signal from the ore gate and the or gate to the timing controller. Module mode detection circuit. The mode detection circuit of claim 1, wherein the mode detection circuit is formed integrally with the liquid crystal display module.

Images