KR100541801B1 - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- KR100541801B1 KR100541801B1 KR1019980057522A KR19980057522A KR100541801B1 KR 100541801 B1 KR100541801 B1 KR 100541801B1 KR 1019980057522 A KR1019980057522 A KR 1019980057522A KR 19980057522 A KR19980057522 A KR 19980057522A KR 100541801 B1 KR100541801 B1 KR 100541801B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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Abstract
본 발명에 따른 반도체소자 및 그 제조방법을 개시한다. 본 발명은 반도체기판에 얕은 트렌치를 형성한 후 트렌치의 내/외측에 실리콘질화막과 폴리실리콘막의 적층구조로 이루어진 절연막을 형성하고 이를 에치-백 공정으로 식각하여 트렌치의 내측벽에 절연 스페이서를 형성한 다음, 트렌치의 저면에 산화막을 형성하고 트렌치를 채우는 USG막과 PE-TEOS막을 증착한 후 이를 연마하여 평탄화한다.Disclosed are a semiconductor device and a method of manufacturing the same according to the present invention. According to the present invention, after forming a shallow trench in a semiconductor substrate, an insulating film made of a laminated structure of a silicon nitride film and a polysilicon film is formed on the inside / outside of the trench and is etched by an etch-back process to form an insulating spacer on the inner wall of the trench. Next, an oxide film is formed on the bottom of the trench, the USG film and the PE-TEOS film filling the trench are deposited, and then polished and planarized.
따라서, 본 발명은 얕은 트렌치의 깊이를 유지하면서 트렌치 내의 보이드 발생을 방지하여 트렌치의 절연기능을 증대시킬 수 있어 소자의 신뢰성을 향상시킨다. Therefore, the present invention can increase the insulation function of the trench by preventing voids in the trench while maintaining the depth of the shallow trench, thereby improving the reliability of the device.
Description
본 발명은 에스.티.아이(Shallow Trench Isolation 이하, STI)에 관한 것으로, 특히 STI에 로코스(이하, LOCOS) 공정을 접목시켜 얕은 트렌치의 깊이를 유지하면서도 트렌치의 절연기능을 향상시키도록 한 반도체소자 및 그 제조방법에 관한 것이다.The present invention relates to STI (Shallow Trench Isolation, hereinafter), and in particular, by incorporating the LOCOS process into STI to improve the insulation of the trench while maintaining the depth of the shallow trench. A semiconductor device and a method of manufacturing the same.
일반적으로, 반도체 장치의 고집적화에 따라 반도체기판 상에 형성되는 개개의 소자 크기가 축소될뿐만 아니라 개개의 소자를 전기적으로 분리시키는 소자분리영역의 크기도 점차 서브-마이크론(sub-micron)급까지 축소되고 있다. 그에 따라, 반도체 소자의 고집적도와 고성능을 충족시킬 수 있는 미세패턴이 요구되었으며, 이에 따른 소자분리 형성 방법으로 LOCOS, 폴리-버퍼드(Poly-buffered) LOCOS, STI 등이 적용되기 시작하였다.In general, as the integration of semiconductor devices increases, not only the size of individual devices formed on the semiconductor substrate is reduced, but also the size of the device isolation region for electrically separating the individual devices is gradually reduced to sub-micron level. It is becoming. Accordingly, a fine pattern capable of satisfying high integration and high performance of semiconductor devices has been required, and LOCOS, poly-buffered LOCOS, and STI have begun to be applied as a method of forming device isolation.
이러한 소자분리 형성방법 중에 반도체기판의 비활성영역에 세미-리세스(semi-recess)된 필드산화막을 형성하는 로코스(LOCOS)법은 버즈빅(bird'beak)이 크게 발생하여 미세패턴에서의 소자분리가 어렵게 된다.The LOCOS method, which forms a semi-recessed field oxide film in an inactive region of a semiconductor substrate, has a large bird'beak, resulting in a device having a fine pattern. It becomes difficult to separate.
따라서, 필드영역에서 발생할 수 있는 버즈빅의 문제점을 해결하기 위하여 STI공정이 개발 되었으며, 씨.엠.피(Chemical Mechanical Polishing 이하, CMP)공정이 도입됨에 따라 STI공정은 보다 단순하게 되었다.Therefore, the STI process was developed to solve the problem of Buzzvik which may occur in the field area, and the STI process became simpler as the C.M.P (Chemical Mechanical Polishing) process was introduced.
현재 초고집적 디바이스에 적용하고 있는 STI의 경우 트렌치의 깊이로 절연을 제어하고 있다. 디바이스가 고집적화됨에 따라 절연기능을 강화시키기 위하여 트렌치의 깊이를 깊게 형성하는 경우 트렌치의 에스펙트비(Aspect ratio)가 증가함으로 트렌치를 매립하기 위한 절연물질의 매립 후에는 보이드(Void) 등의 결함이 발생할 가능성이 높아지게 된다. 이러한 결함이 후속의 CMP나 세정공정 등을 통해 발생하게 되면 배선의 쇼트(short) 등을 유발하게 되어 소자의 신뢰성을 저하시킨다. STI, which is currently used in ultra-high density devices, controls the isolation to the depth of the trench. If the depth of the trench is deeply formed to increase the insulation function as the device is highly integrated, the aspect ratio of the trench increases, so that defects such as voids after the filling of the insulating material to fill the trench It is more likely to occur. If such a defect is generated through a subsequent CMP or cleaning process, a short circuit or the like of the wiring is caused, thereby degrading the reliability of the device.
상기한 문제점을 해결하기 위한 본 발명의 목적은 STI와 LOCOS 공정을 접목시켜 얕은 트렌치의 깊이를 유지하면서도 절연기능을 증대시킴으로서 소자의 신뢰성을 향상시키도록 한 반도체소자 및 그 제조방법을 제공하는 데 있다.An object of the present invention to solve the above problems is to provide a semiconductor device and a method of manufacturing the same by combining the STI and LOCOS process to improve the reliability of the device by increasing the insulation function while maintaining the depth of the shallow trench. .
상기한 목적을 달성하기 위하여 본 발명에 따른 반도체소자는In order to achieve the above object, the semiconductor device according to the present invention
트렌치를 갖는 반도체기판;A semiconductor substrate having a trench;
상기 트렌치의 내측벽에 형성된 절연 스페이서;An insulating spacer formed on an inner wall of the trench;
상기 트렌치의 저면에 형성된 산화막: 및An oxide film formed on the bottom of the trench: and
상기 트렌치내에 채워져 상기 반도체기판과 평탄화된 절연막을 구비한다.An insulating film filled in the trench and the semiconductor substrate and the planarization insulating film;
상기 절연 스페이서는 실리콘질화막과 폴리실리콘막의 적층구조로 형성되어 있다.The insulating spacer is formed in a stacked structure of a silicon nitride film and a polysilicon film.
또한, 본 발명에 따른 반도체소자의 제조방법은In addition, the method of manufacturing a semiconductor device according to the present invention
반도체기판에 소정 깊이를 갖는 트렌치를 형성하는 공정;Forming a trench having a predetermined depth in the semiconductor substrate;
상기 트렌치의 내측벽에 절연 스페이서를 형성하는 공정;Forming an insulating spacer on an inner wall of the trench;
상기 트렌치의 저면에 산화막을 형성하는 공정; 및Forming an oxide film on the bottom of the trench; And
상기 트렌치내에 절연막을 채우고 이를 상기 반도체기판의 표면에 평탄화하는 공정을 포함한다.Filling the insulating film in the trench and planarizing it on the surface of the semiconductor substrate.
상기 절연 스페이서막은 실리콘질화막과 폴리실리콘막의 적층구조로 형성되어 있으며, 상기 절연막은 USG(Undoped Silicate Glass)막과 PE-TEOS막 또는 HDP(High Density Plasma막)과 PE-TEOS막이 적층되어 있다.The insulating spacer layer is formed of a stacked structure of a silicon nitride layer and a polysilicon layer, and the insulating layer is formed by stacking a USG (Undoped Silicate Glass) layer, a PE-TEOS layer, or an HDP (High Density Plasma layer) and a PE-TEOS layer.
상기와 같은 반도체소자 및 그 제조방법에 따르면, 반도체기판에 얕은 트렌치를 형성한 후, 트렌치의 내측벽에 절연 스페이서를 형성하고 트렌치의 저면에 산화막을 형성시킴으로서 트렌치의 깊이를 깊게 형성시키지 않고서도 트렌치의 절연기능을 향상시킬 수 있다.According to the semiconductor device and the manufacturing method as described above, after forming a shallow trench in the semiconductor substrate, by forming an insulating spacer on the inner wall of the trench and by forming an oxide film on the bottom of the trench, the trench is not formed deep. Can improve the insulation function.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자 및 그 제조방법에 대하여 상세하게 설명하면 다음과 같다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 은 본 발명에 따른 반도체소자의 트렌치 구조를 도시한 도면이다.1 is a view showing a trench structure of a semiconductor device according to the present invention.
반도체기판(10) 상에 실리콘질화막(14)의 패턴과 패드산화막(12)의 패턴이 적층된 마스크층이 형성되고, 마스크층의 개구부에 의해 노출된 반도체기판(10)에는 소정 깊이를 갖는 트렌치(18)가 형성되어 있다. 트렌치(18)의 내측벽에는 실리콘질화막(20)과 폴리실리콘막(22)의 적층구조로 이루어진 절연 스페이서(24)가 형성되어 있다.A mask layer in which the pattern of the silicon nitride film 14 and the pattern of the pad oxide film 12 are stacked is formed on the semiconductor substrate 10, and the trench having a predetermined depth is exposed in the semiconductor substrate 10 exposed by the opening of the mask layer. 18 is formed. An insulating spacer 24 having a stacked structure of the silicon nitride film 20 and the polysilicon film 22 is formed on the inner wall of the trench 18.
또한, 트렌치(18)의 저면에는 로코스 공정에 의해 산화막(26)이 형성되어 있으며, 트렌치(18) 내에는 USG막(28)과 PE-TEOS막(30)이 적층되고 평탄화되어 채워져 있다.In addition, an oxide film 26 is formed on the bottom of the trench 18 by a LOCOS process, and a USG film 28 and a PE-TEOS film 30 are stacked and planarized in the trench 18.
도 2 내지 도 8 은 본 발명에 따른 반도체 소자의 제조방법을 도시한 제조공정도이다.2 to 8 are manufacturing process diagrams showing a method of manufacturing a semiconductor device according to the present invention.
도 2를 참조하면, 먼저, 반도체기판(10) 상에 100Å ～ 120Å 두께 정도의 버퍼용 패드산화막(12)과 1800Å ～ 2200Å 두께 정도의 실리콘질화막(14)을 순차적으로 증착한다. 이어서, 트렌치의 형성을 위하여 실리콘질화막(14) 상에 감광막(16)의 패턴을 형성한다.Referring to FIG. 2, first, a buffer pad oxide film 12 having a thickness of about 100 kV to 120 kPa and a silicon nitride film 14 having a thickness of about 1800 kPa to 2200 kPa are sequentially deposited on the semiconductor substrate 10. Subsequently, a pattern of the photosensitive film 16 is formed on the silicon nitride film 14 to form a trench.
도 3을 참조하면, 그런 다음, 감광막(16)의 패턴을 마스크로 실리콘질화막(14)에서부터 순차적으로 식각하여 반도체기판(10)에 0.35μm 정도의 깊이를 갖는 트렌치(18)를 형성한다.Referring to FIG. 3, a trench 18 having a depth of about 0.35 μm is formed on the semiconductor substrate 10 by sequentially etching the silicon nitride film 14 using the pattern of the photosensitive film 16 as a mask.
도 4를 참조하면, 감광막(16)의 패턴을 제거한 후, 트렌치(18)의 내/외측 전면에 절연막으로서 50Å ～ 100Å 두께 정도의 실리콘질화막(20)과 폴리실리콘막(22)을 순차적으로 증착한다. 이 때, 실리콘질화막(20)은 후속 공정에서 트렌치(18)의 저면만을 산화시키기 위한 완충막의 역할을 한다.Referring to FIG. 4, after the pattern of the photosensitive film 16 is removed, a silicon nitride film 20 and a polysilicon film 22 having a thickness of about 50 to 100 microseconds are sequentially deposited as an insulating film on the inner / outer surface of the trench 18. do. At this time, the silicon nitride film 20 serves as a buffer film for oxidizing only the bottom surface of the trench 18 in a subsequent process.
또한, 폴리실리콘막(22)은 후속 공정의 측벽 스페이서를 형성하기 위한 식각공정을 진행할 때 실리콘질화막(20)을 보호하는 보호막의 역할을 함과 동시에 후속의 산화공정시에 트렌치(18)의 내부에 절연막을 형성시키게 된다.In addition, the polysilicon film 22 serves as a protective film to protect the silicon nitride film 20 during the etching process for forming the sidewall spacers of the subsequent process and at the same time the inside of the trench 18 during the subsequent oxidation process. An insulating film is formed in the film.
도 5를 참조하면, 이어서, 트렌치(18)의 내/외측 전면에 형성되어 있는 실리콘질화막(20)과 폴리실리콘막(22)에 에치-백 공정을 트렌치(18)의 저면이 노출될 때까지 실시한다. 따라서, 트렌치(18)의 측벽에 실리콘질화막(20)과 폴리실리콘막(22)으로 이루어진 절연 스페이서(24)가 형성된다.Referring to FIG. 5, an etch-back process is then performed on the silicon nitride film 20 and the polysilicon film 22 formed on the inner and outer front surfaces of the trench 18 until the bottom surface of the trench 18 is exposed. Conduct. Thus, an insulating spacer 24 made of a silicon nitride film 20 and a polysilicon film 22 is formed on the sidewall of the trench 18.
도 6을 참조하면, 절연 스페이서(24)를 형성한 후, 로코스(LOCOS) 공정을 실시하여 트렌치(18)의 저면에 산화막(26)을 형성한다. 이 때, 트렌치(18) 측벽의 반도체기판(10)은 트렌치(18)의 측벽 상의 실리콘질화막(20)에 의해 산화가 진행되지 않는다.Referring to FIG. 6, after forming the insulating spacer 24, an oxide film 26 is formed on the bottom surface of the trench 18 by performing a LOCOS process. At this time, the semiconductor substrate 10 on the sidewalls of the trench 18 is not oxidized by the silicon nitride film 20 on the sidewalls of the trench 18.
도 7을 참조하면, 트렌치(18)를 채우기 위해 상기 구조물의 전면에 3600Å ～ 4400Å 두께 정도의 USG막(28)과 1800Å ～ 2200Å 두께 정도의 PE-TEOS막(30)을 순차적으로 증착한다.Referring to FIG. 7, in order to fill the trench 18, a USG film 28 having a thickness of about 3600 mm to 4400 mm and a PE-TEOS film 30 having a thickness of about 1800 mm to 2200 mm are sequentially deposited on the front surface of the structure.
이때, USG막(28)을 대체하여 HDP막을 형성하여도 무방하다. 여기서, 트렌치(18) 상에 USG막(28)과 PE-TEOS막(30)을 순차적으로 증착하는 이유는 박막의 단차 개선 및 조밀도를 향상시키기 위함이다.At this time, the HDP film may be formed in place of the USG film 28. The reason why the USG film 28 and the PE-TEOS film 30 are sequentially deposited on the trench 18 is to improve the level difference and the density of the thin film.
도 8을 참조하면, 트렌치(18) 상에 USG막(28)과 PE-TEOS막(30)을 CMP공정으로 트렌치(18) 외측의 실리콘질화막(14)이 노출될 때까지 순차적으로 연마하여 평탄화시킨 다음, 후속의 반도체 제조공정을 진행한다.Referring to FIG. 8, the USG film 28 and the PE-TEOS film 30 are sequentially polished on the trench 18 until the silicon nitride film 14 outside the trench 18 is exposed by a CMP process. After that, the subsequent semiconductor manufacturing process is performed.
따라서, STI에 LOCOS 공정을 접목시켜 얕은 트렌치의 깊이를 유지하면서도 트렌치의 절연기능을 증대시킬 수 있으므로 트렌치의 깊이를 깊게 형성하는 경우 트렌치의 에스펙비가 증가하여 후속공정의 CMP 또는 세정공정을 통해 발생되는 보이드와 같은 결함 발생을 방지할 수 있다.Therefore, by incorporating LOCOS process into STI, it is possible to increase the insulation function of the trench while maintaining the depth of the shallow trench. Therefore, when the depth of the trench is deeply formed, the specp ratio of the trench is increased and it is generated through the CMP or cleaning process of the subsequent process. The occurrence of defects such as voids can be prevented.
이상에서와 같이 본 발명에 따르면, 반도체기판에 얕은 트렌치를 형성한 후 트렌치의 내/외측에 실리콘질화막과 폴리실리콘막의 적층구조로 이루어진 절연막을 형성하고 이를 에치-백 공정으로 식각하여 트렌치의 내측벽에 절연 스페이서를 형성한 다음, 트렌치의 저면에 산화막을 형성시킨다.As described above, according to the present invention, after forming a shallow trench in a semiconductor substrate, an insulating film made of a laminated structure of a silicon nitride film and a polysilicon film is formed on the inside / outside of the trench and etched by an etch-back process to form an inner wall of the trench. An insulating spacer is formed in the trench, and then an oxide film is formed on the bottom of the trench.
따라서, 본 발명은 얕은 트렌치의 깊이를 유지하면서 트렌치 내의 보이드 발생을 방지하여 트렌치의 절연기능을 증대시킬 수 있어 소자의 신뢰성을 향상시킨다.Therefore, the present invention can increase the insulation function of the trench by preventing voids in the trench while maintaining the depth of the shallow trench, thereby improving the reliability of the device.
도 1 은 본 발명에 따른 반도체소자의 트렌치 구조를 도시한 도면1 illustrates a trench structure of a semiconductor device according to the present invention.
도 2 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 제조공정도2 to 8 are manufacturing process diagrams showing a method for manufacturing a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체기판 12 : 패드산화막10 semiconductor substrate 12 pad oxide film
14, 20 : 실리콘질화막 16 : 감광막14, 20: silicon nitride film 16: photosensitive film
18 : 트렌치 22 : 폴리실리콘막18: trench 22: polysilicon film
24 : 절연 스페이서 26 : 산화막24: insulating spacer 26: oxide film
28 : USG막 30 : PE-TEOS막 28: USG film 30: PE-TEOS film
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|---|---|---|---|---|
| KR950021382A (en) * | 1993-12-29 | 1995-07-26 | 김주용 | Separator Formation Method of Semiconductor Device |
| KR970030630A (en) * | 1995-11-06 | 1997-06-26 | 김주용 | Device Separation Method of Semiconductor Device |
| KR970053450A (en) * | 1995-12-27 | 1997-07-31 | 김주용 | Device Separation Method of Semiconductor Device |
| KR19980065504A (en) * | 1997-01-10 | 1998-10-15 | 김광호 | Trench element isolation |
| KR19980083835A (en) * | 1997-05-19 | 1998-12-05 | 윤종용 | Device Separation Method of Semiconductor Device |
| KR19990039742A (en) * | 1997-11-14 | 1999-06-05 | 구본준 | Device isolation method of semiconductor device |
| KR20010056443A (en) * | 1999-12-15 | 2001-07-04 | 박종섭 | Isolation method for semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR950021382A (en) * | 1993-12-29 | 1995-07-26 | 김주용 | Separator Formation Method of Semiconductor Device |
| KR970030630A (en) * | 1995-11-06 | 1997-06-26 | 김주용 | Device Separation Method of Semiconductor Device |
| KR970053450A (en) * | 1995-12-27 | 1997-07-31 | 김주용 | Device Separation Method of Semiconductor Device |
| KR19980065504A (en) * | 1997-01-10 | 1998-10-15 | 김광호 | Trench element isolation |
| KR19980083835A (en) * | 1997-05-19 | 1998-12-05 | 윤종용 | Device Separation Method of Semiconductor Device |
| KR19990039742A (en) * | 1997-11-14 | 1999-06-05 | 구본준 | Device isolation method of semiconductor device |
| KR20010056443A (en) * | 1999-12-15 | 2001-07-04 | 박종섭 | Isolation method for semiconductor devices |
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