KR100532202B1 - Method for forming a capacitor - Google Patents

Abstract

In the cylindrical capacitor manufacturing method, first, a first mold film, a second mold film, a support film, and a third mold film, which are superior in etching resistance by the wet cleaning liquid, are formed on the substrate. The films are sequentially etched to form openings. A cylindrical storage electrode is formed on an inner surface of the opening. The third mold film and the support film are partially removed to form a support film pattern. The second mold layer is first etched using a first etchant having an etching selectivity ratio between the second mold layer and the support layer pattern higher than 70: 1. The etching selectivity between the first mold layer and the support layer pattern is maintained using a second etching solution that satisfies a condition higher than the etching selectivity between the second mold layer and the support layer pattern etched by the first etching solution. The mold layers are secondarily etched. A dielectric film and a plate electrode are formed on the storage electrode. According to the method, the consumption of the support layer pattern can be reduced to improve the stability of the storage node electrode of the capacitor.

Description

Method for forming a capacitor

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing a capacitor of a cylindrical shape.

Generally, semiconductor devices for memory, such as DRAM devices, store information such as data or program instructions, and may read information stored therein and store other information in the device. One memory device usually consists of one transistor and one capacitor. Typically, a capacitor included in a DRAM device or the like is composed of a storage electrode, a dielectric film, a plate electrode, and the like. In order to improve the capacity of a memory device including such a capacitor, it is very important to increase the capacitance of the capacitor.

Currently, in order to secure the capacitance of the capacitor while decreasing the allowable area per unit cell as the degree of integration of the DRAM device increases above the giga level, the capacitor is initially manufactured in a flat structure, and gradually becomes a box or cylinder shape. Formed.

Examples of such cylindrical capacitors are disclosed in US Pat. No. 6,228,736 (issued to Lee et al), US Pat. No. 6,080,620 (issued to Jeng), and the like. However, when the height of the cylindrical capacitor is simply increased, the storage electrode of the capacitor is inclined or falls down during the manufacture of the capacitor. In particular, in the case of a cylindrical type, the situation occurs more frequently. This is because the cylindrical capacitor is somewhat weak in height.

Accordingly, in recent years, the upper portion of the storage electrode of the cylindrical capacitor has been manufactured in a form in which the structure is reinforced.

An example of a cylindrical capacitor of the type which reinforces the substructure is disclosed in Japanese Patent Laid-Open No. 13-57413.

1 is a cross-sectional view schematically showing the structure of a storage electrode of a conventional cylindrical capacitor.

Referring to FIG. 1, as a storage electrode 10 of a cylindrical capacitor formed on a substrate 15, the storage electrode 10 is a contact plug 11 formed by an insulating film pattern 17 and the contact. It has a node 13 connected with a plug 11. In addition, although not shown, there is a pad connected to the contact plug 11 under the contact plug 11.

Here, the node 13 of the storage electrode 10 is divided into an upper node 13a and a lower node 13b based on the line width. In this case, the node 10 of the storage electrode 10 has a structure in which the line width CD2 of the lower node 13b is larger than the line width CD1 of the upper node 13a.

As such, by forming the line width CD2 of the lower node 13b to be somewhat larger than the line width CD1 of the upper node 13a, a weak structure according to the height of the cylindrical capacitor may be partially overcome.

As an example of another method for preventing the 2-bit short circuit, a method of forming a mesh-like support layer pattern for improving structural stability of the capacitors by mutually supporting the capacitors has been developed. It is becoming.

Briefly describing the method, first, the mold film structure for forming the storage electrode of the capacitor is composed of a first mold film, a second mold film, a support film and a third mold film. The second mold layer is formed of a film having better etching resistance by the wet cleaning liquid than the first mold layer. By forming the second mold film, it is possible to prevent the inlet portion of the opening formed in the subsequent step from being too wide.

After forming an opening for forming a capacitor in the mold layer structure, a storage electrode is formed on an inner surface of the opening. The third mold layer is removed and the support layer is partially etched to form a support layer pattern. Thereafter, the mold layer structure is completely removed through a lift off process.

When removing the mold layer structure, the support layer pattern should be etched under the condition that the support layer pattern is hardly etched. When the support layer pattern is also removed when the mold layer structure is removed, the support layer pattern becomes too thin or disappears and thus cannot support the storage electrode.

However, typically, the etching rate of the first mold layer and the second mold layer is slightly different when the same etching solution is used. In addition, each of the first mold layer and the second mold layer has a difference in etching selectivity from the support layer pattern which is typically made of silicon nitride.

Therefore, the combination of thicknesses of the first mold film and the second mold film is restricted. For example, when the etching selectivity between the first mold layer and the support layer pattern is lower than the etching selectivity between the second mold layer and the support layer pattern during the lift-off process, the first etchant is used. While the first mold film is removed, a substantial portion of the support film pattern is also removed, so that the line width of the mesh connection portion of the support film becomes too thin. Therefore, in order to use the first etchant, the first mold layer must be formed as thin as possible.

On the other hand, when the etching selectivity between the first mold layer and the support layer pattern is higher than the etching selectivity between the second mold layer and the support layer pattern during the lift-off process, While the first mold film is removed, a substantial portion of the support film is also removed so that the line width of the mesh connection portion of the support film pattern becomes too thin. Therefore, in order to use the second etchant, the first mold layer must be formed thicker.

As described above, as the combination of thicknesses of the first mold layer and the second mold layer is restricted, a problem such as the inability to increase the cylindrical capacitor storage electrode to a desired height occurs.

Accordingly, it is an object of the present invention to provide a cylindrical capacitor manufacturing method having a mesh-like support film pattern and not being limited by the height.

In order to achieve the above object, according to an embodiment of the present invention, first, the first mold film, the second mold film, the support film and the first excellent in the etching resistance by the wet cleaning liquid compared to the first mold film 3 A mold film is formed. The third mold film, the support film, the second mold film, and the first mold film are sequentially etched to form openings. A conductive layer is formed on the inner surface of the opening to form a cylindrical storage electrode. The third mold layer and the support layer are partially removed to form a support layer pattern that surrounds the storage electrode and is connected to neighboring storage electrodes. The second mold layer is first etched using a first etchant having an etching selectivity ratio between the second mold layer and the support layer pattern higher than 70: 1. The etching selectivity between the first mold layer and the support layer pattern is maintained using a second etching solution that satisfies a condition higher than the etching selectivity between the second mold layer and the support layer pattern etched by the first etching solution. The mold layers are secondarily etched. A dielectric film is formed on the storage electrode. Subsequently, a plate electrode is formed on the dielectric layer to complete the capacitor.

As described above, by performing the lift-off process by two etching processes in consideration of the etching characteristics of the first mold film and the second mold film, thickness constraints of the first mold film and the second mold film may be avoided. Therefore, the cylindrical capacitor storage electrode can be formed at a desired height.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 6, 8 to 13 and 15 are cross-sectional views for explaining a method of manufacturing a DRAM device according to an embodiment of the present invention. 2 to 6, 8 and 10 are cross-sectional views taken along the line I_I 'in FIG. 7, and FIGS. 9, 11 to 13 and 14 are cross-sectional views taken along the line II_II' in FIG. 7.

7 and 14 are plan views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention.

Referring to FIG. 2, the device isolation layer 103 is formed on the semiconductor substrate 100 by using a device isolation process such as a shallow trench device isolation (STI) process or a silicon partial oxidation method (LOCOS). ) Is divided into an active region and a field region.

Subsequently, a thermal oxidation method or a chemical vapor deposition (CVD) process is performed on the semiconductor substrate 100 on which the device isolation film 103 is formed to form a gate oxide film 106 having a thin thickness. Gate conductive layer patterns 109 and first hard mask patterns 112 are formed on the gate oxide layer 106. Hereinafter, the stacked structure of the gate oxide film 106, the gate conductive film pattern 109, and the first hard mask pattern 112 will be described as a gate structure 115. The gate structure 115 is formed in a line shape.

After silicon nitride is formed on the semiconductor substrate 100 on which the gate structures 115 are formed, the silicon nitride is anisotropically etched to form gate spacers 118 as gate spacers on sidewalls of the gate structures 115. do.

Using the gate structures 115 as an ion implantation mask, impurities are implanted and heat-treated in the semiconductor substrate 100 exposed between the gate structures 115, so that the source / drain regions 124 are formed on the semiconductor substrate 100. 121).

By performing the above processes, transistors are completed in the semiconductor substrate 100. The line type gate electrode is commonly used as a word line. The source / drain regions 124 and 121 are defined by the operating mode of the transistor. However, hereinafter, a portion electrically connected to the bit line will be referred to as a source region 124 and a portion electrically connected to the capacitor will be described as a drain region 121 for convenience.

A first interlayer insulating layer 130 made of silicon oxide is formed on the entire surface of the semiconductor substrate 100 on which the transistors are formed. The first interlayer insulating layer 130 is partially etched to form first contact holes (not shown) that expose the source and drain regions. Subsequently, a conductive material is filled in the first contact holes to form pad contacts 133.

A second interlayer insulating layer 139 is formed on the first interlayer insulating layer 130. The second interlayer insulating layer 139 is etched to form a second contact hole (not shown) that is electrically connected to the pad contact 133 in contact with the source region 124. A conductive material is deposited on the inside of the second contact hole and the upper surface of the second interlayer insulating layer 139 and then patterned to form bit lines (not shown) and bit line contacts (not shown).

A third interlayer insulating layer 154 is formed on the second interlayer insulating layer 139 while filling the bit line. Next, the third interlayer insulating layer 154 and the second interlayer insulating layer 139 are partially etched to form third contact holes (not shown) that expose the pad contact 133 connecting to the drain region. . The storage node contact 157 is formed by filling the third contact holes with a conductive material. Subsequently, although not shown, a pad pattern may be further formed on the storage node contact 157 to define a formation region of the storage node electrode.

Next, a silicon nitride layer is formed as an etch stop layer 163 on the storage node contact 157 and the third interlayer insulating layer 154.

Referring to FIG. 3, a first mold layer 170 is formed on the etch stop layer 163, and a wet cleaning solution is formed on the first mold layer 170 in comparison with the first mold layer 170. The second mold layer 172 having excellent etching resistance is formed. The first mold layer 170 and the second mold layer 172 are formed of a silicon oxide insulating material.

For example, the first mold layer 170 may be formed of a BPSG layer or a USG layer, and the second mold layer 172 may be formed of a PE-TEOS layer.

The first mold layer 170 and the second mold layer 172 are films for molding a cylindrical storage electrode. In this case, the second mold layer 172 for forming the upper portion of the storage electrode is used as a film having excellent etching resistance due to the wet cleaning liquid compared to the first mold layer 170, so that the upper portion of the storage electrode is too wide. And a storage electrode having an overall stable structure can be formed. A description thereof will be described later in more detail.

In addition, the sum of the thicknesses of the first mold layer 170 and the second mold layer 172 determines the height of the cylindrical storage electrode. Therefore, the sum of the thicknesses of the first mold layer 170 and the second mold layer 172 may be appropriately adjusted according to the capacitance required by the capacitor. In the recent DRAM device, the sum of the thicknesses of the first mold layer 170 and the second mold layer 172 has a thickness of about 10000 to 20,000 kPa.

A support layer 174 is formed on the second mold layer 172 to form a support layer pattern for connecting the cylindrical storage electrodes to each other. The support layer 174 may be formed of silicon nitride, which is a material having a high etching selectivity between the first mold layer 170 and the second mold layer 172 made of the silicon oxide-based material. The support film is formed to a thickness of 100 to 1000Å.

Subsequently, a third mold layer 176 is formed on the support layer 174. The third mold layer 176 may be formed to have a thickness of about 1,000 to 6,000 mm 3 from the second mold layer 172.

A second hard mask pattern 178 is formed on the third mold layer 176 to expose an opening portion for forming a cylindrical storage electrode. The second hard mask pattern 178 may be formed of a material having a high etching selectivity with respect to the first to third mold layers 170, 172, and 176. For example, the second hard mask pattern 178 may be formed of polysilicon.

Referring to FIG. 4, the third mold layer 176, the support layer 174, the second mold layer 172, and the first mold layer 170 using the second hard mask pattern 178 as an etching mask. By sequentially etching to form a preliminary opening (not shown) that exposes the top surface of the storage node contact.

Subsequently, the opening 180 for forming the cylindrical storage electrode is formed by cleaning the surface of the preliminary opening (not shown). The cleaning process is performed using a wet cleaning liquid. As the first and second mold layers 170 and 172 are partially removed by the wet cleaning liquid, the opening 180 becomes larger in size than the preliminary opening. . However, since the second mold layer 172 having high etching resistance is removed smaller than the first mold layer 170, the inlet portion of the opening 180 to be formed is not excessively increased. Therefore, as the opening width of the inlet portion of the opening 180 is increased, the short circuit of the storage node electrodes formed in a subsequent process may be minimized. In addition, the structure of the storage node electrode formed by the subsequent process is stabilized.

Referring to FIG. 5, a conductive layer for a storage node electrode (not shown) is formed on a sidewall, a bottom surface of the opening 180, and an upper surface of the remaining second hard mask pattern (not shown). The conductive layer for the storage node electrode may be formed of polysilicon doped with impurities.

A sacrificial layer 184 is formed on the conductive layer for the storage node electrode to sufficiently fill the opening 180. The sacrificial layer 184 may be formed of a silicon oxide based material, for example, a BPSG film or a USG film.

Subsequently, a planarization process is performed to remove the second hard mask pattern and the conductive layer for the storage node electrode formed on the top surface of the third mold layer 176, thereby forming the conductive layer only on the inner surface of the opening 180. To form the storage electrode 182.

Referring to FIG. 6, after the storage electrode 182 is formed, the third mold layer 176 is removed by performing a wet etching process. When the wet etching process is performed, an upper surface of the support layer 174 is exposed. In addition, an upper portion of the sacrificial layer 184 formed inside the opening is also removed.

7 is a plan view showing the arrangement of the storage electrodes.

The storage electrodes 182 are regularly arranged in an oblique direction. In addition, referring to one storage electrode 182a and looking at neighboring storage electrodes, while there is a storage electrode 182b relatively close to the reference storage electrode 182a, the reference storage electrode 182a There is a storage electrode 182c that is relatively far from. Hereinafter, one direction connecting the storage electrodes having relatively close distances between neighboring storage electrodes is referred to as a first direction I-I ', and the storage electrodes having relatively close distances between the neighboring storage electrodes are connected. Either direction is described as 2nd direction II-II '.

8 and 9 are cross-sectional views cut in the second direction and the first direction, respectively, in the same process.

8 and 9, a mask oxide layer (not shown) is formed on the exposed storage electrode 182, the support layer 174, and the surface of the sacrificial layer 184. The mask oxide film may be formed using an APCVD process having a strong underlying film dependency.

The mask oxide layer is disposed in the second direction II-II 'while the gap region (see FIG. 9) between the storage electrodes 182 disposed in the first direction I-I' is completely filled. The gap region (see FIG. 8) between the storage electrodes 182 is formed to be partially filled along the profile of the gap.

Next, the mask oxide film is anisotropically etched to form a spacer-shaped third mask pattern 186 on the upper sidewall of the storage electrode.

At this time, since the mask oxide film is completely filled in the gap between the storage electrodes 182 arranged in the first direction, the third mask pattern 186 in the gap does not have a spacer shape. On the other hand, the gap between the storage electrodes arranged in the second direction and the mask oxide film formed on the sacrificial layer 184 are etched anisotropically to form a spacer-shaped third mask pattern 186. Accordingly, the support layer 174 is exposed at the gap between the storage electrodes 182 disposed in the second direction, and the third portion is disposed at the gap between the storage electrodes 182 arranged in the first direction. Since the mask pattern is formed, the support layer 174 is not exposed to the outside.

10 and 11 are cross-sectional views cut in the first direction and the second direction, respectively, in the same process.

10 and 11, the exposed support layer 174 may be selectively removed to form a support layer pattern 174a that connects the storage electrodes 182 disposed in the first direction to each other. The support layer pattern 174a has a mesh shape that surrounds the storage electrode 182 and connects the storage electrodes 182 disposed in the first direction to each other.

As the support layer pattern 174a is formed, the storage electrodes 182 are supported by each other to be structurally stable, thereby minimizing the fall or inclination of the storage electrode 182.

Referring to FIG. 12, the second mold layer 172 and the sacrificial layer 184 are first etched. When performing the first etching process, a first etching solution having an etching selectivity between the second mold layer 172 and the support layer pattern 174a is higher than 70: 1.

For example, when the second mold layer 172 is formed of a PE-TEOS layer, a mixed solution of HF, NHF ₄ and water may be used as the first etching solution. Specifically, the first etching solution is preferably composed of the NHF ₄ 17% by volume (%) or more. Examples of the first etchant that can be used include NHF ₄ , HF and water with high selective silicon nitride etchant (HSSE) having a volume ratio of 18: 4.5: 77.5, and NHF ₄ , HF and water with 17: 0.7: And LAL200 solution having a volume ratio of 82.3, NHF ₄ , HF and water having a volume ratio of 25: 2.5: 77.5.

When the etching process is performed using the HSSE, the etching rate of the PE-TEOS film is about 3396Å / min, the BPSG film is about 2158Å / min, and the SiN film is about 40Å / min. min.

In the first etching process, only the second mold layer 172 may be completely removed. However, even if some of the first mold layer 170 is removed or some of the second mold layer 172 remains in the first etching process, the same effect may be obtained.

Referring to FIG. 13, an etch selectivity between the first mold layer 170 and the support layer pattern 174a is between the second mold layer 172 and the support layer pattern 174a etched by the first etchant. The remaining mold film and the sacrificial layer 184 are secondaryly etched using a second etchant that satisfies a condition higher than the etching selectivity. In detail, when the secondary etching process is performed, a second etching solution having an etching selectivity between the first mold layer 170 and the support layer pattern 174a is greater than 90: 1.

For example, when the first mold layer 170 is formed of a BPSG layer, a mixed solution in which HF and water are mixed may be used as the second etching solution. Specifically, the second etchant is preferably such that the water and HF is 5: 1 volume ratio or more. In other words, the HF is preferably composed of a volume of 16% or more in the second etching solution.

When the remaining mold layer and the sacrificial layer 184 are removed in the secondary etching process, an outer surface of the cylindrical storage electrode is exposed.

14 is a plan view illustrating a storage electrode on which a support layer pattern is formed. When the above processes are completed, the storage electrode having the mesh-like support layer pattern formed thereon may be completed.

As described above, the etching process is performed twice in consideration of the etching characteristics of each of the first mold layer 170 and the second mold layer 172, thereby forming the first mold layer 170 and the second mold layer. When removing 172, the inevitable etching of the support layer pattern 174a by the etching process may be minimized. In addition, it is possible to minimize the reduction in the line width (D) of the mesh wing portion of the support layer pattern 174a.

In addition, since the amount of etching of the support layer pattern 174a may be minimized due to the thicknesses of the first mold layer 170 and the second mold layer 172, the thickness of the first mold layer 170 may be reduced. The thickness of the second mold film 172 does not have to be restricted.

Referring to FIG. 15, a dielectric layer 190 is formed on the surface of the storage electrode 182 and the surface of the support layer pattern 174a. Subsequently, a plate electrode 192 is formed on the dielectric layer 190.

By the above process, it is possible to form a DRAM device including a storage electrode having a high capacity while preventing the storage electrode from falling or tilting.

Comparison data 1

FIG. 16 is a graph showing a consumption amount of a silicon nitride film when the lift-off process is performed by one wet etching by a conventional method.

Specifically, a BPSG film is formed on the substrate as a first mold oxide film, a PE-TEOS film is formed as a second mold oxide film, and a support film pattern made of silicon nitride is formed on the PE-TEOS film. At this time, the sum of the thicknesses of the BPSG film and the PE-TEOS film is fixed at 20000Å, and is formed by changing the thicknesses of the BPSG film and the PE-TEOS film, respectively. In addition, the etching amount of the support membrane pattern in the case of using different wet etchant for each of the above structures was obtained by calculation and represented by a graph. In this case, the etching amount of the support layer pattern is an etching amount when the BPSG film and the PE-TEOS film are excessively etched by about 40%.

The etching rate (Å / min) of each wet etchant used is shown in Table 1.

             Etch Rate (Å / min) PE-TEOS membrane BPSG film SiN film LAL 500 975 580 12 HSSE 3396 2158 40 HF Diluent 1750 4830 47

In FIG. 16, reference numeral 200 denotes the thickness of the silicon nitride film consumed when LAL 500 is used as an etchant, and reference numeral 202 denotes the thickness of the silicon nitride film consumed when HSSE is used as an etchant, and reference numeral 204 is diluted. The thickness of the silicon nitride film consumed when the prepared HF is used as an etching solution is shown.

As shown in FIG. 16, even when the same etchant is used, the silicon nitride film consumed by wet etching is very different depending on the thickness of the BPSG film and the PE-TEOS film. In addition, even if the thickness of the BPSG film and PE-TEOS film is the same, if the wet etching solution is different, the silicon nitride film consumed is very different. Furthermore, in order to keep the line width of the wing portion of the mesh 40 nm or more, the consumption of the silicon nitride film is preferably 380 kPa or less. Reference numeral 206 denotes a leader line of which the consumption of the silicon nitride film is 380 kPa, and as shown, the thickness of the BPSG film and the PE-TEOS film having a consumption of the silicon nitride film of 380 kPa or less is very limited.

Comparison data 2

17 is a graph showing the consumption amount of silicon nitride film when the lift-off process is performed by two wet etching processes by the method of the present invention.

Specifically, a BPSG film is formed on the substrate as a first mold oxide film, a PE-TEOS film is formed as a second mold oxide film, and a support film pattern made of silicon nitride is formed on the PE-TEOS film. At this time, the sum of the thicknesses of the BPSG film and the PE-TEOS film is fixed at 20000Å, and is formed by changing the thicknesses of the BPSG film and the PE-TEOS film, respectively.

In addition, the PE-TEOS film was firstly etched using HSSE, and the etching amount of the support film pattern when the BPSG was secondly etched using HF dilution was obtained by calculation, and is represented by a graph. The etching amount of the silicon nitride film in the graph (FIG. 17) is the etching amount of the silicon nitride film in the case of excessive etching for about 2 minutes during the secondary etching.

As shown by reference numeral 300 of FIG. 17, the difference in thickness of the silicon nitride film consumed according to the thickness of the BPSG film and the PE-TEOS film hardly occurs. Moreover, no matter what thickness combination the BPSG film and the PE-TEOS film have, the silicon nitride film is consumed to a thickness of 350 kPa or less. Here, reference numeral 302 denotes a leader line whose consumption amount of the silicon nitride film is 380 kPa. Therefore, when the lift-off process is performed twice as described above, the line width of the blade portion of the mesh remains 40 nm or more.

As described above, according to the present invention, by performing the lift-off process by two etching processes in consideration of the etching characteristics of the first mold film and the second mold film, the thickness constraints of the first mold film and the second mold film can be avoided. Can be. Therefore, the cylindrical storage electrode can be formed at a desired height, thereby increasing the capacitance of the capacitor. In addition, since the support layer pattern is hardly removed by the lift-off process, stability of the storage node electrode of the capacitor may be improved. For this reason, the reliability improvement, the yield improvement, etc. of a semiconductor device can be anticipated.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1 is a cross-sectional view schematically showing the structure of a storage electrode of a conventional cylindrical capacitor.

2 to 6, 8 to 13 and 15 are cross-sectional views for explaining a method of manufacturing a DRAM device according to an embodiment of the present invention.

7 and 14 are plan views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention.

FIG. 16 is a graph showing a consumption amount of a silicon nitride film when the lift-off process is performed by one wet etching by a conventional method.

17 is a graph showing the consumption amount of silicon nitride film when the lift-off process is performed by two wet etching processes by the method of the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 163 etch stop film

170: first mold film 172: second mold film

174a: support film pattern 176: third mold film

180: opening 182: storage electrode

184: sacrificial layer 186: third mask pattern

190 dielectric film 192 plate electrode

Claims (9)

Forming a first mold film, a second mold film, a support film, and a third mold film on the substrate, which are superior in etching resistance by a wet cleaning liquid compared to the first mold film; Sequentially etching the third mold film, the support film, the second mold film, and the first mold film to form an opening; Forming a conductive layer on the inner surface of the opening to form a cylindrical storage electrode; Partially removing the third mold layer and the support layer to form a support layer pattern surrounding the storage electrode and connected to a neighboring storage electrode; First etching the second mold layer using a first etchant having an etching selectivity between the second mold layer and the support layer pattern higher than 70: 1; The etching selectivity between the first mold layer and the support layer pattern is maintained using a second etching solution that satisfies a condition higher than the etching selectivity between the second mold layer and the support layer pattern etched by the first etching solution. Secondary etching the mold layers; Forming a dielectric layer on the storage electrode; And Forming a plate electrode on the dielectric layer. The method of claim 1, wherein the first mold film is a BPSG film or a USG film. The method of claim 2, wherein the second etchant is a mixture of water and HF. The method of claim 3, wherein water and HF are mixed in a volume ratio of 5: 1 or more in the second etching solution. The method of claim 2, wherein the second mold film is made of a P_TEOS film. The method of claim 5, wherein the first etchant is a mixture of HF, NH ₄ F, and water. The method of claim 6, wherein the NH ₄ F in the first etchant comprises 17 volume percent or more. The method of claim 1, further comprising forming a sacrificial layer filling the opening after forming the storage electrode. The method of claim 8, wherein the sacrificial layer is made of a BPSG film or a USG film.