KR100520177B1 - A method for forming a field oxide of semiconductor device - Google Patents
A method for forming a field oxide of semiconductor device Download PDFInfo
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- KR100520177B1 KR100520177B1 KR10-2003-0043730A KR20030043730A KR100520177B1 KR 100520177 B1 KR100520177 B1 KR 100520177B1 KR 20030043730 A KR20030043730 A KR 20030043730A KR 100520177 B1 KR100520177 B1 KR 100520177B1
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910019142 PO4 Inorganic materials 0.000 claims abstract description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims abstract description 3
- 239000010452 phosphate Substances 0.000 claims abstract description 3
- 230000007547 defect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 소자분리영역과 활성영역 경계부에 유발되는 턱짐현상 ( moat ) 을 억제하기 위하여, 패드산화막이 형성된 반도체기판을 식각하여 소자분리용 트렌치를 형성하고 상기 소자분리용 트렌치 표면에 측벽 산화막을 형성한 다음, 전체표면상부에 측벽 질화막을 형성하고 상기 트렌치를 매립하는 소자분리용 산화막을 전체표면상부에 형성한 다음, 상기 측벽 질화막을 노출시키는 평탄화식각을 실시하고 상기 패드산화막 상부로 노출된 측벽 질화막을 제거하여 상기 패드산화막을 노출시킨 다음, 상기 노출된 패드산화막을 제거하여 반도체기판의 표면을 노출시키는 동시에 상기 반도체기판 상부로 돌출된 소자분리용 산화막과 그 측벽에 구비되는 측벽 질화막을 남기고 상기 반도체기판 표면에 스크린 산화막을 형성한 다음, 상기 측벽 질화막을 인산용액으로 제거하여 평탄화된 소자분리막을 형성하는 구성으로 턱짐 현상이 유발되지 않는 평탄화된 소자분리막을 형성하여 후속 공정으로 용이하게 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, in order to suppress the mow caused by the boundary between the device isolation region and the active region, to form a trench for device isolation by etching the semiconductor substrate on which the pad oxide film is formed; After forming a sidewall oxide film on the surface of the trench for isolation, a sidewall nitride film is formed over the entire surface, and a device isolation oxide film for filling the trench is formed over the entire surface, and then the planarization etching exposing the sidewall nitride film is performed. And removing the sidewall nitride film exposed to the upper portion of the pad oxide film to expose the pad oxide film, and then removing the exposed pad oxide film to expose the surface of the semiconductor substrate and simultaneously protruding the device isolation oxide film to the upper portion of the semiconductor substrate. Leaving a sidewall nitride film provided on the sidewalls and After the screen oxide film is formed, the sidewall nitride film is removed with a phosphate solution to form a planarized device isolation film, thereby forming a planarized device isolation film that does not cause a jaw phenomenon. It is a technology that can improve reliability.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 활성영역과 소자분리영역의 경계부에 턱짐 ( moat ) 현상이 유발되지 않도록 하여 소자의 전기적 특성 및 동작 특성을 향상시킬 수 있는 기술에 관한 것이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a technology capable of improving electrical and operating characteristics of a device by preventing moat from occurring at the boundary between the active region and the device isolation region. .
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘 기판 상부에 산화막, 다결정실리콘층, 질화막 순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional methods for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film stacked on top of a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그 중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the devices.
그리고, 상기 PBL 을 사용하는 경우, 필드 산화시 산소의 측면 확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속 공정에 어려움을 준다. 그리고, 기판 상부의 다결정실리콘층으로 인하여 필드산화시 기판 내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the PBL, buzz big occurs due to lateral diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing reliability compared to the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속 공정을 어렵게 하는 단점이 있다. The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속 공정을 용이하게 실시할 수 있도록 하였다. In order to solve this drawback, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다. 1A to 1D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(11) 상부에 패드산화막(13)을 형성하고, 상기 패드산화막(13) 상부에 질화막(15)을 형성한다. Referring to FIG. 1A, the pad oxide layer 13 is formed on the semiconductor substrate 11, and the nitride layer 15 is formed on the pad oxide layer 13.
그리고, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 질화막(15)과 패드산화막(13) 및 일정두께의 반도체기판(11)을 식각하여 상기 반도체기판(11)에 트렌치(17)를 형성한다.In addition, the trench 17 is formed in the semiconductor substrate 11 by etching the nitride layer 15, the pad oxide layer 13, and the semiconductor substrate 11 having a predetermined thickness by an etching process using an element isolation mask (not shown). do.
도 1b를 참조하면, 상기 트렌치(17) 표면을 열산화시켜 열산화막(도시안됨)을 형성하고 이를 제거하여 트렌치 표면의 결함을 제거한다. Referring to FIG. 1B, the surface of the trench 17 is thermally oxidized to form a thermal oxide film (not shown), thereby removing defects on the surface of the trench.
상기 트렌치(17) 표면에 측벽 산화막(19)을 형성하고 전체표면상부에 측벽 질화막(21)을 형성한다. A sidewall oxide film 19 is formed on the trench 17 and a sidewall nitride film 21 is formed over the entire surface.
도 1c를 참조하면, 상기 트렌치(17)를 매립하는 소자분리용 산화막(23)을 전체표면상부에 형성한다. Referring to FIG. 1C, an oxide layer 23 for forming an isolation layer for filling the trench 17 is formed on the entire surface.
상기 소자분리용 산화막(23)을 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 방법으로 상기 측벽 질화막(21) 또는 질화막(15)이 노출되도록 평탄화식각한다. The device isolation oxide film 23 is planarized by chemical mechanical polishing (hereinafter referred to as CMP) to expose the sidewall nitride film 21 or the nitride film 15.
도 1d를 참조하면, 인산용액을 이용한 습식방법으로 상기 측벽 질화막(21) 및 질화막(15)을 제거한다. Referring to FIG. 1D, the sidewall nitride film 21 and the nitride film 15 are removed by a wet method using a phosphoric acid solution.
이때, 상기 측벽 질화막(21)의 손실이 커지게 되어 ⓐ 와 같이 턱짐현상 ( moat ) 이 유발된다. At this time, the loss of the sidewall nitride film 21 is increased, causing a crush phenomenon (moat) as shown by ⓐ.
후속 공정으로, 상기 패드산화막(13)을 제거하는 습식 세정 공정을 실시하여 소자분리막을 형성한다. In a subsequent process, a wet cleaning process of removing the pad oxide layer 13 is performed to form an isolation layer.
상기한 바와 같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 턱짐현상의 유발로 인하여 전계의 집중에 의한 누설전류가 유발되고 그로 인한 소자의 특성 열화가 발생하며, 후속 공정을 어렵게 하여 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. As described above, in the method of forming a device isolation film of a semiconductor device according to the prior art, leakage current due to concentration of an electric field is caused by the occurrence of a jaw phenomena, resulting in deterioration of characteristics of the device, and making subsequent processing difficult. There is a problem in that the characteristics and reliability of the deterioration and thereby the high integration of the semiconductor device is difficult.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 패드산화막 상의 질화막 적층 공정없이 소자분리 공정을 진행하여 턱짐현상 ( moat ) 의 유발을 방지할 수 있도록 함으로써 후속 공정을 용이하게 하고 그에 따른 소자의 특성 열화를 방지할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art described above, the device separation process without the nitride film deposition process on the pad oxide film can be performed to prevent the occurrence of squeeze (moat), thereby facilitating subsequent processes and thereby It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device, which can prevent deterioration of characteristics, thereby improving characteristics and reliability of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은, In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
패드산화막이 형성된 반도체기판을 식각하여 소자분리용 트렌치를 형성하는 공정과,Forming a device isolation trench by etching the semiconductor substrate on which the pad oxide film is formed;
상기 소자분리용 트렌치 표면에 측벽 산화막을 형성하고 전체표면상부에 측벽 질화막을 형성하는 공정과,Forming a sidewall oxide film on the surface of the isolation trench and forming a sidewall nitride film over the entire surface thereof;
상기 트렌치를 매립하는 소자분리용 산화막을 전체표면상부에 형성하고 상기 측벽 질화막을 노출시키는 평탄화식각공정과,A planarization etching step of forming an isolation layer for filling the trench over the entire surface and exposing the sidewall nitride film;
상기 패드산화막 상부로 노출된 측벽 질화막을 제거하여 상기 패드산화막을 노출시키는 공정과,Exposing the pad oxide film by removing the sidewall nitride film exposed over the pad oxide film;
상기 노출된 패드산화막을 제거하여 반도체기판의 표면을 노출시키는 동시에 상기 반도체기판 상부로 돌출된 소자분리용 산화막과 그 측벽에 구비되는 측벽 질화막을 남기는 공정과,Removing the exposed pad oxide film to expose a surface of the semiconductor substrate, and leaving an oxide layer for device isolation protruding above the semiconductor substrate and a sidewall nitride film provided on the sidewalls;
상기 반도체기판 표면에 스크린 산화막을 형성하고 상기 측벽 질화막을 인산용액으로 제거하여 소자분리막을 형성하는 공정을 포함하는 것과,Forming a device isolation film by forming a screen oxide film on the surface of the semiconductor substrate and removing the sidewall nitride film with a phosphate solution;
상기 패드산화막은 400 ∼ 900 Å 두께로 형성하는 것과,The pad oxide film is formed to a thickness of 400 ~ 900 Å,
상기 측벽 산화막은 상기 트렌치 표면의 겸함을 제거하기 위한 열산화막의 형성 및 제거 공정후에 실시되되, 상기 열산화 공정은 700 ∼ 1200 ℃ 의 온도에서 실시하는 것과,The sidewall oxide film is carried out after the formation and removal of a thermal oxide film for removing the function of the trench surface, the thermal oxidation process is carried out at a temperature of 700 ~ 1200 ℃,
상기 측벽 산화막은 50 ∼ 150 Å 두께로 형성되는 것과,The sidewall oxide film is formed to a thickness of 50 to 150 kPa,
상기 측벽 질화막은 30 ∼ 100 Å 두께로 형성되는 것과,The sidewall nitride film is formed to a thickness of 30 to 100 mm 3,
상기 소자분리용 산화막은 패드산화막보다 1.5∼50 배로 식각선택비가 낮은 산화막인 것과,The device isolation oxide film is an oxide film having an etching selectivity lower than that of the pad oxide film by 1.5 to 50 times;
상기 패드산화막의 제거공정은 HF 용액이나 BOE ( buffered oxide etchant ) 용액을 이용하여 실시하는 것을 특징으로 한다. The pad oxide film removal process may be performed using HF solution or BOE (buffered oxide etchant) solution.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다. 2A through 2E are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체기판(31) 상에 패드산화막(33)을 형성한다. 이때, 상기 패드산화막(33)은 종래의 50 ∼ 150 Å 보다 두꺼운 400 ∼ 900 Å 두께로 형성한다. Referring to FIG. 2A, a pad oxide film 33 is formed on the semiconductor substrate 31. At this time, the pad oxide film 33 is formed to a thickness of 400 ~ 900 Å thicker than the conventional 50 ~ 150 Å.
소자분리마스크(도시안됨)를 이용한 사진식각공정으로 상기 패드산화막(33) 및 소정두께의 반도체기판(31)을 식각하여 트렌치(35)를 형성한다. A trench 35 is formed by etching the pad oxide layer 33 and the semiconductor substrate 31 having a predetermined thickness by a photolithography process using an element isolation mask (not shown).
도 2b를 참조하면, 상기 트렌치(35) 표면을 열산화시켜 열산화막(도시안됨)을 형성하고 이를 제거하여 트렌치(35)를 형성하기 위한 식각공정시 유발된 트렌치(35) 표면의 결함을 제거한다. 상기 열산화 공정은 700 ∼ 1200 ℃ 의 온도에서 실시한다. Referring to FIG. 2B, the surface of the trench 35 is thermally oxidized to form a thermal oxide layer (not shown) and to remove the defect, thereby removing defects on the surface of the trench 35 induced during the etching process for forming the trench 35. do. The said thermal oxidation process is performed at the temperature of 700-1200 degreeC.
상기 트렌치(35) 표면에 50 ∼ 150 Å 두께의 측벽 산화막(37)을 형성하고, 전체표면상부에 30 ∼ 100 Å 두께의 측벽 질화막(39)을 형성한다. A sidewall oxide film 37 having a thickness of 50 to 150 GPa is formed on the surface of the trench 35, and a sidewall nitride film 39 having a thickness of 30 to 100 GPa is formed on the entire surface.
도 2c를 참조하면, 상기 트렌치(35)를 매립하는 소자분리용 산화막(41)을 전체표면상부에 형성한다. 이때, 상기 소자분리용 산화막(41)은 패드산화막이 1.5∼50 배로 식각이 잘되는 산화막으로 형성한 것이다.Referring to FIG. 2C, an oxide layer 41 for isolation of the trench 35 is formed on the entire surface. In this case, the device isolation oxide film 41 is formed of an oxide film which is well etched with a pad oxide film 1.5 to 50 times.
상기 소자분리용 산화막(41)을 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 방법으로 평탄화식각하여 상기 측벽 질화막(39)을 노출시킨다. 이때, 상기 CMP 공정은 소자분리용 산화막(41)의 연마량이 상기 측벽 질화막(39)의 연마량보다 50 배 이상인 HSS ( high selectivity slurry ) 로 실시한다. The sidewall nitride film 39 is exposed by planarization etching of the device isolation oxide film 41 by chemical mechanical polishing (hereinafter, referred to as CMP). In this case, the CMP process is performed with a high selectivity slurry (HSS) having a polishing amount of at least 50 times the polishing amount of the sidewall nitride layer 39.
도 2d를 참조하면, 인산용액을 이용한 습식방법으로 상기 패드산화막(33) 상부에 형성된 상기 측벽 질화막(39)을 제거한다.Referring to FIG. 2D, the sidewall nitride layer 39 formed on the pad oxide layer 33 is removed by a wet method using a phosphoric acid solution.
상기 반도체기판(31) 상의 상기 패드산화막(33)을 식각하는 습식식각공정을 HF 용액이나 BOE 용액을 이용하여 실시한다. A wet etching process of etching the pad oxide layer 33 on the semiconductor substrate 31 is performed using an HF solution or a BOE solution.
이때, 상기 소자분리용 산화막(41)과 상기 패드산화막(33)은 1 : 1.5∼50 의 식각선택비 차이를 가지므로 패드산화막(33)의 식각속도가 빨라 소자분리용 산화막(41)은 거의 식각되지 않는다. At this time, since the device isolation oxide film 41 and the pad oxide film 33 have an etching selectivity difference of 1: 1.5 to 50, the etching rate of the pad oxide film 33 is fast, so that the device isolation oxide film 41 is almost It is not etched.
여기서, 상기 소자분리용 산화막(41)의 측벽에는 측벽 질화막(39)이 구비된다.Here, the sidewall nitride film 39 is provided on the sidewall of the isolation layer 41.
도 2e를 참조하면, 상기 반도체기판(31)의 표면을 산화시켜 스크린 산화막(43)을 형성하고 인산용액을 이용하여 상기 반도체기판(31) 상부로 돌출된 측벽 질화막(39)을 제거한다. 이때, 상기 측벽 질화막(39) 내측의 상기 소자분리용 산화막(41)이 동시에 제거되어 소자분리막(45)이 형성된다. Referring to FIG. 2E, the surface of the semiconductor substrate 31 is oxidized to form a screen oxide film 43, and the sidewall nitride film 39 protruding above the semiconductor substrate 31 is removed using a phosphoric acid solution. In this case, the device isolation oxide film 41 inside the sidewall nitride film 39 is simultaneously removed to form the device isolation film 45.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 식각하여야할 질화막의 두께를 종래보다 얇게 형성하여 질화막 식각시간을 감소시킴으로써 과도식각의 문제점을 방지하여 트렌치 측벽의 측벽 질화막 식각공정시 턱짐현상 ( moat )의 유발을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과를 제공한다. As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, the thickness of the nitride film to be etched is formed to be thinner than that of the prior art, thereby reducing the etching time of the nitride film, thereby preventing the problem of transient etching. It provides an effect that can prevent the occurrence of chin phenomena (moat) and thereby improve the characteristics and reliability of the semiconductor device.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 패드산화막11,31: semiconductor substrate 13,33: pad oxide film
15 : 질화막 17,35 : 트렌치15: nitride film 17,35: trench
19,37 : 측벽 산화막 21,39 : 측벽 질화막19,37 sidewall oxide film 21,39sidewall nitride film
23,41 : 소자분리용 산화막 43 : 스크린 산화막23,41: oxide film for device isolation 43: screen oxide film
45 : 소자분리막45: device isolation film
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