KR100510478B1 - Input circuit having delay dectector and data input method using the same - Google Patents

Abstract

An input circuit and a data input method using the same have been described which sufficiently compensates the phase difference between the reference signal and the data signal generated by the process error to minimize the speed loss. The input circuit according to the present invention inputs a reference signal and a data signal through a reference signal line and a data line, and drives an internal circuit by synchronizing the data signal with the input reference signal. The input circuit may include a plurality of delay units provided on the reference signal line for delaying and outputting the reference signal for a predetermined time, and comparing the signal transmission rates of the reference signal line and the data signal line, And a delay detection circuit for generating a plurality of detection signals that are selectively activated only for a delay time corresponding to.

Description

Input circuit having delay detection circuit and data input method using same {Input circuit having delay dectector and data input method using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an input circuit and a data input method using the same, which sufficiently compensate for a phase difference between a reference signal and a data signal generated by a process error to minimize speed loss.

The development trend of semiconductor memory devices is in the trend of high integration and high speed. In accordance with such a trend of high speed, a synchronous DRAM has been developed in which data input and output are controlled based on an external reference signal input from an external system or the like. The synchronous DRAM generates internal signals based on the internal reference signal generated by the transition of the external reference signal and controls data input / output operations. That is, the data signal is input to a specific internal circuit in synchronization with the generated internal reference signal.

However, in the conventional high speed semiconductor memory device, an internal reference signal is transmitted to a plurality of input / output circuits through a reference signal line. Similarly, data signals are delivered to a plurality of input / output circuits through specific data signal lines. In general, the reference signal line or the data signal line is formed of a metal line, and the load, that is, the parasitic resistance and the parasitic capacitance, varies depending on the length. As a result, the delay time generated from them varies according to the length of the reference signal line or the data signal line, which may cause a phase difference between the reference signal and the data signal transmitted to each input / output circuit.

In particular, when a process error occurs in the manufacturing process of the memory device due to the miniaturization of the device due to high integration, the phase difference between the reference signal and the data signal is more severe. The phase difference between the reference signal and the data signal results in a decrease in operating speed.

FIG. 1 is a diagram illustrating a configuration of a conventional input circuit, in which a reference signal is a clock signal and a data signal is an address signal.

Referring to FIG. 1, the input external clock signal CLK is generated as the internal clock signal PCLK through the clock buffer 110, and the address signal ADDR is internal through the address buffer 120. Is generated. The internal clock signal PCLK is transmitted through the clock line 112, and the internal address signal PADDR is transmitted through the address line 122.

The clock line 112 includes a delay circuit 114 to compensate for the speed difference compared to the address line 122. The delay clock signal output from the delay circuit 114 and the internal address signal PADDR transmitted through the address line are input to the logic circuits 116 and 126, and are logically combined to output the outputs OUT1 and OUT2.

FIG. 2 is a timing diagram of signals used in the input circuit shown in FIG. 1.

Referring to FIG. 2, when the external clock signal CLK is enabled at a high level, one input terminal A0 of the logic circuits 116 and 126 transitions to a low level in response thereto. When the address signal ADDR transitions to the high level, each of the other input terminals B0 and C0 of the logic circuits 116 and 126 transitions to the high and low levels. Data is output (OUT1, OUT2) by the combination of the level values of the input terminals (A0, B0, C0).

However, according to the conventional input circuit, a delay circuit 114 having a constant time delay is provided to compensate for a phase difference that may occur between the internal clock signal PCLK and the address signal ADDR. As described above, according to the conventional input circuit, since the delay time by the delay circuit 114 is fixed, the speed difference between the clock line 112 and the address line 122 generated due to the conventional process error is not sufficiently compensated. Is generated.

For example, when the delay time by the delay circuit 114 is too large, even if the internal address signal PADDR is first provided to the input terminals B0 and C0 of the respective logic circuits 116 and 126, the internal clock signal PCLK The data outputs OUT1 and OUT2 are not activated to the high level until they are activated to the high level, but only after a certain time TD.

That is, speed loss occurs until data outputs OUT1 and OUT2 are generated. On the contrary, when the delay time is small, a problem occurs that unwanted data outputs OUT1 and OUT2 are generated due to a malfunction.

Accordingly, an object of the present invention is to provide an input circuit of a semiconductor memory device which minimizes speed loss by sufficiently compensating the phase difference between a reference signal and a data signal generated by a process error.

Another object of the present invention is to provide a data input method using the input circuit.

The input circuit according to the present invention for achieving the above technical problem, inputs a reference signal and a data signal through a reference signal line and a data line, and drives the internal circuit by synchronizing the data signal to the input reference signal. The input circuit may include a plurality of delay units provided on the reference signal line for delaying and outputting the reference signal for a predetermined time, and comparing the signal transmission rates of the reference signal line and the data signal line, And a delay detection circuit for generating a plurality of detection signals that are selectively activated only for a delay time corresponding to.

According to a preferred embodiment of the present invention, the delay detection circuit includes a plurality of transmission units for selectively outputting data transmitted to the data line controlled by the output signal of each of the plurality of delay units, and the output of the transmission units. And a plurality of logic units for combining and outputting signals, each of the plurality of transmitters being selectively activated to have a delay time corresponding to a phase difference between the reference signal and the data signal transmitted to the reference signal line and the data line. .

The input circuit may include a delay compensation circuit configured to determine delay times by the plurality of delay units using detection signals generated through the delay detection circuit, an address signal generated through the data signal line, and the delay. The apparatus further includes a data input unit configured to generate a data output by combining the reference signals output through the compensation circuit.

The delay signal compensation circuit may include a plurality of fuses having one terminal connected to an output terminal of the plurality of delay units, another terminal connected to the data input unit in common, and having a connection state determined by the detection signal. can do.

According to another aspect of the present invention, a data input method includes comparing a signal transmission speed between a reference signal line and a data signal line, and selectively detecting a plurality of detection signals that are selectively activated only for delay times corresponding to these signal transmission speed differences. And a plurality of delay units provided in a reference signal line so as to have a delay time corresponding to the signal transmission speed difference using the selectively activated detection signal.

According to the input circuit of the present invention, speed loss is minimized until data output is generated. In addition, the low latency eliminates the risk of unwanted data output.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

FIG. 3 is a circuit diagram illustrating an input circuit of a semiconductor memory device having a delay detection circuit according to an exemplary embodiment of the present invention, and illustrates an example in which a reference signal is a clock signal and a data signal is an address signal.

Referring to FIG. 3, the signal input circuit 200 of the present invention includes a clock buffer 210 for converting an input external reference signal such as an external clock signal CLK into an internal reference signal such as an internal clock signal PCLK. A reference signal line for transmitting the internal clock signal PCLK generated in the clock buffer 210 may be provided, for example, a clock line 212. In addition, an address buffer 220 for converting an externally input data signal, for example, an address signal ADDR into an internal address signal PADDR, and a data signal line for transmitting the internal address signal PADDR, for example, an address line 222. And a plurality of first to third delay units 230, 232, and 234 provided on the clock line 212 to delay the internal clock signal PCLK for a predetermined time.

The input circuit 200 further includes a delay detection circuit 250 for generating a plurality of detection signals DET1, DET2, and DET3 by comparing the transmission rates of the clock line 212 and the address line 222. Equipped. Each of the detection signals DET1, DET2, and DET3 is selectively activated only for a delay time corresponding to the transmission rate difference.

That is, the delay detection circuit 250 detects a time delay difference generated between the clock line 212 and the address line 222 due to various factors generated during the manufacturing process of the memory device.

Preferably, the delay detection circuit 250 includes a plurality of first to third transmission units 252, 258 and 264, and a plurality of first to third logic units 270, 274 and 278.

The first to third transmitters 252, 258, and 264 are controlled by the output signals DL1, DL2, and DL3 of the first to third delay units 230, 232, and 234, respectively, and are transmitted to the address line 222. The signal PADDR is provided to the inputs of the first to third logic units 270, 274, and 278. Each of the first to third transmitters 252, 258, and 264 is selectively activated with respect to a transmission speed difference between the clock line 212 and the address line 222.

For example, when the transmission rate difference between the clock line 212 and the address line 222 is smaller than the delay time of the first delay unit 230, in other words, the output signal DL1 of the first delay unit 230 is different. When the signal DA passing through the address line reaches the input terminal of the logic units before activating, all of the first to third transmitters 252, 258, 264 are activated and the first logic unit 270 is activated. The detection signal DET1 is activated.

The transmission speed difference between the clock line 212 and the address line 222 is larger than the delay time of the first delay unit 230 and smaller than the delay time of the sum of the delay times of the first and second delay units 230 and 232. In other words, when the signal DA passing through the address line reaches the input terminal of the logic units before the output signal DL2 of the second delay unit 232 is activated, the first transmitter 252 is deactivated. The second and third transmitters 258 and 264 are activated to activate the second detection signal DET2 through the second logic unit 274.

In addition, a difference in transmission speed between the clock line 212 and the address line 222 is greater than the sum of the delay times of the first and second delay units 230 and 232, and the first to third delay units 230, 232, 234 of FIG. In other words, when the delay time is smaller than the sum of the delay times, in other words, when the signal DA passing through the address line reaches the input terminal of the logic units before the output signal DL3 of the third delay unit 234 is activated, The first and second transmitters 252 and 258 are deactivated and the third transmitter 264 is activated to activate the third detection signal DET3 through the third logic unit 278.

Each of the first to third transfer units may be implemented with one transfer gate 254, 260, 266 and latches 256, 262, 268.

The first to third logic units 270, 274, and 278 logically combine the output signals of the first to third transmission units 252, 258, and 264 to generate detection signals DET1, DET2, and DET3 that are selectively activated.

Preferably, the first to third logic units 270, 274, and 278 may be implemented as NOR gates.

The process of generating the detection signals DET1, DET2, and DET3 through the delay detection circuit 250 will be described with reference to FIGS. 4 to 6.

4 to 6 are timing diagrams of main signals used in the input circuit shown in FIG. 3, wherein the time delay generated in the address line 222 is smaller than the first delay time D1 (see FIG. 4). , Larger than the first delay time D1 and smaller than the second delay time D2 (see FIG. 5), and larger than the second delay time D2 and smaller than the third delay time D3 ( 6).

Here, the first delay time D1 is the sum of the time delays generated by the clock line 212 and the first delay unit 230, and the second delay time D2 is the clock line 212 and the second delay time. The sum of the time delays generated by the first delay unit 230 and the second delay unit 232, and the third delay time D3 is the clock line 212, the first delay unit 230, and the second delay. This is the sum of the time delays generated by the unit 232 and the third delay unit 234.

First, the case where the time delay generated in the address line 222 is smaller than the first delay time D1 will be described as an example.

3 and 4, the first to third delayed internal clock signals PCLK by the first to third delay times D1, D2, and D3 through the first to third delay units 230, 232, and 234, respectively. Delay signals DL1, DL2, and DL3 are generated.

The delay address signal DA having a time delay smaller than the first delay time D1 is input from the internal address signal PADDR through the address line 222. That is, after the delay address signal DA is activated at the high level, the output signal DL1 of the first delay unit 230 is activated at the high level.

Therefore, when the delay address signal DA is input, the output signals DL1, DL2, and DL3 of the first to third delay units 230, 232, and 234 all have a low level state. As a result, all of the transmission gates 254, 260, and 266 constituting the first to third transmitters 252, 258, and 264 are activated, and the delay address signal DA is at a low level in each of the first to third logic units 270, 274, and 278. It is entered as a state.

As a result, the output terminals A, B, and C of the first to third transmission units 252, 258, and 264 are all at low level, and the first detection signal DET1 is activated through the first logic unit 270.

Subsequently, the case where the time delay generated in the address line 222 is larger than the first delay time D1 and smaller than the second delay time D2 will be described with reference to FIGS. 3 and 5.

3 and 5, as described with reference to FIG. 4, the internal clock signal PCLK is configured to have the first to third delay times D1, D2, through the first to third delay units 230, 232, and 234, respectively. The first to third delay signals DL1, DL2, and DL3 delayed by D3) are generated. The delay address signal DA having a time delay greater than the first delay time D1 and smaller than the second delay time D2 is input from the internal address signal PADDR through the address line 222. That is, after the delay address signal DA is activated at the high level, the output signal DL2 of the second delay unit 232 is activated at the high level.

Therefore, when the delay address signal DA is input, the output signal DL1 of the first delay unit 230 has a high level and the output signals of the second and third delay units 232 and 234. DL2 and DL3 have a low level state.

As a result, the transmission gates 254 constituting the first transmission unit 252 are deactivated, and the transmission gates 260 and 266 constituting the second and third transmission units 258 and 264 are activated. As a result, the delay address signal DA is input to the first logic unit 270 at a high level and low to the second and third logic units 274 and 278.

As a result, the output terminal A of the first transmitter 252 is at a high level, and the output terminals B and C of the second and third transmitters 258 and 264 are at a low level. Through the second detection signal (DET2) is activated.

Finally, a case in which the time delay generated in the address line 222 is larger than the second delay time D2 and smaller than the third delay time D3 will be described with reference to FIGS. 3 and 6.

3 and 6, as described with reference to FIG. 4, the internal clock signal PCLK is configured to have the first to third delay times D1, D2, through the first to third delay units 230, 232, and 234, respectively. The first to third delay signals DL1, DL2, and DL3 delayed by D3) are generated. The delay address signal DA having a time delay greater than the second delay time D2 and smaller than the third delay time D3 is input from the internal address signal PADDR. That is, after the delay address signal DA is activated at the high level, the output signal DL3 of the third delay unit 234 is activated at the high level.

Therefore, when the delay address signal DA is input, the output signals DL1 and DL2 of the first and second delay units 230 and 234 have a high level, and the third delay unit 234 The output signal DL3 has a low level state.

As a result, the transmission gates 254 and 260 constituting the first and second transmission units 252 and 258 are deactivated, and the transmission gates 266 constituting the third transmission unit 264 are activated. As a result, the delay address signal DA is input to the first and second logic units 270 and 274 at a high level and to the third logic unit 278 at a low level.

As a result, the output terminals A and B of the first and second transmitters 252 and 258 are at a high level, and the output terminal C of the third transmitter 264 is at a low level. Through the third detection signal DET3 is activated.

FIG. 7 is a circuit diagram illustrating an input circuit of a memory device having a delay compensation circuit according to a preferred embodiment of the present invention, wherein the same reference numerals as in FIG. 3 denote the same members.

In addition to the delay detection circuit 250 illustrated in FIG. 3, the input circuit 200 of the present invention further includes a delay compensation circuit 280 and a data input unit 290.

The delay compensation circuit 280 determines the delay time by the first to third delay units 230, 232, and 234 using the detection signals DET1, DET2, and DET3 of the delay detection circuit 250.

Preferably, the delay compensation circuit 280 is implemented with a plurality of first to third fuses F1, F2, and F2, for example.

One terminal of each of the first to third fuses F1, F2, and FF3 is connected to an output terminal of the first to third delay units 230, 232, and 234. The other terminal is connected to one input of the data input unit 290.

The connection state of the first to third fuses F1, F2, and F2 is determined by the detection signals DET1, DET2, and DET3.

For example, when the first detection signal DET1 is activated, the first fuse F1 is connected and the second and third fuses F2 and F3 are cut off. As a result, the internal clock signal PCLK transmitted through the clock line 212 is input to the data input unit 290 through the first delay unit 230.

That is, when the transmission rate difference between the clock line 212 and the address line 222 is smaller than the delay time of the first delay unit 230, only the first delay unit 230 is connected, and thus the data outputs OUT1 and OUT2. The speed loss is minimized until this occurs. In addition, there is no fear of undesired data outputs OUT1 and OUT2 due to the short delay time.

In addition, when the second detection signal DET2 is activated, the second fuse F2 is connected and the first and third fuses F1 and F3 are cut off. As a result, the internal clock signal PCLK transmitted through the clock line 212 is input to the data input unit 290 through the first and second delay units 230 and 232.

That is, the transmission speed difference between the clock line 212 and the address line 222 is greater than the delay time of the first delay unit 230 and smaller than the delay time of the sum of the delay times of the first and second delay units 230 and 232. In this case, since the first and second delay units 230 and 232 are connected, the speed loss is minimized until the data outputs OUT1 and OUT2 are generated. In addition, there is no fear of undesired data outputs OUT1 and OUT2 due to the short delay time.

Similarly, for example, when the third detection signal DET3 is activated, the third fuse F3 is connected and the first and second fuses F1 and F2 are cut off. As a result, the internal clock signal PCLK transmitted through the clock line 212 is input to the data input unit 290 through the first, second, and third delay units 230, 232, and 234.

That is, the difference between the transmission speeds between the clock line 212 and the address line 222 is greater than the sum of the delay times of the first and second delay units 230 and 232, and the delay time of the first to third delay units 230, 232 and 234. If the sum is smaller than the sum delay time, the first, second and third delay parts 230, 232 and 234 are connected, so that the delay time is short, so that there is no fear that unwanted data outputs OUT1 and OUT2 are generated.

The data input unit 290 combines a delay address signal DA generated through the address line 222 and a clock signal output through the delay compensation circuit 280 to generate data outputs OUT1 and OUT2. Occurs.

Preferably, the data input unit 290 is implemented with NOR gates 292 and 296 that generate a high level signal when both input signals are at a low level. One input terminal of the NOR gates 292 and 296 is commonly connected to the other terminals of the first to third fuses F1, F2 and F3. Accordingly, the clock signal generated by the connection state of the first to third fuses F1, F2, and F3 is provided as one input signal of the NOR gates 292 and 296. In addition, the delay address signal DA and the delay address signal inverted are provided as other input signals of the NOR gates 292 and 296.

According to the input circuit according to the present invention, a delay detection circuit for generating detection signals selectively activated only for a delay time corresponding to a difference in transmission speed between a reference signal line and a data signal line is provided.

The connection relationship of the delay compensation circuit is controlled based on the detection signals generated by the delay detection circuit. Therefore, since the delay units corresponding to the delay time corresponding to the transmission speed difference between the reference signal line and the data signal line are selectively connected, the speed loss is minimized until the data outputs OUT1 and OUT2 are generated. In addition, there is no fear of undesired data outputs OUT1 and OUT2 due to the short delay time.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the input circuit according to the present invention, speed loss is minimized until data output occurs. In addition, the low latency eliminates the risk of unwanted data output.

1 is a view showing the configuration of a conventional general input circuit.

FIG. 2 is a timing diagram of signals used in the input circuit shown in FIG. 1.

3 is a circuit diagram illustrating an input circuit of a semiconductor memory device having a delay detection circuit according to an embodiment of the present invention.

4 through 6 are timing diagrams of main signals used in the input circuit shown in FIG.

7 is a circuit diagram illustrating an input circuit of a memory device having a delay compensation circuit according to a preferred embodiment of the present invention.

Claims (5)

An input circuit of a semiconductor device for inputting a reference signal and a data signal through a reference signal line and a data line, and driving an internal circuit by synchronizing the data signal with the input reference signal, A plurality of delay units provided on the reference signal line to delay and output the reference signal for a predetermined time; And And a delay detection circuit comparing the signal transmission speeds of the reference signal line and the data signal line and generating a plurality of detection signals selectively activated only for a delay time corresponding to the signal transmission speed difference. The method of claim 1, wherein the delay detection circuit, A plurality of transmitters selectively controlled by an output signal of each of the plurality of delay units to selectively output data transmitted to the data line; And And a plurality of logic units for combining and outputting the output signals of the transmitters, Each of the plurality of transmitters is selectively activated to have a delay time corresponding to a phase difference between a reference signal and a data signal transmitted to the reference signal line and the data line. The method of claim 1, wherein the input circuit, A delay compensation circuit configured to determine delay times by the plurality of delay units using detection signals generated through the delay detection circuit; And And a data input unit for generating a data output by combining an address signal generated through the data signal line and a reference signal output through the delay compensation circuit. The method of claim 3, wherein the delay signal compensation circuit, An input circuit having one terminal connected to an output terminal of the plurality of delay units, another terminal connected to the data input unit in common, and having a plurality of fuses whose connection state is determined by the detection signal. . A data input method of a semiconductor device for inputting a reference signal and a data signal through a reference signal line and a data line, and driving an internal circuit by synchronizing the data signal with the input reference signal. Comparing a signal transmission rate between the reference signal line and the data signal line and generating a plurality of detection signals selectively activated only for a delay time corresponding to the signal transmission rate difference; And And selectively connecting a plurality of delay units provided in a reference signal line to have a delay time corresponding to the signal transmission speed difference using the selectively activated detection signal.