KR100500920B1 - Voltage level shifter - Google Patents

Abstract

The present invention provides a voltage level shifter capable of operating at high speed. The present invention has a first pull-up driver and a first pull-down driver, and has a relatively large swing width for an input signal having a small swing width. Level changing means for changing to a signal having; A second pull-up driver for additionally driving up an output terminal of the level converting means; A second pull-down driver for additionally driving down the output terminal of the level converting means; Pull-up control means for enabling the second pull-up driver in the transition period of the input signal; And a pull-down control means for enabling the second pull-down driver in the transition period of the input signal.

Description

Voltage level shifter {VOLTAGE LEVEL SHIFTER}

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to a voltage level shifter.

In general, a pad for connecting the core inside the chip and the outside of the chip to increase the low output voltage of the core when interfacing between an internal chip operating at a low power supply voltage and an external system operating at a normal power supply voltage. Voltage level shifters are used between them. This interface exists between the core inside the chip and the pad for connecting the pin connecting the outside of the chip.

1 is a circuit diagram of a voltage level shifter according to the prior art.

Referring to FIG. 1, a voltage level shifter according to the related art is an inverter I1 for inverting an input signal IN and a level shifting for outputting an inverted high potential voltage level signal by inputting an inverted input signal. The unit 10 and the level shifting unit 11 are configured with an inverter I2 for inverting the output signal.

On the other hand, the driving voltage of the inverter I1 is the normal voltage VDD and the ground voltage VSS, and serves as an input buffer, and the driving voltage of the inverter I2 is the high potential voltage VPP and the ground voltage VSS. It acts as an output buffer. Therefore, it is the level shifting unit 10 to perform the actual voltage level shifting operation.

Specifically, the level shifting unit 10 has a drain-source path formed between an output node (A: 'input node') of the inverter and a gate of the PMOS transistor PM2. A drain-source path is formed between the NMOS transistor NM1 having the normal voltage VDD as a gate input, and the node of the ground voltage terminal VSS and the drain of the PMOS transistor PM2 (hereinafter referred to as an 'output node'). And a drain-source path is formed between the NMOS transistor NM2 having the input node voltage Va as a gate input, and the output node B and the high potential voltage terminal VPP, and the drain terminal of the NMOS transistor NM1. PMOS transistor PM2 having the voltage applied to C) as its gate input, and a drain-source path formed between node 'C' and the high potential voltage terminal VPP, and the PMOS having the input node voltage Vb as the gate input. It consists of the transistor PM1.

In addition, the transistors driving the output node B to the high potential voltage VPP or the ground voltage VSS are the PMOS transistor PM2 and the NMOS transistor NM2, respectively. In addition, the input node voltage Va of the level shifting unit 10 swings between the ground voltage VSS and the normal voltage VDD, and the output node voltage Vb is the ground voltage VSS and the high potential voltage VPP. Swing between). Therefore, in the following description, specific reference to the level of each node voltage is omitted.

Next, a detailed operation of the level shifting unit 10 will be described in a section in which a level transition of the input node voltage Va occurs.

Since the normal voltage VDD is always applied to the gate terminal of the NMOS transistor NM1, the NMOS transistor NM1 is always turned on.

First, the input node voltage Va transitions from logic level high to low.

As the input node voltage Va falls from the level high to the low, the NMOS transistor NM2 is turned off and the PMOS transistor PM2 starts to be turned on. By the operation of the transistors NM2 and PM2, the output node voltage Vb gradually rises, thereby turning off the PMOS transistor PM1, whereby the node 'C' has a stable logic level low. As a result, the NMOS transistor NM2 is turned off and the PMOS transistor PM2 is turned on to have a high logic level at which the output node voltage Vb is stable.

Next, the input node voltage Va transitions high from the logic level low.

As the input node voltage Va rises from the level low to the high, the NMOS transistor NM2 is turned on and the PMOS transistor PM2 starts to be turned off. When the output node voltage Vb gradually decreases due to the operation of each transistor NM2 or PM2, the PMOS transistor PM1 is turned on, whereby the high of the logic level of the high potential voltage VPP at which the node voltage Vc is stabilized is increased. Have As a result, the NMOS transistor NM2 is turned on and the PMOS transistor PM2 is turned off so that the output node voltage Vb has a stable logic level low.

FIG. 2 is an operation waveform diagram of the circuit of FIG. 1, through which the overall operation will be described. FIG.

First, since the input signal IN is stabilized at a logic level low, the input node voltage Va is maintained at a logic level high by the inverter I1, and the level shifting unit 10 controls the output node voltage Vb. Keep it low. The output signal OUT has a logic level low (part 'a' in FIG. 2).

Next, when the input signal IN transitions from the logic level low to the high, the input node voltage Va is shifted from the high to the low by the inverter I1, and the output node voltage (by the level shifting unit 10). Vb) transitions from low to high. The output signal OUT transitions from logic level high to low (part 'b' in FIG. 2).

Subsequently, since the input signal IN is stabilized at a logic level high, the input node voltage Va is held at a logic level low by the inverter I1, and the level shifting unit 10 adjusts the output node voltage Vb. Keep logic level high. The output signal OUT has a logic level low ('c' portion of FIG. 2).

Next, when the input signal IN transitions from logic level high to low, the input node voltage Va is shifted low to high by the inverter I1, and the output node voltage (by the level shifting unit 10). Vb) transitions from high to low. The output signal OUT transitions high from the logic level low (the 'd' portion of FIG. 2).

On the other hand, in the case of using the conventional technology, the driving speed of the voltage level shifter cannot be improved by increasing only the sizes of the transistors PM2 and NM2 driving the output node B. This is because when a voltage level transition occurs in the output node B, all the transistors connected to the output node B are turned on so that another transistor acts as a loading for the transistor driving the output node.

For example, while the output node voltage Vb transitions to logic level high, the NMOS transistor NM2 acts as a load for the PMOS transistor PM2 driving the output node voltage Vb. Therefore, even if the size of the transistor is increased, the driving speed cannot be improved.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a voltage level shifter capable of operating at high speed.

According to an aspect of the present invention for achieving the above technical problem, and having a first pull-up driver and a first pull-down driver, the level for changing an input signal having a small swing width to a signal having a relatively large swing width Change means; A second pull-up driver for additionally driving up an output terminal of the level converting means; A second pull-down driver for additionally driving down the output terminal of the level converting means; Pull-up control means for enabling the second pull-up driver in the transition period of the input signal; And a pull-down control means for enabling the second pull-down driver in the transition period of the input signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention.

Referring to FIG. 3, the voltage level shifter converts an inverter I1 for inverting the input signal IN and an input signal IN having a small swing width to an output signal OUT having a relatively large swing. A pull-up controller 30 for enabling the pull-up driver PM3 in the level shift period of the level shifting unit 10 and the input node voltage Va of the level shifting unit 10 for outputting; A pull-up driver PM3 controlled by the pull-up control unit 30 to additionally pull-up the output node B of the level shifting unit 10; A pull-down controller 31 for enabling the pull-down driver NM3 in the level transition period of the input node voltage Va of the level shifting unit 10; The pull-down driver NM3 for additionally pulling down the output node B of the level shifting unit 10 under the control of the pull-down control unit 31, and for inverting the output node voltage Vb of the level shifting unit 10. An inverter I2 is provided.

When comparing FIG. 3 with FIG. 1, it can be seen that the pull-up driver PM3 and the pull-down driver NM3, and the pull-up control unit 30 and the pull-down control unit 31 for controlling the same are added to FIG. 1. In addition, the same reference numerals are used for the same blocks, and thus detailed description thereof will be omitted.

The pull-up driver and the pull-down driver are preferably implemented with a PMOS transistor PM3 and an NMOS transistor NM3, respectively.

The pull-up control unit 30 transfers the input gate voltage Va to the gate of the PMOS transistor PM3 using the output node voltage Vb as a gate input, and the inverted output node voltage. It is implemented as a PMOS transistor PM4 for delivering a high potential voltage VPP to a gate of the PMOS transistor PM3 as a gate input.

The pull-down control unit 31 transfers the input gate voltage Va to the gate of the NMOS transistor NM3 using the output node voltage Vb as a gate input, and transfers the voltage of the inverted output node. The gate input is implemented as an NMOS transistor NM4 for transferring the ground voltage VSS to the gate of the NMOS transistor NM3.

Next, the overall operation of the voltage level shifter according to an embodiment of the present invention will be described.

First, when the input signal IN has a logic level low, since the input node voltage Va has a logic level high and the NMOS transistor NM2 is turned on, the output node voltage Vb transitions to a logic level low. Therefore, the output signal OUT becomes high of the high potential voltage level VPP.

At this time, when the input node voltage Va transitions from the logic level low to the high, the output gate voltage Vb has the previous logic level high, so that the transfer gate TG1 is enabled, and thereby the pull-down driver NM3. ) Turns on for a while to help the output node voltage (Vb) transition to a logic level low, thus improving speed.

On the other hand, when the input signal IN has a logic level high, the input node voltage Va has a logic level low such that the NMOS transistor NM2 is turned off and the PMOS transistor PM2 is turned on to output node voltage Vb. The high potential voltage level VPP transitions high. Therefore, the output signal OUT goes to the logic level low.

At this time, when the input node voltage Va transitions from the logic level high to the low, the transfer gate TG2 is enabled because the output node voltage Vb has the previous logic level low, and thereby the pull-up driver PM3. ) Is turned on for a while to help the output node voltage (Vb) transition to the high potential voltage level (VPP) high, thus improving the speed.

The voltage level shifter according to an embodiment of the present invention uses two transistors PM2, PM3, NM2, and NM3 that pull up and pull down the output node, respectively, and the additional transistors PM3, NM3 have transition periods of the input signal. Only active at and deactivated at other times reduces the output load.

In addition, the size of the pull-up driver (PM2) according to the prior art is the same as the size of two pull-up drivers (PM2, PM3) in accordance with an embodiment of the present invention, pull-down driver (NM2) is also an embodiment of the present invention Is equal to the size of two pull-down drivers NM2 and NM3.

FIG. 4A is a simulation result diagram illustrating a change in the output signal OUT when the input signal IN transitions from the logic level low to the high circuit in FIG. 3.

Referring to FIG. 4A, the X axis is the time axis and the scale is y, and the Y axis is the voltage axis and the scale is y. Reference numeral b denotes a level transition of the output node voltage according to the prior art, and a denotes a level transition of the output node voltage according to the present invention.

First, as the input signal IN transitions, the output signal OUT transitions from high to low at the high potential voltage VPP level. At this time, when comparing the conventional b and the a according to the present invention, from the point of time when the input signal IN transitions from low to high, the output signal OUT changes in response to the transition of the input signal IN. If you look at the time to point, it takes 0.5ns for b and 0.45ns for a. In conclusion, when the input signal IN transitions from low to high, the driving speed of the voltage level shifter according to the embodiment of the present invention is further improved by 0.05 ns compared with the related art.

FIG. 4B is a simulation result diagram illustrating a change in the output signal OUT when the input signal IN transitions from the logic level high to the low in the circuit of FIG. 3.

Since FIG. 4B has the same axis and symbol as FIG. 4A, a separate description is omitted.

First, as the voltage level of the input signal IN changes, the output signal OUT transitions from low to high of the high potential voltage VPP level. At this time, when comparing b according to the prior art and a according to the present invention, it takes 0.55 ns for b and 0.5 ns for a, so that the operating speed of the voltage level shifter according to the present invention is improved by 0.05 ns.

The present invention reduces the size of the transistors PM2 and NM2 driving the output node B, and additionally adds a pull-up driver PM3 and a pull-down driver NM3, while the added driver drives the output node B while driving. Only turned on and off. Therefore, the substantial size of the transistor driving the output node B is increased, and the loading of the output node B can be reduced, thereby improving the driving speed of the voltage level shifter.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The above-described present invention improves the driving speed of the voltage level shifter by 10% by adding pull-up and pull-down drivers which are driven only when the input signal transitions.

1 is a circuit diagram of a voltage level shifter according to the prior art.

2 is an operational waveform diagram of the circuit of FIG.

3 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention.

4A and 4B show simulation results of the circuit of FIG. 3.

* Description of the main parts of the drawing

30: pull-up drive unit

31: pull-down drive unit

Claims (5)

Level changing means having a first pull-up driver and a first pull-down driver, for changing an input signal having a small swing width to a signal having a relatively large swing width; A second pull-up driver for additionally driving up an output terminal of the level converting means; A second pull-down driver for additionally driving down the output terminal of the level converting means; Pull-up control means for enabling the second pull-up driver in the transition period of the input signal; And Pull-down control means for enabling the second pull-down driver in the transition period of the input signal; Voltage level shifter having a. The method of claim 1, The level change means, The first pull-down driver, a first NMOS transistor having a gate connected to an input terminal and having a source-drain path formed between a ground voltage terminal and the output terminal; A second NMOS transistor having a gate connected to a normal voltage terminal and a source connected to the input terminal; The first pull-up driver, a first PMOS transistor having a gate connected to the drain of the second NMOS transistor and having a source-drain path formed between a high potential voltage terminal and the output terminal; And And a second PMOS transistor having a gate connected to the output terminal and having a source-drain path formed between the high potential voltage terminal and the drain of the second NMOS transistor. The method of claim 2, The second pull-up driver includes a third PMOS transistor connected between the high potential voltage terminal and an output terminal of the level converting means, And said second pull-down driver comprises a third NMOS transistor connected between said ground voltage terminal and an output terminal of said level converting means. The method of claim 3, The pull-up control means, A first transfer gate for transferring the voltage at the input of the level converting means to the gate of the third PMOS transistor in response to the voltage at the output of the level converting means; And a fourth PMOS transistor having a source-drain path formed between the high potential voltage terminal and the gate of the third PMOS transistor as a gate input of a voltage inversion signal of the output terminal of the level converting means. Shifter. The method of claim 4, wherein The pull-down control means, A second transfer gate for transferring the voltage at the input of the level converting means to the gate of the third NMOS transistor in response to the voltage at the output of the level converting means; And a fourth NMOS transistor having a source-drain path formed between the ground voltage terminal and the gate of the third NMOS transistor as an input of an inverted signal of a voltage at an output terminal of the level converting means.